target/linux/at91/patches-5.10/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch

   1 From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 15 Apr 2021 13:49:55 +0300
   4 Subject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4
   5
   6 SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than
   7 MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of
   8 suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4.
   9
  10 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  11 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  12 Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com
  13 ---
  14  arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++---------
  15  1 file changed, 35 insertions(+), 13 deletions(-)
  16
  17 diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
  18 index 1f63bbfad728..7669b32d5257 100644
  19 --- a/arch/arm/mach-at91/pm_suspend.S
  20 +++ b/arch/arm/mach-at91/pm_suspend.S
  21 @@ -22,11 +22,23 @@ tmp3        .req    r6
  22
  23  /*
  24   * Wait until master clock is ready (after switching master clock source)
  25 + *
  26 + * @r_mckid:   register holding master clock identifier
  27 + *
  28 + * Side effects: overwrites r7, r8
  29   */
  30 -       .macro wait_mckrdy
  31 -1:     ldr     tmp1, [pmc, #AT91_PMC_SR]
  32 -       tst     tmp1, #AT91_PMC_MCKRDY
  33 -       beq     1b
  34 +       .macro wait_mckrdy r_mckid
  35 +#ifdef CONFIG_SOC_SAMA7
  36 +       cmp     \r_mckid, #0
  37 +       beq     1f
  38 +       mov     r7, #AT91_PMC_MCKXRDY
  39 +       b       2f
  40 +#endif
  41 +1:     mov     r7, #AT91_PMC_MCKRDY
  42 +2:     ldr     r8, [pmc, #AT91_PMC_SR]
  43 +       and     r8, r7
  44 +       cmp     r8, r7
  45 +       bne     2b
  46         .endm
  47
  48  /*
  49 @@ -231,7 +243,9 @@ sr_dis_exit:
  50         bic     tmp1, tmp1, #AT91_PMC_PRES
  51         orr     tmp1, tmp1, #AT91_PMC_PRES_64
  52         str     tmp1, [pmc, tmp3]
  53 -       wait_mckrdy
  54 +
  55 +       mov     tmp3, #0
  56 +       wait_mckrdy tmp3
  57         b       1f
  58
  59  0:
  60 @@ -267,10 +281,13 @@ sr_dis_exit:
  61         bne     5f
  62
  63         /* Set lowest prescaler for fast resume. */
  64 +       ldr     tmp3, .mckr_offset
  65         ldr     tmp1, [pmc, tmp3]
  66         bic     tmp1, tmp1, #AT91_PMC_PRES
  67         str     tmp1, [pmc, tmp3]
  68 -       wait_mckrdy
  69 +
  70 +       mov     tmp3, #0
  71 +       wait_mckrdy tmp3
  72         b       6f
  73
  74  5:     /* Restore RC oscillator state */
  75 @@ -307,6 +324,7 @@ sr_dis_exit:
  76  .macro at91_pm_ulp1_mode
  77         ldr     pmc, .pmc_base
  78         ldr     tmp2, .mckr_offset
  79 +       mov     tmp3, #0
  80
  81         /* Save RC oscillator state and check if it is enabled. */
  82         ldr     tmp1, [pmc, #AT91_PMC_SR]
  83 @@ -348,7 +366,7 @@ sr_dis_exit:
  84         orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
  85         str     tmp1, [pmc, tmp2]
  86
  87 -       wait_mckrdy
  88 +       wait_mckrdy tmp3
  89
  90         /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
  91         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
  92 @@ -361,7 +379,7 @@ sr_dis_exit:
  93         nop
  94         nop
  95
  96 -       wait_mckrdy
  97 +       wait_mckrdy tmp3
  98
  99         /* Enable the crystal oscillator */
 100         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 101 @@ -377,7 +395,7 @@ sr_dis_exit:
 102         bic     tmp1, tmp1, #AT91_PMC_CSS
 103         str     tmp1, [pmc, tmp2]
 104
 105 -       wait_mckrdy
 106 +       wait_mckrdy tmp3
 107
 108         /* Switch main clock source to crystal oscillator */
 109         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 110 @@ -394,7 +412,7 @@ sr_dis_exit:
 111         orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
 112         str     tmp1, [pmc, tmp2]
 113
 114 -       wait_mckrdy
 115 +       wait_mckrdy tmp3
 116
 117         /* Restore RC oscillator state */
 118         ldr     tmp1, .saved_osc_status
 119 @@ -573,10 +591,12 @@ sr_dis_exit:
 120  save_mck:
 121         str     tmp1, [pmc, tmp2]
 122
 123 -       wait_mckrdy
 124 +       mov     tmp3, #0
 125 +       wait_mckrdy tmp3
 126
 127         at91_plla_disable
 128
 129 +       ldr     tmp3, .pm_mode
 130         cmp     tmp3, #AT91_PM_ULP1
 131         beq     ulp1_mode
 132
 133 @@ -599,7 +619,8 @@ ulp_exit:
 134         ldr     tmp2, .saved_mckr
 135         str     tmp2, [pmc, tmp1]
 136
 137 -       wait_mckrdy
 138 +       mov     tmp3, #0
 139 +       wait_mckrdy tmp3
 140
 141  .endm
 142
 143 @@ -611,7 +632,8 @@ ulp_exit:
 144         bic     tmp1, tmp1, #AT91_PMC_CSS
 145         str     tmp1, [pmc, tmp2]
 146
 147 -       wait_mckrdy
 148 +       mov     tmp3, #0
 149 +       wait_mckrdy tmp3
 150
 151         /*BUMEN*/
 152         ldr     r0, .sfrbu
 153 --
 154 2.32.0
 155