1 From 1bfd85d71703f80392a71043caf74f159bec97b8 Mon Sep 17 00:00:00 2001
2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
3 Date: Thu, 15 Apr 2021 13:49:58 +0300
4 Subject: [PATCH 208/247] ARM: at91: pm: add self-refresh support for sama7g5
6 Add self-refresh support for SAMA7G5.
8 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
9 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
10 Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com
12 arch/arm/mach-at91/pm.h | 2 +
13 arch/arm/mach-at91/pm_data-offsets.c | 2 +
14 arch/arm/mach-at91/pm_suspend.S | 199 +++++++++++++++++++++++++++
15 3 files changed, 203 insertions(+)
17 diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
18 index bfb260be371e..666474088d55 100644
19 --- a/arch/arm/mach-at91/pm.h
20 +++ b/arch/arm/mach-at91/pm.h
22 #include <linux/mfd/syscon/atmel-mc.h>
23 #include <soc/at91/at91sam9_ddrsdr.h>
24 #include <soc/at91/at91sam9_sdramc.h>
25 +#include <soc/at91/sama7-ddr.h>
27 #define AT91_MEMCTRL_MC 0
28 #define AT91_MEMCTRL_SDRAMC 1
32 void __iomem *ramc[2];
33 + void __iomem *ramc_phy;
34 unsigned long uhp_udp_mask;
37 diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
38 index 82089ff258c0..40bd4e8fe40a 100644
39 --- a/arch/arm/mach-at91/pm_data-offsets.c
40 +++ b/arch/arm/mach-at91/pm_data-offsets.c
41 @@ -8,6 +8,8 @@ int main(void)
42 DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
43 DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
44 DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
45 + DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data,
47 DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
48 DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
49 DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc));
50 diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
51 index 7669b32d5257..84418120ba67 100644
52 --- a/arch/arm/mach-at91/pm_suspend.S
53 +++ b/arch/arm/mach-at91/pm_suspend.S
54 @@ -87,6 +87,200 @@ tmp3 .req r6
58 +#ifdef CONFIG_SOC_SAMA7
60 + * Enable self-refresh
62 + * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7
64 +.macro at91_sramc_self_refresh_ena
66 + ldr r3, .sramc_phy_base
71 + /* Disable all AXI ports. */
72 + ldr tmp1, [r2, #UDDRC_PCTRL_0]
73 + bic tmp1, tmp1, #0x1
74 + str tmp1, [r2, #UDDRC_PCTRL_0]
76 + ldr tmp1, [r2, #UDDRC_PCTRL_1]
77 + bic tmp1, tmp1, #0x1
78 + str tmp1, [r2, #UDDRC_PCTRL_1]
80 + ldr tmp1, [r2, #UDDRC_PCTRL_2]
81 + bic tmp1, tmp1, #0x1
82 + str tmp1, [r2, #UDDRC_PCTRL_2]
84 + ldr tmp1, [r2, #UDDRC_PCTRL_3]
85 + bic tmp1, tmp1, #0x1
86 + str tmp1, [r2, #UDDRC_PCTRL_3]
88 + ldr tmp1, [r2, #UDDRC_PCTRL_4]
89 + bic tmp1, tmp1, #0x1
90 + str tmp1, [r2, #UDDRC_PCTRL_4]
93 + /* Wait for all ports to disable. */
94 + ldr tmp1, [r2, #UDDRC_PSTAT]
95 + ldr tmp2, =UDDRC_PSTAT_ALL_PORTS
99 + /* Switch to self-refresh. */
100 + ldr tmp1, [r2, #UDDRC_PWRCTL]
101 + orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
102 + str tmp1, [r2, #UDDRC_PWRCTL]
105 + /* Wait for self-refresh enter. */
106 + ldr tmp1, [r2, #UDDRC_STAT]
107 + bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
108 + cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
111 + /* Put DDR PHY's DLL in bypass mode for non-backup modes. */
112 + cmp r7, #AT91_PM_BACKUP
114 + ldr tmp1, [r3, #DDR3PHY_PIR]
115 + orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
116 + str tmp1, [r3, #DDR3PHY_PIR]
119 + /* Power down DDR PHY data receivers. */
120 + ldr tmp1, [r3, #DDR3PHY_DXCCR]
121 + orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
122 + str tmp1, [r3, #DDR3PHY_DXCCR]
124 + /* Power down ADDR/CMD IO. */
125 + ldr tmp1, [r3, #DDR3PHY_ACIOCR]
126 + orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
127 + orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
128 + orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
129 + str tmp1, [r3, #DDR3PHY_ACIOCR]
131 + /* Power down ODT. */
132 + ldr tmp1, [r3, #DDR3PHY_DSGCR]
133 + orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
134 + str tmp1, [r3, #DDR3PHY_DSGCR]
138 + * Disable self-refresh
140 + * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3
142 +.macro at91_sramc_self_refresh_dis
143 + ldr r2, .sramc_base
144 + ldr r3, .sramc_phy_base
146 + /* Power up DDR PHY data receivers. */
147 + ldr tmp1, [r3, #DDR3PHY_DXCCR]
148 + bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
149 + str tmp1, [r3, #DDR3PHY_DXCCR]
151 + /* Power up the output of CK and CS pins. */
152 + ldr tmp1, [r3, #DDR3PHY_ACIOCR]
153 + bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
154 + bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
155 + bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
156 + str tmp1, [r3, #DDR3PHY_ACIOCR]
158 + /* Power up ODT. */
159 + ldr tmp1, [r3, #DDR3PHY_DSGCR]
160 + bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
161 + str tmp1, [r3, #DDR3PHY_DSGCR]
163 + /* Take DDR PHY's DLL out of bypass mode. */
164 + ldr tmp1, [r3, #DDR3PHY_PIR]
165 + bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
166 + str tmp1, [r3, #DDR3PHY_PIR]
168 + /* Enable quasi-dynamic programming. */
170 + str tmp1, [r2, #UDDRC_SWCTRL]
172 + /* De-assert SDRAM initialization. */
173 + ldr tmp1, [r2, #UDDRC_DFIMISC]
174 + bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
175 + str tmp1, [r2, #UDDRC_DFIMISC]
177 + /* Quasi-dynamic programming done. */
178 + mov tmp1, #UDDRC_SWCTRL_SW_DONE
179 + str tmp1, [r2, #UDDRC_SWCTRL]
182 + ldr tmp1, [r2, #UDDRC_SWSTAT]
183 + tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
186 + /* DLL soft-reset + DLL lock wait + ITM reset */
187 + mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
188 + DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST)
189 + str tmp1, [r3, #DDR3PHY_PIR]
193 + ldr tmp1, [r3, #DDR3PHY_PGSR]
194 + tst tmp1, #DDR3PHY_PGSR_IDONE
197 + /* Enable quasi-dynamic programming. */
199 + str tmp1, [r2, #UDDRC_SWCTRL]
201 + /* Assert PHY init complete enable signal. */
202 + ldr tmp1, [r2, #UDDRC_DFIMISC]
203 + orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
204 + str tmp1, [r2, #UDDRC_DFIMISC]
206 + /* Programming is done. Set sw_done. */
207 + mov tmp1, #UDDRC_SWCTRL_SW_DONE
208 + str tmp1, [r2, #UDDRC_SWCTRL]
212 + ldr tmp1, [r2, #UDDRC_SWSTAT]
213 + tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
216 + /* Trigger self-refresh exit. */
217 + ldr tmp1, [r2, #UDDRC_PWRCTL]
218 + bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
219 + str tmp1, [r2, #UDDRC_PWRCTL]
222 + /* Wait for self-refresh exit done. */
223 + ldr tmp1, [r2, #UDDRC_STAT]
224 + bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
225 + cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL
228 + /* Enable all AXI ports. */
229 + ldr tmp1, [r2, #UDDRC_PCTRL_0]
230 + orr tmp1, tmp1, #0x1
231 + str tmp1, [r2, #UDDRC_PCTRL_0]
233 + ldr tmp1, [r2, #UDDRC_PCTRL_1]
234 + orr tmp1, tmp1, #0x1
235 + str tmp1, [r2, #UDDRC_PCTRL_1]
237 + ldr tmp1, [r2, #UDDRC_PCTRL_2]
238 + orr tmp1, tmp1, #0x1
239 + str tmp1, [r2, #UDDRC_PCTRL_2]
241 + ldr tmp1, [r2, #UDDRC_PCTRL_3]
242 + orr tmp1, tmp1, #0x1
243 + str tmp1, [r2, #UDDRC_PCTRL_3]
245 + ldr tmp1, [r2, #UDDRC_PCTRL_4]
246 + orr tmp1, tmp1, #0x1
247 + str tmp1, [r2, #UDDRC_PCTRL_4]
253 * Enable self-refresh
255 @@ -228,6 +422,7 @@ sdramc_exit_sf:
261 .macro at91_pm_ulp0_mode
263 @@ -668,6 +863,8 @@ ENTRY(at91_pm_suspend_in_sram)
264 str tmp1, .sramc_base
265 ldr tmp1, [r0, #PM_DATA_RAMC1]
266 str tmp1, .sramc1_base
267 + ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
268 + str tmp1, .sramc_phy_base
269 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
271 ldr tmp1, [r0, #PM_DATA_MODE]
272 @@ -721,6 +918,8 @@ ENDPROC(at91_pm_suspend_in_sram)