1 From 1bfd85d71703f80392a71043caf74f159bec97b8 Mon Sep 17 00:00:00 2001
2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
3 Date: Thu, 15 Apr 2021 13:49:58 +0300
4 Subject: [PATCH 208/247] ARM: at91: pm: add self-refresh support for sama7g5
6 Add self-refresh support for SAMA7G5.
8 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
9 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
10 Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com
12 arch/arm/mach-at91/pm.h | 2 +
13 arch/arm/mach-at91/pm_data-offsets.c | 2 +
14 arch/arm/mach-at91/pm_suspend.S | 199 +++++++++++++++++++++++++++
15 3 files changed, 203 insertions(+)
17 --- a/arch/arm/mach-at91/pm.h
18 +++ b/arch/arm/mach-at91/pm.h
20 #include <linux/mfd/syscon/atmel-mc.h>
21 #include <soc/at91/at91sam9_ddrsdr.h>
22 #include <soc/at91/at91sam9_sdramc.h>
23 +#include <soc/at91/sama7-ddr.h>
25 #define AT91_MEMCTRL_MC 0
26 #define AT91_MEMCTRL_SDRAMC 1
30 void __iomem *ramc[2];
31 + void __iomem *ramc_phy;
32 unsigned long uhp_udp_mask;
35 --- a/arch/arm/mach-at91/pm_data-offsets.c
36 +++ b/arch/arm/mach-at91/pm_data-offsets.c
37 @@ -8,6 +8,8 @@ int main(void)
38 DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
39 DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
40 DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
41 + DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data,
43 DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
44 DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
45 DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc));
46 --- a/arch/arm/mach-at91/pm_suspend.S
47 +++ b/arch/arm/mach-at91/pm_suspend.S
48 @@ -87,6 +87,200 @@ tmp3 .req r6
52 +#ifdef CONFIG_SOC_SAMA7
54 + * Enable self-refresh
56 + * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7
58 +.macro at91_sramc_self_refresh_ena
60 + ldr r3, .sramc_phy_base
65 + /* Disable all AXI ports. */
66 + ldr tmp1, [r2, #UDDRC_PCTRL_0]
67 + bic tmp1, tmp1, #0x1
68 + str tmp1, [r2, #UDDRC_PCTRL_0]
70 + ldr tmp1, [r2, #UDDRC_PCTRL_1]
71 + bic tmp1, tmp1, #0x1
72 + str tmp1, [r2, #UDDRC_PCTRL_1]
74 + ldr tmp1, [r2, #UDDRC_PCTRL_2]
75 + bic tmp1, tmp1, #0x1
76 + str tmp1, [r2, #UDDRC_PCTRL_2]
78 + ldr tmp1, [r2, #UDDRC_PCTRL_3]
79 + bic tmp1, tmp1, #0x1
80 + str tmp1, [r2, #UDDRC_PCTRL_3]
82 + ldr tmp1, [r2, #UDDRC_PCTRL_4]
83 + bic tmp1, tmp1, #0x1
84 + str tmp1, [r2, #UDDRC_PCTRL_4]
87 + /* Wait for all ports to disable. */
88 + ldr tmp1, [r2, #UDDRC_PSTAT]
89 + ldr tmp2, =UDDRC_PSTAT_ALL_PORTS
93 + /* Switch to self-refresh. */
94 + ldr tmp1, [r2, #UDDRC_PWRCTL]
95 + orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
96 + str tmp1, [r2, #UDDRC_PWRCTL]
99 + /* Wait for self-refresh enter. */
100 + ldr tmp1, [r2, #UDDRC_STAT]
101 + bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
102 + cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
105 + /* Put DDR PHY's DLL in bypass mode for non-backup modes. */
106 + cmp r7, #AT91_PM_BACKUP
108 + ldr tmp1, [r3, #DDR3PHY_PIR]
109 + orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
110 + str tmp1, [r3, #DDR3PHY_PIR]
113 + /* Power down DDR PHY data receivers. */
114 + ldr tmp1, [r3, #DDR3PHY_DXCCR]
115 + orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
116 + str tmp1, [r3, #DDR3PHY_DXCCR]
118 + /* Power down ADDR/CMD IO. */
119 + ldr tmp1, [r3, #DDR3PHY_ACIOCR]
120 + orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
121 + orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
122 + orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
123 + str tmp1, [r3, #DDR3PHY_ACIOCR]
125 + /* Power down ODT. */
126 + ldr tmp1, [r3, #DDR3PHY_DSGCR]
127 + orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
128 + str tmp1, [r3, #DDR3PHY_DSGCR]
132 + * Disable self-refresh
134 + * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3
136 +.macro at91_sramc_self_refresh_dis
137 + ldr r2, .sramc_base
138 + ldr r3, .sramc_phy_base
140 + /* Power up DDR PHY data receivers. */
141 + ldr tmp1, [r3, #DDR3PHY_DXCCR]
142 + bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
143 + str tmp1, [r3, #DDR3PHY_DXCCR]
145 + /* Power up the output of CK and CS pins. */
146 + ldr tmp1, [r3, #DDR3PHY_ACIOCR]
147 + bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
148 + bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
149 + bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
150 + str tmp1, [r3, #DDR3PHY_ACIOCR]
152 + /* Power up ODT. */
153 + ldr tmp1, [r3, #DDR3PHY_DSGCR]
154 + bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
155 + str tmp1, [r3, #DDR3PHY_DSGCR]
157 + /* Take DDR PHY's DLL out of bypass mode. */
158 + ldr tmp1, [r3, #DDR3PHY_PIR]
159 + bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
160 + str tmp1, [r3, #DDR3PHY_PIR]
162 + /* Enable quasi-dynamic programming. */
164 + str tmp1, [r2, #UDDRC_SWCTRL]
166 + /* De-assert SDRAM initialization. */
167 + ldr tmp1, [r2, #UDDRC_DFIMISC]
168 + bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
169 + str tmp1, [r2, #UDDRC_DFIMISC]
171 + /* Quasi-dynamic programming done. */
172 + mov tmp1, #UDDRC_SWCTRL_SW_DONE
173 + str tmp1, [r2, #UDDRC_SWCTRL]
176 + ldr tmp1, [r2, #UDDRC_SWSTAT]
177 + tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
180 + /* DLL soft-reset + DLL lock wait + ITM reset */
181 + mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
182 + DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST)
183 + str tmp1, [r3, #DDR3PHY_PIR]
187 + ldr tmp1, [r3, #DDR3PHY_PGSR]
188 + tst tmp1, #DDR3PHY_PGSR_IDONE
191 + /* Enable quasi-dynamic programming. */
193 + str tmp1, [r2, #UDDRC_SWCTRL]
195 + /* Assert PHY init complete enable signal. */
196 + ldr tmp1, [r2, #UDDRC_DFIMISC]
197 + orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
198 + str tmp1, [r2, #UDDRC_DFIMISC]
200 + /* Programming is done. Set sw_done. */
201 + mov tmp1, #UDDRC_SWCTRL_SW_DONE
202 + str tmp1, [r2, #UDDRC_SWCTRL]
206 + ldr tmp1, [r2, #UDDRC_SWSTAT]
207 + tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
210 + /* Trigger self-refresh exit. */
211 + ldr tmp1, [r2, #UDDRC_PWRCTL]
212 + bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
213 + str tmp1, [r2, #UDDRC_PWRCTL]
216 + /* Wait for self-refresh exit done. */
217 + ldr tmp1, [r2, #UDDRC_STAT]
218 + bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
219 + cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL
222 + /* Enable all AXI ports. */
223 + ldr tmp1, [r2, #UDDRC_PCTRL_0]
224 + orr tmp1, tmp1, #0x1
225 + str tmp1, [r2, #UDDRC_PCTRL_0]
227 + ldr tmp1, [r2, #UDDRC_PCTRL_1]
228 + orr tmp1, tmp1, #0x1
229 + str tmp1, [r2, #UDDRC_PCTRL_1]
231 + ldr tmp1, [r2, #UDDRC_PCTRL_2]
232 + orr tmp1, tmp1, #0x1
233 + str tmp1, [r2, #UDDRC_PCTRL_2]
235 + ldr tmp1, [r2, #UDDRC_PCTRL_3]
236 + orr tmp1, tmp1, #0x1
237 + str tmp1, [r2, #UDDRC_PCTRL_3]
239 + ldr tmp1, [r2, #UDDRC_PCTRL_4]
240 + orr tmp1, tmp1, #0x1
241 + str tmp1, [r2, #UDDRC_PCTRL_4]
247 * Enable self-refresh
249 @@ -228,6 +422,7 @@ sdramc_exit_sf:
255 .macro at91_pm_ulp0_mode
257 @@ -668,6 +863,8 @@ ENTRY(at91_pm_suspend_in_sram)
258 str tmp1, .sramc_base
259 ldr tmp1, [r0, #PM_DATA_RAMC1]
260 str tmp1, .sramc1_base
261 + ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
262 + str tmp1, .sramc_phy_base
263 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
265 ldr tmp1, [r0, #PM_DATA_MODE]
266 @@ -721,6 +918,8 @@ ENDPROC(at91_pm_suspend_in_sram)