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kernel: bump 5.10 to 5.10.103
[openwrt/staging/dangole.git] / target / linux / at91 / patches-5.10 / 222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch
1 From 969b39d51b7df0869cca9983b06cefb59dae72b0 Mon Sep 17 00:00:00 2001
2 From: Eugen Hristev <eugen.hristev@microchip.com>
3 Date: Mon, 28 Jun 2021 15:04:50 +0300
4 Subject: [PATCH 222/247] ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek
5
6 Add Device Tree for sama7g5 SoC and associated board sama7g5-ek
7
8 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
9 [claudiu.beznea@microchip.com: add clocks, ethernet, timers, power]
10 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
11 [codrin.ciubotariu@microchip.com: add audio]
12 Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
13 [nicolas.ferre@microchip.com: removed eeproms, reorder i2s dma chans]
14 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
15 Link: https://lore.kernel.org/r/20210628120452.74408-2-eugen.hristev@microchip.com
16 [claudiu.beznea: adapt to kernel v5.10]
17 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
18 ---
19 arch/arm/boot/dts/Makefile | 2 +
20 arch/arm/boot/dts/at91-sama7g5ek.dts | 656 +++++++++++++++++++
21 arch/arm/boot/dts/sama7g5-pinfunc.h | 923 +++++++++++++++++++++++++++
22 arch/arm/boot/dts/sama7g5.dtsi | 528 +++++++++++++++
23 4 files changed, 2109 insertions(+)
24 create mode 100644 arch/arm/boot/dts/at91-sama7g5ek.dts
25 create mode 100644 arch/arm/boot/dts/sama7g5-pinfunc.h
26 create mode 100644 arch/arm/boot/dts/sama7g5.dtsi
27
28 --- a/arch/arm/boot/dts/Makefile
29 +++ b/arch/arm/boot/dts/Makefile
30 @@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += \
31 atlas6-evb.dtb
32 dtb-$(CONFIG_ARCH_ATLAS7) += \
33 atlas7-evb.dtb
34 +dtb-$(CONFIG_SOC_SAMA7G5) += \
35 + at91-sama7g5ek.dtb
36 dtb-$(CONFIG_ARCH_AXXIA) += \
37 axm5516-amarillo.dtb
38 dtb-$(CONFIG_ARCH_BCM2835) += \
39 --- /dev/null
40 +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
41 @@ -0,0 +1,656 @@
42 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
43 +/*
44 + * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board
45 + *
46 + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries
47 + *
48 + * Author: Eugen Hristev <eugen.hristev@microchip.com>
49 + * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
50 + *
51 + */
52 +/dts-v1/;
53 +#include "sama7g5-pinfunc.h"
54 +#include "sama7g5.dtsi"
55 +#include <dt-bindings/mfd/atmel-flexcom.h>
56 +#include <dt-bindings/input/input.h>
57 +
58 +/ {
59 + model = "Microchip SAMA7G5-EK";
60 + compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7";
61 +
62 + chosen {
63 + bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait";
64 + stdout-path = "serial0:115200n8";
65 + };
66 +
67 + aliases {
68 + serial0 = &uart3;
69 + serial1 = &uart4;
70 + serial2 = &uart7;
71 + serial3 = &uart0;
72 + i2c0 = &i2c1;
73 + i2c1 = &i2c8;
74 + i2c2 = &i2c9;
75 + };
76 +
77 + clocks {
78 + slow_xtal {
79 + clock-frequency = <32768>;
80 + };
81 +
82 + main_xtal {
83 + clock-frequency = <24000000>;
84 + };
85 + };
86 +
87 + gpio_keys {
88 + compatible = "gpio-keys";
89 +
90 + pinctrl-names = "default";
91 + pinctrl-0 = <&pinctrl_key_gpio_default>;
92 +
93 + bp1 {
94 + label = "PB_USER";
95 + gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;
96 + linux,code = <KEY_PROG1>;
97 + wakeup-source;
98 + };
99 + };
100 +
101 + leds {
102 + compatible = "gpio-leds";
103 + pinctrl-names = "default";
104 + pinctrl-0 = <&pinctrl_led_gpio_default>;
105 + status = "okay"; /* Conflict with pwm. */
106 +
107 + red_led {
108 + label = "red";
109 + gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
110 + };
111 +
112 + green_led {
113 + label = "green";
114 + gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>;
115 + };
116 +
117 + blue_led {
118 + label = "blue";
119 + gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>;
120 + linux,default-trigger = "heartbeat";
121 + };
122 + };
123 +
124 + /* 512 M */
125 + memory@60000000 {
126 + device_type = "memory";
127 + reg = <0x60000000 0x20000000>;
128 + };
129 +
130 + sound: sound {
131 + compatible = "simple-audio-card";
132 + simple-audio-card,name = "sama7g5ek audio";
133 + #address-cells = <1>;
134 + #size-cells = <0>;
135 + simple-audio-card,dai-link@0 {
136 + reg = <0>;
137 + cpu {
138 + sound-dai = <&spdiftx>;
139 + };
140 + codec {
141 + sound-dai = <&spdif_out>;
142 + };
143 + };
144 + simple-audio-card,dai-link@1 {
145 + reg = <1>;
146 + cpu {
147 + sound-dai = <&spdifrx>;
148 + };
149 + codec {
150 + sound-dai = <&spdif_in>;
151 + };
152 + };
153 + };
154 +
155 + spdif_in: spdif-in {
156 + #sound-dai-cells = <0>;
157 + compatible = "linux,spdif-dir";
158 + };
159 +
160 + spdif_out: spdif-out {
161 + #sound-dai-cells = <0>;
162 + compatible = "linux,spdif-dit";
163 + };
164 +};
165 +
166 +&cpu0 {
167 + cpu-supply = <&vddcpu>;
168 +};
169 +
170 +&dma0 {
171 + status = "okay";
172 +};
173 +
174 +&dma1 {
175 + status = "okay";
176 +};
177 +
178 +&dma2 {
179 + status = "okay";
180 +};
181 +
182 +&flx0 {
183 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
184 + status = "disabled";
185 +
186 + uart0: serial@200 {
187 + pinctrl-names = "default";
188 + pinctrl-0 = <&pinctrl_flx0_default>;
189 + status = "disabled";
190 + };
191 +};
192 +
193 +&flx1 {
194 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
195 + status = "okay";
196 +
197 + i2c1: i2c@600 {
198 + pinctrl-names = "default";
199 + pinctrl-0 = <&pinctrl_i2c1_default>;
200 + i2c-analog-filter;
201 + i2c-digital-filter;
202 + i2c-digital-filter-width-ns = <35>;
203 + status = "okay";
204 +
205 + mcp16502@5b {
206 + compatible = "microchip,mcp16502";
207 + reg = <0x5b>;
208 + status = "okay";
209 +
210 + regulators {
211 + vdd_3v3: VDD_IO {
212 + regulator-name = "VDD_IO";
213 + regulator-min-microvolt = <1200000>;
214 + regulator-max-microvolt = <3700000>;
215 + regulator-initial-mode = <2>;
216 + regulator-allowed-modes = <2>, <4>;
217 + regulator-always-on;
218 +
219 + regulator-state-standby {
220 + regulator-on-in-suspend;
221 + regulator-mode = <4>;
222 + };
223 +
224 + regulator-state-mem {
225 + regulator-off-in-suspend;
226 + regulator-mode = <4>;
227 + };
228 + };
229 +
230 + vddioddr: VDD_DDR {
231 + regulator-name = "VDD_DDR";
232 + regulator-min-microvolt = <1300000>;
233 + regulator-max-microvolt = <1450000>;
234 + regulator-initial-mode = <2>;
235 + regulator-allowed-modes = <2>, <4>;
236 + regulator-always-on;
237 +
238 + regulator-state-standby {
239 + regulator-on-in-suspend;
240 + regulator-mode = <4>;
241 + };
242 +
243 + regulator-state-mem {
244 + regulator-on-in-suspend;
245 + regulator-mode = <4>;
246 + };
247 + };
248 +
249 + vddcore: VDD_CORE {
250 + regulator-name = "VDD_CORE";
251 + regulator-min-microvolt = <1100000>;
252 + regulator-max-microvolt = <1850000>;
253 + regulator-initial-mode = <2>;
254 + regulator-allowed-modes = <2>, <4>;
255 + regulator-always-on;
256 +
257 + regulator-state-standby {
258 + regulator-on-in-suspend;
259 + regulator-mode = <4>;
260 + };
261 +
262 + regulator-state-mem {
263 + regulator-off-in-suspend;
264 + regulator-mode = <4>;
265 + };
266 + };
267 +
268 + vddcpu: VDD_OTHER {
269 + regulator-name = "VDD_OTHER";
270 + regulator-min-microvolt = <1125000>;
271 + regulator-max-microvolt = <1850000>;
272 + regulator-initial-mode = <2>;
273 + regulator-allowed-modes = <2>, <4>;
274 + regulator-ramp-delay = <3125>;
275 + regulator-always-on;
276 +
277 + regulator-state-standby {
278 + regulator-on-in-suspend;
279 + regulator-mode = <4>;
280 + };
281 +
282 + regulator-state-mem {
283 + regulator-off-in-suspend;
284 + regulator-mode = <4>;
285 + };
286 + };
287 +
288 + vldo1: LDO1 {
289 + regulator-name = "LDO1";
290 + regulator-min-microvolt = <1200000>;
291 + regulator-max-microvolt = <3700000>;
292 + regulator-always-on;
293 +
294 + regulator-state-standby {
295 + regulator-on-in-suspend;
296 + };
297 +
298 + regulator-state-mem {
299 + regulator-off-in-suspend;
300 + };
301 + };
302 +
303 + vldo2: LDO2 {
304 + regulator-name = "LDO2";
305 + regulator-min-microvolt = <1200000>;
306 + regulator-max-microvolt = <3700000>;
307 +
308 + regulator-state-standby {
309 + regulator-on-in-suspend;
310 + };
311 +
312 + regulator-state-mem {
313 + regulator-off-in-suspend;
314 + };
315 + };
316 + };
317 + };
318 + };
319 +};
320 +
321 +&flx3 {
322 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
323 + status = "okay";
324 +
325 + uart3: serial@200 {
326 + pinctrl-names = "default";
327 + pinctrl-0 = <&pinctrl_flx3_default>;
328 + status = "okay";
329 + };
330 +};
331 +
332 +&flx4 {
333 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
334 + status = "okay";
335 +
336 + uart4: serial@200 {
337 + pinctrl-names = "default";
338 + pinctrl-0 = <&pinctrl_flx4_default>;
339 + status = "okay";
340 + };
341 +};
342 +
343 +&flx7 {
344 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
345 + status = "okay";
346 +
347 + uart7: serial@200 {
348 + pinctrl-names = "default";
349 + pinctrl-0 = <&pinctrl_flx7_default>;
350 + status = "okay";
351 + };
352 +};
353 +
354 +&flx8 {
355 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
356 + status = "okay";
357 +
358 + i2c8: i2c@600 {
359 + pinctrl-names = "default";
360 + pinctrl-0 = <&pinctrl_i2c8_default>;
361 + i2c-analog-filter;
362 + i2c-digital-filter;
363 + i2c-digital-filter-width-ns = <35>;
364 + status = "okay";
365 + };
366 +};
367 +
368 +&flx9 {
369 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
370 + status = "okay";
371 +
372 + i2c9: i2c@600 {
373 + pinctrl-names = "default";
374 + pinctrl-0 = <&pinctrl_i2c9_default>;
375 + i2c-analog-filter;
376 + i2c-digital-filter;
377 + i2c-digital-filter-width-ns = <35>;
378 + status = "okay";
379 + };
380 +};
381 +
382 +&flx11 {
383 + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
384 + status = "okay";
385 +
386 + spi11: spi@400 {
387 + pinctrl-names = "default";
388 + pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>;
389 + status = "okay";
390 + };
391 +};
392 +
393 +&gmac0 {
394 + #address-cells = <1>;
395 + #size-cells = <0>;
396 + pinctrl-names = "default";
397 + pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;
398 + phy-mode = "rgmii-id";
399 + status = "okay";
400 +
401 + ethernet-phy@7 {
402 + reg = <0x7>;
403 + interrupt-parent = <&pioA>;
404 + interrupts = <PIN_PA31 IRQ_TYPE_LEVEL_LOW>;
405 + };
406 +};
407 +
408 +&gmac1 {
409 + #address-cells = <1>;
410 + #size-cells = <0>;
411 + pinctrl-names = "default";
412 + pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;
413 + phy-mode = "rmii";
414 + status = "okay";
415 +
416 + ethernet-phy@0 {
417 + reg = <0x0>;
418 + interrupt-parent = <&pioA>;
419 + interrupts = <PIN_PA21 IRQ_TYPE_LEVEL_LOW>;
420 + };
421 +};
422 +
423 +&i2s0 {
424 + pinctrl-names = "default";
425 + pinctrl-0 = <&pinctrl_i2s0_default>;
426 +};
427 +
428 +&pioA {
429 + pinctrl_flx0_default: flx0_default {
430 + pinmux = <PIN_PE3__FLEXCOM0_IO0>,
431 + <PIN_PE4__FLEXCOM0_IO1>,
432 + <PIN_PE6__FLEXCOM0_IO3>,
433 + <PIN_PE7__FLEXCOM0_IO4>;
434 + bias-disable;
435 + };
436 +
437 + pinctrl_flx3_default: flx3_default {
438 + pinmux = <PIN_PD16__FLEXCOM3_IO0>,
439 + <PIN_PD17__FLEXCOM3_IO1>;
440 + bias-disable;
441 + };
442 +
443 + pinctrl_flx4_default: flx4_default {
444 + pinmux = <PIN_PD18__FLEXCOM4_IO0>,
445 + <PIN_PD19__FLEXCOM4_IO1>;
446 + bias-disable;
447 + };
448 +
449 + pinctrl_flx7_default: flx7_default {
450 + pinmux = <PIN_PC23__FLEXCOM7_IO0>,
451 + <PIN_PC24__FLEXCOM7_IO1>;
452 + bias-disable;
453 + };
454 +
455 + pinctrl_gmac0_default: gmac0_default {
456 + pinmux = <PIN_PA16__G0_TX0>,
457 + <PIN_PA17__G0_TX1>,
458 + <PIN_PA26__G0_TX2>,
459 + <PIN_PA27__G0_TX3>,
460 + <PIN_PA19__G0_RX0>,
461 + <PIN_PA20__G0_RX1>,
462 + <PIN_PA28__G0_RX2>,
463 + <PIN_PA29__G0_RX3>,
464 + <PIN_PA15__G0_TXEN>,
465 + <PIN_PA30__G0_RXCK>,
466 + <PIN_PA18__G0_RXDV>,
467 + <PIN_PA22__G0_MDC>,
468 + <PIN_PA23__G0_MDIO>,
469 + <PIN_PA25__G0_125CK>;
470 + bias-disable;
471 + };
472 +
473 + pinctrl_gmac0_txck_default: gmac0_txck_default {
474 + pinmux = <PIN_PA24__G0_TXCK>;
475 + bias-pull-up;
476 + };
477 +
478 + pinctrl_gmac0_phy_irq: gmac0_phy_irq {
479 + pinmux = <PIN_PA31__GPIO>;
480 + bias-disable;
481 + };
482 +
483 + pinctrl_gmac1_default: gmac1_default {
484 + pinmux = <PIN_PD30__G1_TXCK>,
485 + <PIN_PD22__G1_TX0>,
486 + <PIN_PD23__G1_TX1>,
487 + <PIN_PD21__G1_TXEN>,
488 + <PIN_PD25__G1_RX0>,
489 + <PIN_PD26__G1_RX1>,
490 + <PIN_PD27__G1_RXER>,
491 + <PIN_PD24__G1_RXDV>,
492 + <PIN_PD28__G1_MDC>,
493 + <PIN_PD29__G1_MDIO>;
494 + bias-disable;
495 + };
496 +
497 + pinctrl_gmac1_phy_irq: gmac1_phy_irq {
498 + pinmux = <PIN_PA21__GPIO>;
499 + bias-disable;
500 + };
501 +
502 + pinctrl_i2c1_default: i2c1_default {
503 + pinmux = <PIN_PC9__FLEXCOM1_IO0>,
504 + <PIN_PC10__FLEXCOM1_IO1>;
505 + bias-disable;
506 + };
507 +
508 + pinctrl_i2c8_default: i2c8_default {
509 + pinmux = <PIN_PC14__FLEXCOM8_IO0>,
510 + <PIN_PC13__FLEXCOM8_IO1>;
511 + bias-disable;
512 + };
513 +
514 + pinctrl_i2c9_default: i2c9_default {
515 + pinmux = <PIN_PC18__FLEXCOM9_IO0>,
516 + <PIN_PC19__FLEXCOM9_IO1>;
517 + bias-disable;
518 + };
519 +
520 + pinctrl_i2s0_default: i2s0_default {
521 + pinmux = <PIN_PB23__I2SMCC0_CK>,
522 + <PIN_PB24__I2SMCC0_WS>,
523 + <PIN_PB25__I2SMCC0_DOUT1>,
524 + <PIN_PB26__I2SMCC0_DOUT0>,
525 + <PIN_PB27__I2SMCC0_MCK>;
526 + bias-disable;
527 + };
528 +
529 + pinctrl_key_gpio_default: key_gpio_default {
530 + pinmux = <PIN_PA12__GPIO>;
531 + bias-pull-up;
532 + };
533 +
534 + pinctrl_led_gpio_default: led_gpio_default {
535 + pinmux = <PIN_PA13__GPIO>,
536 + <PIN_PB8__GPIO>,
537 + <PIN_PD20__GPIO>;
538 + bias-pull-up;
539 + };
540 +
541 + pinctrl_mikrobus1_an_default: mikrobus1_an_default {
542 + pinmux = <PIN_PD0__GPIO>;
543 + bias-disable;
544 + };
545 +
546 + pinctrl_mikrobus2_an_default: mikrobus2_an_default {
547 + pinmux = <PIN_PD1__GPIO>;
548 + bias-disable;
549 + };
550 +
551 + pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default {
552 + pinmux = <PIN_PA13__PWMH2>;
553 + bias-disable;
554 + };
555 +
556 + pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default {
557 + pinmux = <PIN_PD20__PWMH3>;
558 + bias-disable;
559 + };
560 +
561 + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs {
562 + pinmux = <PIN_PB6__FLEXCOM11_IO3>;
563 + bias-disable;
564 + };
565 +
566 + pinctrl_mikrobus1_spi: mikrobus1_spi {
567 + pinmux = <PIN_PB3__FLEXCOM11_IO0>,
568 + <PIN_PB4__FLEXCOM11_IO1>,
569 + <PIN_PB5__FLEXCOM11_IO2>;
570 + bias-disable;
571 + };
572 +
573 + pinctrl_sdmmc0_default: sdmmc0_default {
574 + cmd_data {
575 + pinmux = <PIN_PA1__SDMMC0_CMD>,
576 + <PIN_PA3__SDMMC0_DAT0>,
577 + <PIN_PA4__SDMMC0_DAT1>,
578 + <PIN_PA5__SDMMC0_DAT2>,
579 + <PIN_PA6__SDMMC0_DAT3>,
580 + <PIN_PA7__SDMMC0_DAT4>,
581 + <PIN_PA8__SDMMC0_DAT5>,
582 + <PIN_PA9__SDMMC0_DAT6>,
583 + <PIN_PA10__SDMMC0_DAT7>;
584 + bias-pull-up;
585 + };
586 +
587 + ck_cd_rstn_vddsel {
588 + pinmux = <PIN_PA0__SDMMC0_CK>,
589 + <PIN_PA2__SDMMC0_RSTN>,
590 + <PIN_PA11__SDMMC0_DS>;
591 + bias-pull-up;
592 + };
593 + };
594 +
595 + pinctrl_sdmmc1_default: sdmmc1_default {
596 + cmd_data {
597 + pinmux = <PIN_PB29__SDMMC1_CMD>,
598 + <PIN_PB31__SDMMC1_DAT0>,
599 + <PIN_PC0__SDMMC1_DAT1>,
600 + <PIN_PC1__SDMMC1_DAT2>,
601 + <PIN_PC2__SDMMC1_DAT3>;
602 + bias-pull-up;
603 + };
604 +
605 + ck_cd_rstn_vddsel {
606 + pinmux = <PIN_PB30__SDMMC1_CK>,
607 + <PIN_PB28__SDMMC1_RSTN>,
608 + <PIN_PC5__SDMMC1_1V8SEL>,
609 + <PIN_PC4__SDMMC1_CD>;
610 + bias-pull-up;
611 + };
612 + };
613 +
614 + pinctrl_sdmmc2_default: sdmmc2_default {
615 + cmd_data {
616 + pinmux = <PIN_PD3__SDMMC2_CMD>,
617 + <PIN_PD5__SDMMC2_DAT0>,
618 + <PIN_PD6__SDMMC2_DAT1>,
619 + <PIN_PD7__SDMMC2_DAT2>,
620 + <PIN_PD8__SDMMC2_DAT3>;
621 + bias-pull-up;
622 + };
623 +
624 + ck {
625 + pinmux = <PIN_PD4__SDMMC2_CK>;
626 + bias-pull-up;
627 + };
628 + };
629 +
630 + pinctrl_spdifrx_default: spdifrx_default {
631 + pinmux = <PIN_PB0__SPDIF_RX>;
632 + bias-disable;
633 + };
634 +
635 + pinctrl_spdiftx_default: spdiftx_default {
636 + pinmux = <PIN_PB1__SPDIF_TX>;
637 + bias-disable;
638 + };
639 +};
640 +
641 +&pwm {
642 + pinctrl-names = "default";
643 + pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>;
644 + status = "disabled"; /* Conflict with leds. */
645 +};
646 +
647 +&rtt {
648 + atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
649 +};
650 +
651 +&sdmmc0 {
652 + bus-width = <8>;
653 + non-removable;
654 + no-1-8-v;
655 + sdhci-caps-mask = <0x0 0x00200000>;
656 + pinctrl-names = "default";
657 + pinctrl-0 = <&pinctrl_sdmmc0_default>;
658 + status = "okay";
659 +};
660 +
661 +&sdmmc1 {
662 + bus-width = <4>;
663 + no-1-8-v;
664 + sdhci-caps-mask = <0x0 0x00200000>;
665 + pinctrl-names = "default";
666 + pinctrl-0 = <&pinctrl_sdmmc1_default>;
667 + status = "okay";
668 +};
669 +
670 +&sdmmc2 {
671 + bus-width = <4>;
672 + no-1-8-v;
673 + sdhci-caps-mask = <0x0 0x00200000>;
674 + pinctrl-names = "default";
675 + pinctrl-0 = <&pinctrl_sdmmc2_default>;
676 +};
677 +
678 +&spdifrx {
679 + pinctrl-names = "default";
680 + pinctrl-0 = <&pinctrl_spdifrx_default>;
681 + status = "okay";
682 +};
683 +
684 +&spdiftx {
685 + pinctrl-names = "default";
686 + pinctrl-0 = <&pinctrl_spdiftx_default>;
687 + status = "okay";
688 +};
689 +
690 +&trng {
691 + status = "okay";
692 +};
693 +
694 +&vddout25 {
695 + vin-supply = <&vdd_3v3>;
696 + status = "okay";
697 +};
698 --- /dev/null
699 +++ b/arch/arm/boot/dts/sama7g5-pinfunc.h
700 @@ -0,0 +1,923 @@
701 +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
702 +#define PINMUX_PIN(no, func, ioset) \
703 +(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))
704 +
705 +#define PIN_PA0 0
706 +#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0)
707 +#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1)
708 +#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1)
709 +#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1)
710 +#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2)
711 +#define PIN_PA1 1
712 +#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0)
713 +#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1)
714 +#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1)
715 +#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1)
716 +#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1)
717 +#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3)
718 +#define PIN_PA2 2
719 +#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0)
720 +#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1)
721 +#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1)
722 +#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1)
723 +#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1)
724 +#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3)
725 +#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3)
726 +#define PIN_PA3 3
727 +#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0)
728 +#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1)
729 +#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1)
730 +#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1)
731 +#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1)
732 +#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3)
733 +#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3)
734 +#define PIN_PA4 4
735 +#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0)
736 +#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1)
737 +#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1)
738 +#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1)
739 +#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1)
740 +#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3)
741 +#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3)
742 +#define PIN_PA5 5
743 +#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0)
744 +#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1)
745 +#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1)
746 +#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1)
747 +#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1)
748 +#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3)
749 +#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3)
750 +#define PIN_PA6 6
751 +#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0)
752 +#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1)
753 +#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1)
754 +#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1)
755 +#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1)
756 +#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3)
757 +#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3)
758 +#define PIN_PA7 7
759 +#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0)
760 +#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1)
761 +#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1)
762 +#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1)
763 +#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1)
764 +#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3)
765 +#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3)
766 +#define PIN_PA8 8
767 +#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0)
768 +#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1)
769 +#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1)
770 +#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1)
771 +#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1)
772 +#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3)
773 +#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3)
774 +#define PIN_PA9 9
775 +#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0)
776 +#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1)
777 +#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1)
778 +#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1)
779 +#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1)
780 +#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1)
781 +#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3)
782 +#define PIN_PA10 10
783 +#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0)
784 +#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1)
785 +#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1)
786 +#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1)
787 +#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1)
788 +#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1)
789 +#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3)
790 +#define PIN_PA11 11
791 +#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0)
792 +#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1)
793 +#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1)
794 +#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1)
795 +#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1)
796 +#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3)
797 +#define PIN_PA12 12
798 +#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0)
799 +#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1)
800 +#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1)
801 +#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1)
802 +#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3)
803 +#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3)
804 +#define PIN_PA13 13
805 +#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0)
806 +#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1)
807 +#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1)
808 +#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1)
809 +#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3)
810 +#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3)
811 +#define PIN_PA14 14
812 +#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0)
813 +#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1)
814 +#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1)
815 +#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1)
816 +#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3)
817 +#define PIN_PA15 15
818 +#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0)
819 +#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1)
820 +#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1)
821 +#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1)
822 +#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1)
823 +#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1)
824 +#define PIN_PA16 16
825 +#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0)
826 +#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1)
827 +#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1)
828 +#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1)
829 +#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1)
830 +#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1)
831 +#define PIN_PA17 17
832 +#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0)
833 +#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1)
834 +#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1)
835 +#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1)
836 +#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1)
837 +#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1)
838 +#define PIN_PA18 18
839 +#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0)
840 +#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1)
841 +#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1)
842 +#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1)
843 +#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1)
844 +#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1)
845 +#define PIN_PA19 19
846 +#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0)
847 +#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1)
848 +#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1)
849 +#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1)
850 +#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1)
851 +#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1)
852 +#define PIN_PA20 20
853 +#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0)
854 +#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1)
855 +#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1)
856 +#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1)
857 +#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1)
858 +#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1)
859 +#define PIN_PA21 21
860 +#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0)
861 +#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1)
862 +#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1)
863 +#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1)
864 +#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1)
865 +#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1)
866 +#define PIN_PA22 22
867 +#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0)
868 +#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1)
869 +#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1)
870 +#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1)
871 +#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1)
872 +#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1)
873 +#define PIN_PA23 23
874 +#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0)
875 +#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1)
876 +#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1)
877 +#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1)
878 +#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1)
879 +#define PIN_PA24 24
880 +#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0)
881 +#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1)
882 +#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1)
883 +#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1)
884 +#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1)
885 +#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1)
886 +#define PIN_PA25 25
887 +#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0)
888 +#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1)
889 +#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1)
890 +#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1)
891 +#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1)
892 +#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1)
893 +#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3)
894 +#define PIN_PA26 26
895 +#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0)
896 +#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1)
897 +#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1)
898 +#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1)
899 +#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1)
900 +#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1)
901 +#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3)
902 +#define PIN_PA27 27
903 +#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0)
904 +#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1)
905 +#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1)
906 +#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1)
907 +#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1)
908 +#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1)
909 +#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3)
910 +#define PIN_PA28 28
911 +#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0)
912 +#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1)
913 +#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1)
914 +#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1)
915 +#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1)
916 +#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1)
917 +#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3)
918 +#define PIN_PA29 29
919 +#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0)
920 +#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1)
921 +#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1)
922 +#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1)
923 +#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1)
924 +#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1)
925 +#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3)
926 +#define PIN_PA30 30
927 +#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0)
928 +#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1)
929 +#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1)
930 +#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1)
931 +#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1)
932 +#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1)
933 +#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3)
934 +#define PIN_PA31 31
935 +#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0)
936 +#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1)
937 +#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1)
938 +#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1)
939 +#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1)
940 +#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1)
941 +#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3)
942 +#define PIN_PB0 32
943 +#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0)
944 +#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1)
945 +#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2)
946 +#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1)
947 +#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1)
948 +#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2)
949 +#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3)
950 +#define PIN_PB1 33
951 +#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0)
952 +#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1)
953 +#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2)
954 +#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1)
955 +#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1)
956 +#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2)
957 +#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3)
958 +#define PIN_PB2 34
959 +#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0)
960 +#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1)
961 +#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1)
962 +#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1)
963 +#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1)
964 +#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3)
965 +#define PIN_PB3 35
966 +#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0)
967 +#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1)
968 +#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1)
969 +#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2)
970 +#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1)
971 +#define PIN_PB4 36
972 +#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0)
973 +#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1)
974 +#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1)
975 +#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2)
976 +#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1)
977 +#define PIN_PB5 37
978 +#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0)
979 +#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1)
980 +#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1)
981 +#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2)
982 +#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1)
983 +#define PIN_PB6 38
984 +#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0)
985 +#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1)
986 +#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1)
987 +#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2)
988 +#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1)
989 +#define PIN_PB7 39
990 +#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0)
991 +#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1)
992 +#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1)
993 +#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2)
994 +#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1)
995 +#define PIN_PB8 40
996 +#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0)
997 +#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1)
998 +#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1)
999 +#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2)
1000 +#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1)
1001 +#define PIN_PB9 41
1002 +#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0)
1003 +#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1)
1004 +#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1)
1005 +#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1)
1006 +#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1)
1007 +#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2)
1008 +#define PIN_PB10 42
1009 +#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0)
1010 +#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1)
1011 +#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1)
1012 +#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1)
1013 +#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1)
1014 +#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2)
1015 +#define PIN_PB11 43
1016 +#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0)
1017 +#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1)
1018 +#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1)
1019 +#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1)
1020 +#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1)
1021 +#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2)
1022 +#define PIN_PB12 44
1023 +#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0)
1024 +#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1)
1025 +#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1)
1026 +#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1)
1027 +#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1)
1028 +#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2)
1029 +#define PIN_PB13 45
1030 +#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0)
1031 +#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1)
1032 +#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1)
1033 +#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1)
1034 +#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1)
1035 +#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2)
1036 +#define PIN_PB14 46
1037 +#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0)
1038 +#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1)
1039 +#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1)
1040 +#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1)
1041 +#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2)
1042 +#define PIN_PB15 47
1043 +#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0)
1044 +#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1)
1045 +#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1)
1046 +#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1)
1047 +#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2)
1048 +#define PIN_PB16 48
1049 +#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0)
1050 +#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1)
1051 +#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1)
1052 +#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1)
1053 +#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1)
1054 +#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2)
1055 +#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2)
1056 +#define PIN_PB17 49
1057 +#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0)
1058 +#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1)
1059 +#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1)
1060 +#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1)
1061 +#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1)
1062 +#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2)
1063 +#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2)
1064 +#define PIN_PB18 50
1065 +#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0)
1066 +#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1)
1067 +#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1)
1068 +#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1)
1069 +#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1)
1070 +#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2)
1071 +#define PIN_PB19 51
1072 +#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0)
1073 +#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1)
1074 +#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1)
1075 +#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1)
1076 +#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1)
1077 +#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2)
1078 +#define PIN_PB20 52
1079 +#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0)
1080 +#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1)
1081 +#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1)
1082 +#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1)
1083 +#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2)
1084 +#define PIN_PB21 53
1085 +#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0)
1086 +#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1)
1087 +#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1)
1088 +#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1)
1089 +#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1)
1090 +#define PIN_PB22 54
1091 +#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0)
1092 +#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1)
1093 +#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1)
1094 +#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1)
1095 +#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1)
1096 +#define PIN_PB23 55
1097 +#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0)
1098 +#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1)
1099 +#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1)
1100 +#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1)
1101 +#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1)
1102 +#define PIN_PB24 56
1103 +#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0)
1104 +#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1)
1105 +#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1)
1106 +#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1)
1107 +#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1)
1108 +#define PIN_PB25 57
1109 +#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0)
1110 +#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1)
1111 +#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1)
1112 +#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1)
1113 +#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1)
1114 +#define PIN_PB26 58
1115 +#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0)
1116 +#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1)
1117 +#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1)
1118 +#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1)
1119 +#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1)
1120 +#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1)
1121 +#define PIN_PB27 59
1122 +#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0)
1123 +#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1)
1124 +#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1)
1125 +#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1)
1126 +#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1)
1127 +#define PIN_PB28 60
1128 +#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0)
1129 +#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1)
1130 +#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2)
1131 +#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1)
1132 +#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4)
1133 +#define PIN_PB29 61
1134 +#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0)
1135 +#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1)
1136 +#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2)
1137 +#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2)
1138 +#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2)
1139 +#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1)
1140 +#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4)
1141 +#define PIN_PB30 62
1142 +#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0)
1143 +#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1)
1144 +#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2)
1145 +#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2)
1146 +#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1)
1147 +#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1)
1148 +#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4)
1149 +#define PIN_PB31 63
1150 +#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0)
1151 +#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1)
1152 +#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2)
1153 +#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2)
1154 +#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1)
1155 +#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1)
1156 +#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4)
1157 +#define PIN_PC0 64
1158 +#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0)
1159 +#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1)
1160 +#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2)
1161 +#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1)
1162 +#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1)
1163 +#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4)
1164 +#define PIN_PC1 65
1165 +#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0)
1166 +#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1)
1167 +#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2)
1168 +#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1)
1169 +#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1)
1170 +#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4)
1171 +#define PIN_PC2 66
1172 +#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0)
1173 +#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1)
1174 +#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2)
1175 +#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1)
1176 +#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1)
1177 +#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4)
1178 +#define PIN_PC3 67
1179 +#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0)
1180 +#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1)
1181 +#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2)
1182 +#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1)
1183 +#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1)
1184 +#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4)
1185 +#define PIN_PC4 68
1186 +#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0)
1187 +#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1)
1188 +#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2)
1189 +#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2)
1190 +#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1)
1191 +#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1)
1192 +#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4)
1193 +#define PIN_PC5 69
1194 +#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0)
1195 +#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1)
1196 +#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2)
1197 +#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2)
1198 +#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1)
1199 +#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1)
1200 +#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4)
1201 +#define PIN_PC6 70
1202 +#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0)
1203 +#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2)
1204 +#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2)
1205 +#define PIN_PC7 71
1206 +#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0)
1207 +#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1)
1208 +#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2)
1209 +#define PIN_PC8 72
1210 +#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0)
1211 +#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1)
1212 +#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2)
1213 +#define PIN_PC9 73
1214 +#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0)
1215 +#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1)
1216 +#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2)
1217 +#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4)
1218 +#define PIN_PC10 74
1219 +#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0)
1220 +#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1)
1221 +#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2)
1222 +#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4)
1223 +#define PIN_PC11 75
1224 +#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0)
1225 +#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1)
1226 +#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2)
1227 +#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4)
1228 +#define PIN_PC12 76
1229 +#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0)
1230 +#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1)
1231 +#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2)
1232 +#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4)
1233 +#define PIN_PC13 77
1234 +#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0)
1235 +#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1)
1236 +#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2)
1237 +#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4)
1238 +#define PIN_PC14 78
1239 +#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0)
1240 +#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1)
1241 +#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2)
1242 +#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4)
1243 +#define PIN_PC15 79
1244 +#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0)
1245 +#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1)
1246 +#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2)
1247 +#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4)
1248 +#define PIN_PC16 80
1249 +#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0)
1250 +#define PIN_PC16__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1)
1251 +#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2)
1252 +#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4)
1253 +#define PIN_PC17 81
1254 +#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0)
1255 +#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1)
1256 +#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3)
1257 +#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4)
1258 +#define PIN_PC18 82
1259 +#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0)
1260 +#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1)
1261 +#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2)
1262 +#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4)
1263 +#define PIN_PC19 83
1264 +#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0)
1265 +#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1)
1266 +#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2)
1267 +#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4)
1268 +#define PIN_PC20 84
1269 +#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0)
1270 +#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1)
1271 +#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2)
1272 +#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4)
1273 +#define PIN_PC21 85
1274 +#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0)
1275 +#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1)
1276 +#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2)
1277 +#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2)
1278 +#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5)
1279 +#define PIN_PC22 86
1280 +#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0)
1281 +#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1)
1282 +#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2)
1283 +#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2)
1284 +#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5)
1285 +#define PIN_PC23 87
1286 +#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0)
1287 +#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1)
1288 +#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3)
1289 +#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2)
1290 +#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5)
1291 +#define PIN_PC24 88
1292 +#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0)
1293 +#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3)
1294 +#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3)
1295 +#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2)
1296 +#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5)
1297 +#define PIN_PC25 89
1298 +#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0)
1299 +#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1)
1300 +#define PIN_PC26 90
1301 +#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0)
1302 +#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1)
1303 +#define PIN_PC27 91
1304 +#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0)
1305 +#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1)
1306 +#define PIN_PC28 92
1307 +#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0)
1308 +#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1)
1309 +#define PIN_PC29 93
1310 +#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0)
1311 +#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1)
1312 +#define PIN_PC30 94
1313 +#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0)
1314 +#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2)
1315 +#define PIN_PC31 95
1316 +#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0)
1317 +#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2)
1318 +#define PIN_PD0 96
1319 +#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0)
1320 +#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2)
1321 +#define PIN_PD1 97
1322 +#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0)
1323 +#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2)
1324 +#define PIN_PD2 98
1325 +#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0)
1326 +#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1)
1327 +#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2)
1328 +#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1)
1329 +#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2)
1330 +#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2)
1331 +#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5)
1332 +#define PIN_PD3 99
1333 +#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0)
1334 +#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1)
1335 +#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2)
1336 +#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1)
1337 +#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2)
1338 +#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2)
1339 +#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5)
1340 +#define PIN_PD4 100
1341 +#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0)
1342 +#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1)
1343 +#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2)
1344 +#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1)
1345 +#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2)
1346 +#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2)
1347 +#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5)
1348 +#define PIN_PD5 101
1349 +#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0)
1350 +#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1)
1351 +#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2)
1352 +#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1)
1353 +#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2)
1354 +#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2)
1355 +#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5)
1356 +#define PIN_PD6 102
1357 +#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0)
1358 +#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1)
1359 +#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2)
1360 +#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3)
1361 +#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2)
1362 +#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2)
1363 +#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5)
1364 +#define PIN_PD7 103
1365 +#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0)
1366 +#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1)
1367 +#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2)
1368 +#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2)
1369 +#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2)
1370 +#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2)
1371 +#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5)
1372 +#define PIN_PD8 104
1373 +#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0)
1374 +#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1)
1375 +#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1)
1376 +#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2)
1377 +#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2)
1378 +#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5)
1379 +#define PIN_PD9 105
1380 +#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0)
1381 +#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1)
1382 +#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2)
1383 +#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2)
1384 +#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2)
1385 +#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5)
1386 +#define PIN_PD10 106
1387 +#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0)
1388 +#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1)
1389 +#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2)
1390 +#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2)
1391 +#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2)
1392 +#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2)
1393 +#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3)
1394 +#define PIN_PD11 107
1395 +#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0)
1396 +#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1)
1397 +#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2)
1398 +#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2)
1399 +#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2)
1400 +#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2)
1401 +#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3)
1402 +#define PIN_PD12 108
1403 +#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0)
1404 +#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2)
1405 +#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2)
1406 +#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2)
1407 +#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2)
1408 +#define PIN_PD13 109
1409 +#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0)
1410 +#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2)
1411 +#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2)
1412 +#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4)
1413 +#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2)
1414 +#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2)
1415 +#define PIN_PD14 110
1416 +#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0)
1417 +#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2)
1418 +#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2)
1419 +#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4)
1420 +#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2)
1421 +#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2)
1422 +#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5)
1423 +#define PIN_PD15 111
1424 +#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0)
1425 +#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2)
1426 +#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2)
1427 +#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4)
1428 +#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2)
1429 +#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2)
1430 +#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5)
1431 +#define PIN_PD16 112
1432 +#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0)
1433 +#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2)
1434 +#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2)
1435 +#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4)
1436 +#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2)
1437 +#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2)
1438 +#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5)
1439 +#define PIN_PD17 113
1440 +#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0)
1441 +#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2)
1442 +#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2)
1443 +#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4)
1444 +#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2)
1445 +#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2)
1446 +#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5)
1447 +#define PIN_PD18 114
1448 +#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0)
1449 +#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2)
1450 +#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2)
1451 +#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4)
1452 +#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2)
1453 +#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2)
1454 +#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5)
1455 +#define PIN_PD19 115
1456 +#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0)
1457 +#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2)
1458 +#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2)
1459 +#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4)
1460 +#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2)
1461 +#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2)
1462 +#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5)
1463 +#define PIN_PD20 116
1464 +#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0)
1465 +#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3)
1466 +#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2)
1467 +#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4)
1468 +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2)
1469 +#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5)
1470 +#define PIN_PD21 117
1471 +#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0)
1472 +#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3)
1473 +#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2)
1474 +#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2)
1475 +#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5)
1476 +#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1)
1477 +#define PIN_PD22 118
1478 +#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0)
1479 +#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2)
1480 +#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4)
1481 +#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2)
1482 +#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2)
1483 +#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1)
1484 +#define PIN_PD23 119
1485 +#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0)
1486 +#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2)
1487 +#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4)
1488 +#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2)
1489 +#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2)
1490 +#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2)
1491 +#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1)
1492 +#define PIN_PD24 120
1493 +#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0)
1494 +#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2)
1495 +#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4)
1496 +#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2)
1497 +#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2)
1498 +#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1)
1499 +#define PIN_PD25 121
1500 +#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0)
1501 +#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2)
1502 +#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2)
1503 +#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4)
1504 +#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2)
1505 +#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2)
1506 +#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1)
1507 +#define PIN_PD26 122
1508 +#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0)
1509 +#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2)
1510 +#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2)
1511 +#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3)
1512 +#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2)
1513 +#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2)
1514 +#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1)
1515 +#define PIN_PD27 123
1516 +#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0)
1517 +#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2)
1518 +#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2)
1519 +#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3)
1520 +#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2)
1521 +#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2)
1522 +#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1)
1523 +#define PIN_PD28 124
1524 +#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0)
1525 +#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2)
1526 +#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2)
1527 +#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3)
1528 +#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2)
1529 +#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2)
1530 +#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5)
1531 +#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1)
1532 +#define PIN_PD29 125
1533 +#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0)
1534 +#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2)
1535 +#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2)
1536 +#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3)
1537 +#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2)
1538 +#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2)
1539 +#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5)
1540 +#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1)
1541 +#define PIN_PD30 126
1542 +#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0)
1543 +#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2)
1544 +#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2)
1545 +#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3)
1546 +#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2)
1547 +#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2)
1548 +#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5)
1549 +#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1)
1550 +#define PIN_PD31 127
1551 +#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0)
1552 +#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2)
1553 +#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2)
1554 +#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3)
1555 +#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2)
1556 +#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2)
1557 +#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5)
1558 +#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1)
1559 +#define PIN_PE0 128
1560 +#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0)
1561 +#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2)
1562 +#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2)
1563 +#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3)
1564 +#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2)
1565 +#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2)
1566 +#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5)
1567 +#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1)
1568 +#define PIN_PE1 129
1569 +#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0)
1570 +#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2)
1571 +#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2)
1572 +#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3)
1573 +#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2)
1574 +#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2)
1575 +#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5)
1576 +#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1)
1577 +#define PIN_PE2 130
1578 +#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0)
1579 +#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5)
1580 +#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2)
1581 +#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3)
1582 +#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2)
1583 +#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2)
1584 +#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1)
1585 +#define PIN_PE3 131
1586 +#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0)
1587 +#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5)
1588 +#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4)
1589 +#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3)
1590 +#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2)
1591 +#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2)
1592 +#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1)
1593 +#define PIN_PE4 132
1594 +#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0)
1595 +#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5)
1596 +#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4)
1597 +#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3)
1598 +#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2)
1599 +#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2)
1600 +#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1)
1601 +#define PIN_PE5 133
1602 +#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0)
1603 +#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5)
1604 +#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4)
1605 +#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3)
1606 +#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2)
1607 +#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2)
1608 +#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1)
1609 +#define PIN_PE6 134
1610 +#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0)
1611 +#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5)
1612 +#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4)
1613 +#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3)
1614 +#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2)
1615 +#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2)
1616 +#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1)
1617 +#define PIN_PE7 135
1618 +#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0)
1619 +#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5)
1620 +#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4)
1621 +#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3)
1622 +#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2)
1623 +#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1)
1624 --- /dev/null
1625 +++ b/arch/arm/boot/dts/sama7g5.dtsi
1626 @@ -0,0 +1,528 @@
1627 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1628 +/*
1629 + * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
1630 + *
1631 + * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
1632 + *
1633 + * Author: Eugen Hristev <eugen.hristev@microchip.com>
1634 + * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
1635 + *
1636 + */
1637 +
1638 +#include <dt-bindings/interrupt-controller/irq.h>
1639 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1640 +#include <dt-bindings/clock/at91.h>
1641 +#include <dt-bindings/dma/at91.h>
1642 +#include <dt-bindings/gpio/gpio.h>
1643 +
1644 +/ {
1645 + model = "Microchip SAMA7G5 family SoC";
1646 + compatible = "microchip,sama7g5";
1647 + #address-cells = <1>;
1648 + #size-cells = <1>;
1649 + interrupt-parent = <&gic>;
1650 +
1651 + cpus {
1652 + #address-cells = <1>;
1653 + #size-cells = <0>;
1654 +
1655 + cpu0: cpu@0 {
1656 + device_type = "cpu";
1657 + compatible = "arm,cortex-a7";
1658 + reg = <0x0>;
1659 + };
1660 + };
1661 +
1662 + clocks {
1663 + slow_xtal: slow_xtal {
1664 + compatible = "fixed-clock";
1665 + #clock-cells = <0>;
1666 + };
1667 +
1668 + main_xtal: main_xtal {
1669 + compatible = "fixed-clock";
1670 + #clock-cells = <0>;
1671 + };
1672 +
1673 + usb_clk: usb_clk {
1674 + compatible = "fixed-clock";
1675 + #clock-cells = <0>;
1676 + clock-frequency = <48000000>;
1677 + };
1678 + };
1679 +
1680 + vddout25: fixed-regulator-vddout25 {
1681 + compatible = "regulator-fixed";
1682 +
1683 + regulator-name = "VDDOUT25";
1684 + regulator-min-microvolt = <2500000>;
1685 + regulator-max-microvolt = <2500000>;
1686 + regulator-boot-on;
1687 + status = "disabled";
1688 + };
1689 +
1690 + ns_sram: sram@100000 {
1691 + compatible = "mmio-sram";
1692 + #address-cells = <1>;
1693 + #size-cells = <1>;
1694 + reg = <0x100000 0x20000>;
1695 + ranges;
1696 + };
1697 +
1698 + soc {
1699 + compatible = "simple-bus";
1700 + #address-cells = <1>;
1701 + #size-cells = <1>;
1702 + ranges;
1703 +
1704 + secumod: secumod@e0004000 {
1705 + compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
1706 + reg = <0xe0004000 0x4000>;
1707 + gpio-controller;
1708 + #gpio-cells = <2>;
1709 + };
1710 +
1711 + sfrbu: sfr@e0008000 {
1712 + compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
1713 + reg = <0xe0008000 0x20>;
1714 + };
1715 +
1716 + pioA: pinctrl@e0014000 {
1717 + compatible = "microchip,sama7g5-pinctrl";
1718 + reg = <0xe0014000 0x800>;
1719 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1720 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1721 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1722 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1723 + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1724 + interrupt-controller;
1725 + #interrupt-cells = <2>;
1726 + gpio-controller;
1727 + #gpio-cells = <2>;
1728 + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
1729 + };
1730 +
1731 + pmc: pmc@e0018000 {
1732 + compatible = "microchip,sama7g5-pmc", "syscon";
1733 + reg = <0xe0018000 0x200>;
1734 + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1735 + #clock-cells = <2>;
1736 + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1737 + clock-names = "td_slck", "md_slck", "main_xtal";
1738 + };
1739 +
1740 + rtt: rtt@e001d020 {
1741 + compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
1742 + reg = <0xe001d020 0x30>;
1743 + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1744 + clocks = <&clk32k 0>;
1745 + };
1746 +
1747 + clk32k: clock-controller@e001d050 {
1748 + compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
1749 + reg = <0xe001d050 0x4>;
1750 + clocks = <&slow_xtal>;
1751 + #clock-cells = <1>;
1752 + };
1753 +
1754 + gpbr: gpbr@e001d060 {
1755 + compatible = "microchip,sama7g5-gpbr", "syscon";
1756 + reg = <0xe001d060 0x48>;
1757 + };
1758 +
1759 + ps_wdt: watchdog@e001d180 {
1760 + compatible = "microchip,sama7g5-wdt";
1761 + reg = <0xe001d180 0x24>;
1762 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1763 + clocks = <&clk32k 0>;
1764 + };
1765 +
1766 + sdmmc0: mmc@e1204000 {
1767 + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
1768 + reg = <0xe1204000 0x4000>;
1769 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1770 + clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
1771 + clock-names = "hclock", "multclk";
1772 + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
1773 + assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
1774 + assigned-clock-rates = <200000000>;
1775 + microchip,sdcal-inverted;
1776 + status = "disabled";
1777 + };
1778 +
1779 + sdmmc1: mmc@e1208000 {
1780 + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
1781 + reg = <0xe1208000 0x4000>;
1782 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1783 + clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
1784 + clock-names = "hclock", "multclk";
1785 + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
1786 + assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
1787 + assigned-clock-rates = <200000000>;
1788 + microchip,sdcal-inverted;
1789 + status = "disabled";
1790 + };
1791 +
1792 + sdmmc2: mmc@e120c000 {
1793 + compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
1794 + reg = <0xe120c000 0x4000>;
1795 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1796 + clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
1797 + clock-names = "hclock", "multclk";
1798 + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
1799 + assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
1800 + assigned-clock-rates = <200000000>;
1801 + microchip,sdcal-inverted;
1802 + status = "disabled";
1803 + };
1804 +
1805 + pwm: pwm@e1604000 {
1806 + compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
1807 + reg = <0xe1604000 0x4000>;
1808 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1809 + #pwm-cells = <3>;
1810 + clocks = <&pmc PMC_TYPE_PERIPHERAL 77>;
1811 + status = "disabled";
1812 + };
1813 +
1814 + spdifrx: spdifrx@e1614000 {
1815 + #sound-dai-cells = <0>;
1816 + compatible = "microchip,sama7g5-spdifrx";
1817 + reg = <0xe1614000 0x4000>;
1818 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1819 + dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;
1820 + dma-names = "rx";
1821 + clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
1822 + clock-names = "pclk", "gclk";
1823 + status = "disabled";
1824 + };
1825 +
1826 + spdiftx: spdiftx@e1618000 {
1827 + #sound-dai-cells = <0>;
1828 + compatible = "microchip,sama7g5-spdiftx";
1829 + reg = <0xe1618000 0x4000>;
1830 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1831 + dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;
1832 + dma-names = "tx";
1833 + clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
1834 + clock-names = "pclk", "gclk";
1835 + };
1836 +
1837 + i2s0: i2s@e161c000 {
1838 + compatible = "microchip,sama7g5-i2smcc";
1839 + #sound-dai-cells = <0>;
1840 + reg = <0xe161c000 0x4000>;
1841 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1842 + dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;
1843 + dma-names = "tx", "rx";
1844 + clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
1845 + clock-names = "pclk", "gclk";
1846 + status = "disabled";
1847 + };
1848 +
1849 + i2s1: i2s@e1620000 {
1850 + compatible = "microchip,sama7g5-i2smcc";
1851 + #sound-dai-cells = <0>;
1852 + reg = <0xe1620000 0x4000>;
1853 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1854 + dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;
1855 + dma-names = "tx", "rx";
1856 + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
1857 + clock-names = "pclk", "gclk";
1858 + status = "disabled";
1859 + };
1860 +
1861 + pit64b0: timer@e1800000 {
1862 + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
1863 + reg = <0xe1800000 0x4000>;
1864 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1865 + clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
1866 + clock-names = "pclk", "gclk";
1867 + };
1868 +
1869 + pit64b1: timer@e1804000 {
1870 + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
1871 + reg = <0xe1804000 0x4000>;
1872 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1873 + clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;
1874 + clock-names = "pclk", "gclk";
1875 + };
1876 +
1877 + flx0: flexcom@e1818000 {
1878 + compatible = "atmel,sama5d2-flexcom";
1879 + reg = <0xe1818000 0x200>;
1880 + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
1881 + #address-cells = <1>;
1882 + #size-cells = <1>;
1883 + ranges = <0x0 0xe1818000 0x800>;
1884 + status = "disabled";
1885 +
1886 + uart0: serial@200 {
1887 + compatible = "atmel,at91sam9260-usart";
1888 + reg = <0x200 0x200>;
1889 + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1890 + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
1891 + clock-names = "usart";
1892 + dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
1893 + <&dma1 AT91_XDMAC_DT_PERID(5)>;
1894 + dma-names = "tx", "rx";
1895 + atmel,use-dma-rx;
1896 + atmel,use-dma-tx;
1897 + status = "disabled";
1898 + };
1899 + };
1900 +
1901 + flx1: flexcom@e181c000 {
1902 + compatible = "atmel,sama5d2-flexcom";
1903 + reg = <0xe181c000 0x200>;
1904 + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
1905 + #address-cells = <1>;
1906 + #size-cells = <1>;
1907 + ranges = <0x0 0xe181c000 0x800>;
1908 + status = "disabled";
1909 +
1910 + i2c1: i2c@600 {
1911 + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
1912 + reg = <0x600 0x200>;
1913 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1914 + #address-cells = <1>;
1915 + #size-cells = <0>;
1916 + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
1917 + atmel,fifo-size = <32>;
1918 + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
1919 + <&dma0 AT91_XDMAC_DT_PERID(8)>;
1920 + dma-names = "rx", "tx";
1921 + atmel,use-dma-rx;
1922 + atmel,use-dma-tx;
1923 + status = "disabled";
1924 + };
1925 + };
1926 +
1927 + flx3: flexcom@e1824000 {
1928 + compatible = "atmel,sama5d2-flexcom";
1929 + reg = <0xe1824000 0x200>;
1930 + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
1931 + #address-cells = <1>;
1932 + #size-cells = <1>;
1933 + ranges = <0x0 0xe1824000 0x800>;
1934 + status = "disabled";
1935 +
1936 + uart3: serial@200 {
1937 + compatible = "atmel,at91sam9260-usart";
1938 + reg = <0x200 0x200>;
1939 + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1940 + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
1941 + clock-names = "usart";
1942 + dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
1943 + <&dma1 AT91_XDMAC_DT_PERID(11)>;
1944 + dma-names = "tx", "rx";
1945 + atmel,use-dma-rx;
1946 + atmel,use-dma-tx;
1947 + status = "disabled";
1948 + };
1949 + };
1950 +
1951 + trng: rng@e2010000 {
1952 + compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
1953 + reg = <0xe2010000 0x100>;
1954 + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1955 + clocks = <&pmc PMC_TYPE_PERIPHERAL 97>;
1956 + status = "disabled";
1957 + };
1958 +
1959 + flx4: flexcom@e2018000 {
1960 + compatible = "atmel,sama5d2-flexcom";
1961 + reg = <0xe2018000 0x200>;
1962 + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
1963 + #address-cells = <1>;
1964 + #size-cells = <1>;
1965 + ranges = <0x0 0xe2018000 0x800>;
1966 + status = "disabled";
1967 +
1968 + uart4: serial@200 {
1969 + compatible = "atmel,at91sam9260-usart";
1970 + reg = <0x200 0x200>;
1971 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1972 + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
1973 + clock-names = "usart";
1974 + dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
1975 + <&dma1 AT91_XDMAC_DT_PERID(13)>;
1976 + dma-names = "tx", "rx";
1977 + atmel,use-dma-rx;
1978 + atmel,use-dma-tx;
1979 + atmel,fifo-size = <16>;
1980 + status = "disabled";
1981 + };
1982 + };
1983 +
1984 + flx7: flexcom@e2024000 {
1985 + compatible = "atmel,sama5d2-flexcom";
1986 + reg = <0xe2024000 0x200>;
1987 + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
1988 + #address-cells = <1>;
1989 + #size-cells = <1>;
1990 + ranges = <0x0 0xe2024000 0x800>;
1991 + status = "disabled";
1992 +
1993 + uart7: serial@200 {
1994 + compatible = "atmel,at91sam9260-usart";
1995 + reg = <0x200 0x200>;
1996 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1997 + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
1998 + clock-names = "usart";
1999 + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
2000 + <&dma1 AT91_XDMAC_DT_PERID(19)>;
2001 + dma-names = "tx", "rx";
2002 + atmel,use-dma-rx;
2003 + atmel,use-dma-tx;
2004 + atmel,fifo-size = <16>;
2005 + status = "disabled";
2006 + };
2007 + };
2008 +
2009 + gmac0: ethernet@e2800000 {
2010 + compatible = "microchip,sama7g5-gem";
2011 + reg = <0xe2800000 0x1000>;
2012 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
2013 + GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
2014 + GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
2015 + GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
2016 + GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
2017 + GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2018 + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
2019 + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
2020 + assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
2021 + assigned-clock-rates = <125000000>;
2022 + status = "disabled";
2023 + };
2024 +
2025 + gmac1: ethernet@e2804000 {
2026 + compatible = "microchip,sama7g5-emac";
2027 + reg = <0xe2804000 0x1000>;
2028 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
2029 + GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
2030 + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
2031 + clock-names = "pclk", "hclk";
2032 + status = "disabled";
2033 + };
2034 +
2035 + dma0: dma-controller@e2808000 {
2036 + compatible = "microchip,sama7g5-dma";
2037 + reg = <0xe2808000 0x1000>;
2038 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2039 + #dma-cells = <1>;
2040 + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
2041 + clock-names = "dma_clk";
2042 + status = "disabled";
2043 + };
2044 +
2045 + dma1: dma-controller@e280c000 {
2046 + compatible = "microchip,sama7g5-dma";
2047 + reg = <0xe280c000 0x1000>;
2048 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
2049 + #dma-cells = <1>;
2050 + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
2051 + clock-names = "dma_clk";
2052 + status = "disabled";
2053 + };
2054 +
2055 + /* Place dma2 here despite it's address */
2056 + dma2: dma-controller@e1200000 {
2057 + compatible = "microchip,sama7g5-dma";
2058 + reg = <0xe1200000 0x1000>;
2059 + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2060 + #dma-cells = <1>;
2061 + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
2062 + clock-names = "dma_clk";
2063 + dma-requests = <0>;
2064 + status = "disabled";
2065 + };
2066 +
2067 + flx8: flexcom@e2818000 {
2068 + compatible = "atmel,sama5d2-flexcom";
2069 + reg = <0xe2818000 0x200>;
2070 + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
2071 + #address-cells = <1>;
2072 + #size-cells = <1>;
2073 + ranges = <0x0 0xe2818000 0x800>;
2074 + status = "disabled";
2075 +
2076 + i2c8: i2c@600 {
2077 + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
2078 + reg = <0x600 0x200>;
2079 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2080 + #address-cells = <1>;
2081 + #size-cells = <0>;
2082 + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
2083 + atmel,fifo-size = <32>;
2084 + dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
2085 + <&dma0 AT91_XDMAC_DT_PERID(22)>;
2086 + dma-names = "rx", "tx";
2087 + atmel,use-dma-rx;
2088 + atmel,use-dma-tx;
2089 + status = "disabled";
2090 + };
2091 + };
2092 +
2093 + flx9: flexcom@e281c000 {
2094 + compatible = "atmel,sama5d2-flexcom";
2095 + reg = <0xe281c000 0x200>;
2096 + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
2097 + #address-cells = <1>;
2098 + #size-cells = <1>;
2099 + ranges = <0x0 0xe281c000 0x800>;
2100 + status = "disabled";
2101 +
2102 + i2c9: i2c@600 {
2103 + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
2104 + reg = <0x600 0x200>;
2105 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2106 + #address-cells = <1>;
2107 + #size-cells = <0>;
2108 + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
2109 + atmel,fifo-size = <32>;
2110 + dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,
2111 + <&dma0 AT91_XDMAC_DT_PERID(24)>;
2112 + dma-names = "rx", "tx";
2113 + atmel,use-dma-rx;
2114 + atmel,use-dma-tx;
2115 + status = "disabled";
2116 + };
2117 + };
2118 +
2119 + flx11: flexcom@e2824000 {
2120 + compatible = "atmel,sama5d2-flexcom";
2121 + reg = <0xe2824000 0x200>;
2122 + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
2123 + #address-cells = <1>;
2124 + #size-cells = <1>;
2125 + ranges = <0x0 0xe2824000 0x800>;
2126 + status = "disabled";
2127 +
2128 + spi11: spi@400 {
2129 + compatible = "atmel,at91rm9200-spi";
2130 + reg = <0x400 0x200>;
2131 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2132 + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
2133 + clock-names = "spi_clk";
2134 + #address-cells = <1>;
2135 + #size-cells = <0>;
2136 + atmel,fifo-size = <32>;
2137 + dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
2138 + <&dma0 AT91_XDMAC_DT_PERID(28)>;
2139 + dma-names = "rx", "tx";
2140 + status = "disabled";
2141 + };
2142 + };
2143 +
2144 + gic: interrupt-controller@e8c11000 {
2145 + compatible = "arm,cortex-a7-gic";
2146 + #interrupt-cells = <3>;
2147 + #address-cells = <0>;
2148 + interrupt-controller;
2149 + interrupt-parent;
2150 + reg = <0xe8c11000 0x1000>,
2151 + <0xe8c12000 0x2000>;
2152 + };
2153 + };
2154 +};
Staging tree of Daniel Golle