target/linux/at91/patches-5.10/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch

   1 From 372fa27d07f66f97a4bf45621c1b840ce8417a85 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Mon, 23 Aug 2021 16:19:15 +0300
   4 Subject: [PATCH 226/247] ARM: dts: at91: sama7g5: add shdwc node
   5
   6 Add shutdown controller node and enable it.
   7
   8 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
   9 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  10 Link: https://lore.kernel.org/r/20210823131915.23857-5-claudiu.beznea@microchip.com
  11 ---
  12  arch/arm/boot/dts/at91-sama7g5ek.dts |  9 +++++++++
  13  arch/arm/boot/dts/sama7g5.dtsi       | 11 +++++++++++
  14  2 files changed, 20 insertions(+)
  15
  16 diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
  17 index 4cbed98cc2f4..8b13b031a167 100644
  18 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts
  19 +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
  20 @@ -634,6 +634,15 @@ &sdmmc2 {
  21         pinctrl-0 = <&pinctrl_sdmmc2_default>;
  22  };
  23
  24 +&shdwc {
  25 +       atmel,shdwc-debouncer = <976>;
  26 +       status = "okay";
  27 +
  28 +       input@0 {
  29 +               reg = <0>;
  30 +       };
  31 +};
  32 +
  33  &spdifrx {
  34         pinctrl-names = "default";
  35         pinctrl-0 = <&pinctrl_spdifrx_default>;
  36 diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
  37 index 3a4315ac0eb0..e50806cf7660 100644
  38 --- a/arch/arm/boot/dts/sama7g5.dtsi
  39 +++ b/arch/arm/boot/dts/sama7g5.dtsi
  40 @@ -122,6 +122,17 @@ pmc: pmc@e0018000 {
  41                         clock-names = "td_slck", "md_slck", "main_xtal";
  42                 };
  43
  44 +               shdwc: shdwc@e001d010 {
  45 +                       compatible = "microchip,sama7g5-shdwc", "syscon";
  46 +                       reg = <0xe001d010 0x10>;
  47 +                       clocks = <&clk32k 0>;
  48 +                       #address-cells = <1>;
  49 +                       #size-cells = <0>;
  50 +                       atmel,wakeup-rtc-timer;
  51 +                       atmel,wakeup-rtt-timer;
  52 +                       status = "disabled";
  53 +               };
  54 +
  55                 rtt: rtt@e001d020 {
  56                         compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
  57                         reg = <0xe001d020 0x30>;
  58 --
  59 2.32.0
  60