target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch

   1 From 6075bbc75e55258a762d618cd459dbe0dd38aff9 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 30 Sep 2021 18:42:19 +0300
   4 Subject: [PATCH 231/247] ARM: at91: pm: preload base address of controllers in
   5  tlb
   6
   7 In suspend/resume procedure for AT91 architecture different controllers
   8 (PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings
   9 for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh
  10 support for sama7g5") introduced the access to RAMC PHY controller for
  11 SAMA7G5. The access to this controller is done after RAMC ports are
  12 closed, thus any TLB walk necessary for RAMC PHY virtual address will
  13 fail. In the development branch this was not encountered. However, on
  14 current kernel the issue is reproducible.
  15
  16 To solve the issue the previous mechanism of pre-loading the TLB with
  17 the RAMC PHY virtual address has been used. However, only the addition
  18 of this new pre-load breaks the functionality for ARMv5 based
  19 devices (SAM9X60). This behavior has been encountered previously
  20 while debugging this code and using the same mechanism for pre-loading
  21 address for different controllers (e.g. pin controller, the assumption
  22 being that other requested translations are replaced from TLB).
  23
  24 To solve this new issue the TLB flush + the extension of pre-loading
  25 the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The
  26 rest of the controllers should have been pre-loaded previously, anyway.
  27
  28 Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5")
  29 Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading")
  30 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  31 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  32 Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com
  33 ---
  34  arch/arm/mach-at91/pm_suspend.S | 25 ++++++++++++++++++++++++-
  35  1 file changed, 24 insertions(+), 1 deletion(-)
  36
  37 diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
  38 index 34f251fdb743..fdb4f63ecde4 100644
  39 --- a/arch/arm/mach-at91/pm_suspend.S
  40 +++ b/arch/arm/mach-at91/pm_suspend.S
  41 @@ -1014,6 +1014,10 @@ ENTRY(at91_pm_suspend_in_sram)
  42         mov     tmp1, #0
  43         mcr     p15, 0, tmp1, c7, c10, 4
  44
  45 +       /* Flush tlb. */
  46 +       mov     r4, #0
  47 +       mcr     p15, 0, r4, c8, c7, 0
  48 +
  49         ldr     tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
  50         str     tmp1, .mckr_offset
  51         ldr     tmp1, [r0, #PM_DATA_PMC_VERSION]
  52 @@ -1023,23 +1027,42 @@ ENTRY(at91_pm_suspend_in_sram)
  53         ldr     tmp1, [r0, #PM_DATA_MODE]
  54         str     tmp1, .pm_mode
  55
  56 +       /*
  57 +        * ldrne below are here to preload their address in the TLB as access
  58 +        * to RAM may be limited while in self-refresh.
  59 +        */
  60         ldr     tmp1, [r0, #PM_DATA_PMC]
  61         str     tmp1, .pmc_base
  62 +       cmp     tmp1, #0
  63 +       ldrne   tmp2, [tmp1, #0]
  64 +
  65         ldr     tmp1, [r0, #PM_DATA_RAMC0]
  66         str     tmp1, .sramc_base
  67 +       cmp     tmp1, #0
  68 +       ldrne   tmp2, [tmp1, #0]
  69 +
  70         ldr     tmp1, [r0, #PM_DATA_RAMC1]
  71         str     tmp1, .sramc1_base
  72 +       cmp     tmp1, #0
  73 +       ldrne   tmp2, [tmp1, #0]
  74 +
  75 +#ifndef CONFIG_SOC_SAM_V4_V5
  76 +       /* ldrne below are here to preload their address in the TLB */
  77         ldr     tmp1, [r0, #PM_DATA_RAMC_PHY]
  78         str     tmp1, .sramc_phy_base
  79 -       /* Both ldrne below are here to preload their address in the TLB */
  80 +       cmp     tmp1, #0
  81 +       ldrne   tmp2, [tmp1, #0]
  82 +
  83         ldr     tmp1, [r0, #PM_DATA_SHDWC]
  84         str     tmp1, .shdwc
  85         cmp     tmp1, #0
  86         ldrne   tmp2, [tmp1, #0]
  87 +
  88         ldr     tmp1, [r0, #PM_DATA_SFRBU]
  89         str     tmp1, .sfrbu
  90         cmp     tmp1, #0
  91         ldrne   tmp2, [tmp1, #0x10]
  92 +#endif
  93
  94         /* Active the self-refresh mode */
  95         at91_sramc_self_refresh_ena
  96 --
  97 2.32.0
  98