target/linux/at91/patches-5.10/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch

   1 From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Wed, 15 Sep 2021 10:48:35 +0300
   4 Subject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate
   5  settings for GMACs
   6
   7 Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain
   8 GMAC's MDIO pins should be configured with slew-rate enabled, while the
   9 data + signaling pins should be configured with slew-rate disabled when
  10 GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets
  11 the slew-rate as enabled for all pins. Adapt the device tree to comply
  12 with these.
  13
  14 Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
  15 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  16 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  17 Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com
  18 ---
  19  arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------
  20  1 file changed, 22 insertions(+), 6 deletions(-)
  21
  22 diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
  23 index f0772fa01751..30b67cad5f14 100644
  24 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts
  25 +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
  26 @@ -355,7 +355,10 @@ &gmac0 {
  27         #address-cells = <1>;
  28         #size-cells = <0>;
  29         pinctrl-names = "default";
  30 -       pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;
  31 +       pinctrl-0 = <&pinctrl_gmac0_default
  32 +                    &pinctrl_gmac0_mdio_default
  33 +                    &pinctrl_gmac0_txck_default
  34 +                    &pinctrl_gmac0_phy_irq>;
  35         phy-mode = "rgmii-id";
  36         status = "okay";
  37
  38 @@ -370,7 +373,9 @@ &gmac1 {
  39         #address-cells = <1>;
  40         #size-cells = <0>;
  41         pinctrl-names = "default";
  42 -       pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;
  43 +       pinctrl-0 = <&pinctrl_gmac1_default
  44 +                    &pinctrl_gmac1_mdio_default
  45 +                    &pinctrl_gmac1_phy_irq>;
  46         phy-mode = "rmii";
  47         status = "okay";
  48
  49 @@ -425,14 +430,20 @@ pinctrl_gmac0_default: gmac0_default {
  50                          <PIN_PA15__G0_TXEN>,
  51                          <PIN_PA30__G0_RXCK>,
  52                          <PIN_PA18__G0_RXDV>,
  53 -                        <PIN_PA22__G0_MDC>,
  54 -                        <PIN_PA23__G0_MDIO>,
  55                          <PIN_PA25__G0_125CK>;
  56 +               slew-rate = <0>;
  57 +               bias-disable;
  58 +       };
  59 +
  60 +       pinctrl_gmac0_mdio_default: gmac0_mdio_default {
  61 +               pinmux = <PIN_PA22__G0_MDC>,
  62 +                        <PIN_PA23__G0_MDIO>;
  63                 bias-disable;
  64         };
  65
  66         pinctrl_gmac0_txck_default: gmac0_txck_default {
  67                 pinmux = <PIN_PA24__G0_TXCK>;
  68 +               slew-rate = <0>;
  69                 bias-pull-up;
  70         };
  71
  72 @@ -449,8 +460,13 @@ pinctrl_gmac1_default: gmac1_default {
  73                          <PIN_PD25__G1_RX0>,
  74                          <PIN_PD26__G1_RX1>,
  75                          <PIN_PD27__G1_RXER>,
  76 -                        <PIN_PD24__G1_RXDV>,
  77 -                        <PIN_PD28__G1_MDC>,
  78 +                        <PIN_PD24__G1_RXDV>;
  79 +               slew-rate = <0>;
  80 +               bias-disable;
  81 +       };
  82 +
  83 +       pinctrl_gmac1_mdio_default: gmac1_mdio_default {
  84 +               pinmux = <PIN_PD28__G1_MDC>,
  85                          <PIN_PD29__G1_MDIO>;
  86                 bias-disable;
  87         };
  88 --
  89 2.32.0
  90