1 From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001
2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
3 Date: Wed, 15 Sep 2021 10:48:35 +0300
4 Subject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate
7 Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain
8 GMAC's MDIO pins should be configured with slew-rate enabled, while the
9 data + signaling pins should be configured with slew-rate disabled when
10 GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets
11 the slew-rate as enabled for all pins. Adapt the device tree to comply
14 Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
15 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
16 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
17 Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com
19 arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------
20 1 file changed, 22 insertions(+), 6 deletions(-)
22 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts
23 +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
27 pinctrl-names = "default";
28 - pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;
29 + pinctrl-0 = <&pinctrl_gmac0_default
30 + &pinctrl_gmac0_mdio_default
31 + &pinctrl_gmac0_txck_default
32 + &pinctrl_gmac0_phy_irq>;
33 phy-mode = "rgmii-id";
39 pinctrl-names = "default";
40 - pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;
41 + pinctrl-0 = <&pinctrl_gmac1_default
42 + &pinctrl_gmac1_mdio_default
43 + &pinctrl_gmac1_phy_irq>;
52 - <PIN_PA23__G0_MDIO>,
58 + pinctrl_gmac0_mdio_default: gmac0_mdio_default {
59 + pinmux = <PIN_PA22__G0_MDC>,
60 + <PIN_PA23__G0_MDIO>;
64 pinctrl_gmac0_txck_default: gmac0_txck_default {
65 pinmux = <PIN_PA24__G0_TXCK>;
74 - <PIN_PD24__G1_RXDV>,
76 + <PIN_PD24__G1_RXDV>;
81 + pinctrl_gmac1_mdio_default: gmac1_mdio_default {
82 + pinmux = <PIN_PD28__G1_MDC>,