target/linux/at91/patches-5.10/237-clk-at91-clk-master-add-register-definition-for-sama.patch

   1 From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Mon, 11 Oct 2021 14:27:08 +0300
   4 Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for
   5  sama7g5's master clock
   6
   7 SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
   8 register at offset 0x30 (relative to PMC). In the last/first phase of
   9 suspend/resume procedure (which is architecture specific) the parent
  10 of master clocks are changed (via assembly code) for more power saving
  11 (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
  12 and at91_mckx_ps_restore). Thus the macros corresponding to register
  13 at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
  14 commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's
  15 master clock") introduced the proper macros but didn't adapted the
  16 clk-master.c as well. Thus, this commit adapt the clk-master.c to use
  17 the macros introduced in commit ec03f18cc222 ("clk: at91: add register
  18 definition for sama7g5's master clock").
  19
  20 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  21 Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com
  22 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  23 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  24 ---
  25  drivers/clk/at91/clk-master.c | 50 ++++++++++++++++-------------------
  26  1 file changed, 23 insertions(+), 27 deletions(-)
  27
  28 diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
  29 index f75549fff023..88f7af1bfff6 100644
  30 --- a/drivers/clk/at91/clk-master.c
  31 +++ b/drivers/clk/at91/clk-master.c
  32 @@ -17,15 +17,7 @@
  33  #define MASTER_DIV_SHIFT       8
  34  #define MASTER_DIV_MASK                0x7
  35
  36 -#define PMC_MCR                        0x30
  37 -#define PMC_MCR_ID_MSK         GENMASK(3, 0)
  38 -#define PMC_MCR_CMD            BIT(7)
  39 -#define PMC_MCR_DIV            GENMASK(10, 8)
  40 -#define PMC_MCR_CSS            GENMASK(20, 16)
  41  #define PMC_MCR_CSS_SHIFT      (16)
  42 -#define PMC_MCR_EN             BIT(28)
  43 -
  44 -#define PMC_MCR_ID(x)          ((x) & PMC_MCR_ID_MSK)
  45
  46  #define MASTER_MAX_ID          4
  47
  48 @@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struct clk_master *master,
  49  {
  50         unsigned long flags;
  51         unsigned int val, cparent;
  52 -       unsigned int enable = status ? PMC_MCR_EN : 0;
  53 +       unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
  54
  55         spin_lock_irqsave(master->lock, flags);
  56
  57 -       regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
  58 -       regmap_read(master->regmap, PMC_MCR, &val);
  59 -       regmap_update_bits(master->regmap, PMC_MCR,
  60 -                          enable | PMC_MCR_CSS | PMC_MCR_DIV |
  61 -                          PMC_MCR_CMD | PMC_MCR_ID_MSK,
  62 +       regmap_write(master->regmap, AT91_PMC_MCR_V2,
  63 +                    AT91_PMC_MCR_V2_ID(master->id));
  64 +       regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
  65 +       regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
  66 +                          enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
  67 +                          AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
  68                            enable | (master->parent << PMC_MCR_CSS_SHIFT) |
  69                            (master->div << MASTER_DIV_SHIFT) |
  70 -                          PMC_MCR_CMD | PMC_MCR_ID(master->id));
  71 +                          AT91_PMC_MCR_V2_CMD |
  72 +                          AT91_PMC_MCR_V2_ID(master->id));
  73
  74 -       cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
  75 +       cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
  76
  77         /* Wait here only if parent is being changed. */
  78         while ((cparent != master->parent) && !clk_master_ready(master))
  79 @@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(struct clk_hw *hw)
  80
  81         spin_lock_irqsave(master->lock, flags);
  82
  83 -       regmap_write(master->regmap, PMC_MCR, master->id);
  84 -       regmap_update_bits(master->regmap, PMC_MCR,
  85 -                          PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
  86 -                          PMC_MCR_CMD | PMC_MCR_ID(master->id));
  87 +       regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
  88 +       regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
  89 +                          AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |
  90 +                          AT91_PMC_MCR_V2_ID_MSK,
  91 +                          AT91_PMC_MCR_V2_CMD |
  92 +                          AT91_PMC_MCR_V2_ID(master->id));
  93
  94         spin_unlock_irqrestore(master->lock, flags);
  95  }
  96 @@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled(struct clk_hw *hw)
  97
  98         spin_lock_irqsave(master->lock, flags);
  99
 100 -       regmap_write(master->regmap, PMC_MCR, master->id);
 101 -       regmap_read(master->regmap, PMC_MCR, &val);
 102 +       regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
 103 +       regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
 104
 105         spin_unlock_irqrestore(master->lock, flags);
 106
 107 -       return !!(val & PMC_MCR_EN);
 108 +       return !!(val & AT91_PMC_MCR_V2_EN);
 109  }
 110
 111  static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
 112 @@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct regmap *regmap,
 113         master->mux_table = mux_table;
 114
 115         spin_lock_irqsave(master->lock, flags);
 116 -       regmap_write(master->regmap, PMC_MCR, master->id);
 117 -       regmap_read(master->regmap, PMC_MCR, &val);
 118 -       master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
 119 -       master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;
 120 +       regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
 121 +       regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
 122 +       master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
 123 +       master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
 124         spin_unlock_irqrestore(master->lock, flags);
 125
 126         hw = &master->hw;
 127 --
 128 2.32.0
 129