target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch

   1 From bb8e6ca274763fa98613dbe8b0833348a1d8fe4d Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Mon, 11 Oct 2021 14:27:12 +0300
   4 Subject: [PATCH 240/247] clk: at91: clk-master: check if div or pres is zero
   5
   6 Check if div or pres is zero before using it as argument for ffs().
   7 In case div is zero ffs() will return 0 and thus substracting from
   8 zero will lead to invalid values to be setup in registers.
   9
  10 Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
  11 Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5")
  12 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  13 Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com
  14 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/at91/clk-master.c | 4 ++--
  18  1 file changed, 2 insertions(+), 2 deletions(-)
  19
  20 diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
  21 index 9a2c8e64cacf..2093e13b5068 100644
  22 --- a/drivers/clk/at91/clk-master.c
  23 +++ b/drivers/clk/at91/clk-master.c
  24 @@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,
  25
  26         else if (pres == 3)
  27                 pres = MASTER_PRES_MAX;
  28 -       else
  29 +       else if (pres)
  30                 pres = ffs(pres) - 1;
  31
  32         spin_lock_irqsave(master->lock, flags);
  33 @@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
  34
  35         if (div == 3)
  36                 div = MASTER_PRES_MAX;
  37 -       else
  38 +       else if (div)
  39                 div = ffs(div) - 1;
  40
  41         spin_lock_irqsave(master->lock, flags);
  42 --
  43 2.32.0
  44