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[openwrt/staging/dedeckeh.git] / target / linux / at91 / patches-5.10 / 244-clk-at91-clk-master-add-notifier-for-divider.patch
1 From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001
2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
3 Date: Mon, 11 Oct 2021 14:27:16 +0300
4 Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider
5
6 SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
7 parent with cpuck as seen in the following clock tree:
8
9 +----------> cpuck
10 |
11 FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
12
13 mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
14 while changing FRAC PLL or DIV PLL the commit implements a notifier for
15 mck0 which applies a safe divider to register (maximum value of the divider
16 which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
17 overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
18 events.
19
20 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
21 Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
22 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
23 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
24 ---
25 drivers/clk/at91/at91rm9200.c | 2 +-
26 drivers/clk/at91/at91sam9260.c | 2 +-
27 drivers/clk/at91/at91sam9g45.c | 2 +-
28 drivers/clk/at91/at91sam9n12.c | 2 +-
29 drivers/clk/at91/at91sam9rl.c | 2 +-
30 drivers/clk/at91/at91sam9x5.c | 2 +-
31 drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++----------
32 drivers/clk/at91/dt-compat.c | 2 +-
33 drivers/clk/at91/pmc.h | 2 +-
34 drivers/clk/at91/sama5d2.c | 2 +-
35 drivers/clk/at91/sama5d3.c | 2 +-
36 drivers/clk/at91/sama5d4.c | 2 +-
37 drivers/clk/at91/sama7g5.c | 2 +-
38 13 files changed, 186 insertions(+), 82 deletions(-)
39
40 diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c
41 index 428a6f4b9ebc..fff4fdda974f 100644
42 --- a/drivers/clk/at91/at91rm9200.c
43 +++ b/drivers/clk/at91/at91rm9200.c
44 @@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
45 "masterck_pres",
46 &at91rm9200_master_layout,
47 &rm9200_mck_characteristics,
48 - &rm9200_mck_lock, CLK_SET_RATE_GATE);
49 + &rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
50 if (IS_ERR(hw))
51 goto err_free;
52
53 diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
54 index b29843bea278..79802f864ee5 100644
55 --- a/drivers/clk/at91/at91sam9260.c
56 +++ b/drivers/clk/at91/at91sam9260.c
57 @@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
58 &at91rm9200_master_layout,
59 data->mck_characteristics,
60 &at91sam9260_mck_lock,
61 - CLK_SET_RATE_GATE);
62 + CLK_SET_RATE_GATE, 0);
63 if (IS_ERR(hw))
64 goto err_free;
65
66 diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c
67 index 15da0dfe3ef2..7ed984f8058c 100644
68 --- a/drivers/clk/at91/at91sam9g45.c
69 +++ b/drivers/clk/at91/at91sam9g45.c
70 @@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
71 &at91rm9200_master_layout,
72 &mck_characteristics,
73 &at91sam9g45_mck_lock,
74 - CLK_SET_RATE_GATE);
75 + CLK_SET_RATE_GATE, 0);
76 if (IS_ERR(hw))
77 goto err_free;
78
79 diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c
80 index 7fe435f4b46b..63cc58944b00 100644
81 --- a/drivers/clk/at91/at91sam9n12.c
82 +++ b/drivers/clk/at91/at91sam9n12.c
83 @@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
84 &at91sam9x5_master_layout,
85 &mck_characteristics,
86 &at91sam9n12_mck_lock,
87 - CLK_SET_RATE_GATE);
88 + CLK_SET_RATE_GATE, 0);
89 if (IS_ERR(hw))
90 goto err_free;
91
92 diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
93 index ecbabf5162bd..4d4faf6c61d8 100644
94 --- a/drivers/clk/at91/at91sam9rl.c
95 +++ b/drivers/clk/at91/at91sam9rl.c
96 @@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
97 "masterck_pres",
98 &at91rm9200_master_layout,
99 &sam9rl_mck_characteristics,
100 - &sam9rl_mck_lock, CLK_SET_RATE_GATE);
101 + &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
102 if (IS_ERR(hw))
103 goto err_free;
104
105 diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
106 index 5cce48c64ea2..bd8007b4f3e0 100644
107 --- a/drivers/clk/at91/at91sam9x5.c
108 +++ b/drivers/clk/at91/at91sam9x5.c
109 @@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
110 "masterck_pres",
111 &at91sam9x5_master_layout,
112 &mck_characteristics, &mck_lock,
113 - CLK_SET_RATE_GATE);
114 + CLK_SET_RATE_GATE, 0);
115 if (IS_ERR(hw))
116 goto err_free;
117
118 diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
119 index e67bcd03a827..b2d0a7f4f7f9 100644
120 --- a/drivers/clk/at91/clk-master.c
121 +++ b/drivers/clk/at91/clk-master.c
122 @@ -5,6 +5,7 @@
123
124 #include <linux/clk-provider.h>
125 #include <linux/clkdev.h>
126 +#include <linux/clk.h>
127 #include <linux/clk/at91_pmc.h>
128 #include <linux/of.h>
129 #include <linux/mfd/syscon.h>
130 @@ -36,8 +37,12 @@ struct clk_master {
131 u8 id;
132 u8 parent;
133 u8 div;
134 + u32 safe_div;
135 };
136
137 +/* MCK div reference to be used by notifier. */
138 +static struct clk_master *master_div;
139 +
140 static inline bool clk_master_ready(struct clk_master *master)
141 {
142 unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
143 @@ -153,107 +158,81 @@ static const struct clk_ops master_div_ops = {
144 .restore_context = clk_master_div_restore_context,
145 };
146
147 -static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
148 - unsigned long parent_rate)
149 +/* This function must be called with lock acquired. */
150 +static int clk_master_div_set(struct clk_master *master,
151 + unsigned long parent_rate, int div)
152 {
153 - struct clk_master *master = to_clk_master(hw);
154 const struct clk_master_characteristics *characteristics =
155 master->characteristics;
156 - unsigned long flags;
157 - unsigned int mckr, tmp;
158 - int div, i;
159 + unsigned long rate = parent_rate;
160 + unsigned int max_div = 0, div_index = 0, max_div_index = 0;
161 + unsigned int i, mckr, tmp;
162 int ret;
163
164 - div = DIV_ROUND_CLOSEST(parent_rate, rate);
165 - if (div > ARRAY_SIZE(characteristics->divisors))
166 - return -EINVAL;
167 -
168 for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
169 if (!characteristics->divisors[i])
170 break;
171
172 - if (div == characteristics->divisors[i]) {
173 - div = i;
174 - break;
175 + if (div == characteristics->divisors[i])
176 + div_index = i;
177 +
178 + if (max_div < characteristics->divisors[i]) {
179 + max_div = characteristics->divisors[i];
180 + max_div_index = i;
181 }
182 }
183
184 - if (i == ARRAY_SIZE(characteristics->divisors))
185 - return -EINVAL;
186 + if (div > max_div)
187 + div_index = max_div_index;
188
189 - spin_lock_irqsave(master->lock, flags);
190 ret = regmap_read(master->regmap, master->layout->offset, &mckr);
191 if (ret)
192 - goto unlock;
193 + return ret;
194
195 mckr &= master->layout->mask;
196 tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
197 - if (tmp == div)
198 - goto unlock;
199 + if (tmp == div_index)
200 + return 0;
201 +
202 + rate /= characteristics->divisors[div_index];
203 + if (rate < characteristics->output.min)
204 + pr_warn("master clk div is underclocked");
205 + else if (rate > characteristics->output.max)
206 + pr_warn("master clk div is overclocked");
207
208 mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
209 - mckr |= (div << MASTER_DIV_SHIFT);
210 + mckr |= (div_index << MASTER_DIV_SHIFT);
211 ret = regmap_write(master->regmap, master->layout->offset, mckr);
212 if (ret)
213 - goto unlock;
214 + return ret;
215
216 while (!clk_master_ready(master))
217 cpu_relax();
218 -unlock:
219 - spin_unlock_irqrestore(master->lock, flags);
220 +
221 + master->div = characteristics->divisors[div_index];
222
223 return 0;
224 }
225
226 -static int clk_master_div_determine_rate(struct clk_hw *hw,
227 - struct clk_rate_request *req)
228 +static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw,
229 + unsigned long parent_rate)
230 {
231 struct clk_master *master = to_clk_master(hw);
232 - const struct clk_master_characteristics *characteristics =
233 - master->characteristics;
234 - struct clk_hw *parent;
235 - unsigned long parent_rate, tmp_rate, best_rate = 0;
236 - int i, best_diff = INT_MIN, tmp_diff;
237 -
238 - parent = clk_hw_get_parent(hw);
239 - if (!parent)
240 - return -EINVAL;
241 -
242 - parent_rate = clk_hw_get_rate(parent);
243 - if (!parent_rate)
244 - return -EINVAL;
245 -
246 - for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
247 - if (!characteristics->divisors[i])
248 - break;
249
250 - tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,
251 - characteristics->divisors[i]);
252 - tmp_diff = abs(tmp_rate - req->rate);
253 -
254 - if (!best_rate || best_diff > tmp_diff) {
255 - best_diff = tmp_diff;
256 - best_rate = tmp_rate;
257 - }
258 -
259 - if (!best_diff)
260 - break;
261 - }
262 -
263 - req->best_parent_rate = best_rate;
264 - req->best_parent_hw = parent;
265 - req->rate = best_rate;
266 -
267 - return 0;
268 + return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);
269 }
270
271 static void clk_master_div_restore_context_chg(struct clk_hw *hw)
272 {
273 struct clk_master *master = to_clk_master(hw);
274 + unsigned long flags;
275 int ret;
276
277 - ret = clk_master_div_set_rate(hw, master->pms.rate,
278 - master->pms.parent_rate);
279 + spin_lock_irqsave(master->lock, flags);
280 + ret = clk_master_div_set(master, master->pms.parent_rate,
281 + DIV_ROUND_CLOSEST(master->pms.parent_rate,
282 + master->pms.rate));
283 + spin_unlock_irqrestore(master->lock, flags);
284 if (ret)
285 pr_warn("Failed to restore MCK DIV clock\n");
286 }
287 @@ -261,13 +240,116 @@ static void clk_master_div_restore_context_chg(struct clk_hw *hw)
288 static const struct clk_ops master_div_ops_chg = {
289 .prepare = clk_master_prepare,
290 .is_prepared = clk_master_is_prepared,
291 - .recalc_rate = clk_master_div_recalc_rate,
292 - .determine_rate = clk_master_div_determine_rate,
293 - .set_rate = clk_master_div_set_rate,
294 + .recalc_rate = clk_master_div_recalc_rate_chg,
295 .save_context = clk_master_div_save_context,
296 .restore_context = clk_master_div_restore_context_chg,
297 };
298
299 +static int clk_master_div_notifier_fn(struct notifier_block *notifier,
300 + unsigned long code, void *data)
301 +{
302 + const struct clk_master_characteristics *characteristics =
303 + master_div->characteristics;
304 + struct clk_notifier_data *cnd = data;
305 + unsigned long flags, new_parent_rate, new_rate;
306 + unsigned int mckr, div, new_div = 0;
307 + int ret, i;
308 + long tmp_diff;
309 + long best_diff = -1;
310 +
311 + spin_lock_irqsave(master_div->lock, flags);
312 + switch (code) {
313 + case PRE_RATE_CHANGE:
314 + /*
315 + * We want to avoid any overclocking of MCK DIV domain. To do
316 + * this we set a safe divider (the underclocking is not of
317 + * interest as we can go as low as 32KHz). The relation
318 + * b/w this clock and its parents are as follows:
319 + *
320 + * FRAC PLL -> DIV PLL -> MCK DIV
321 + *
322 + * With the proper safe divider we should be good even with FRAC
323 + * PLL at its maximum value.
324 + */
325 + ret = regmap_read(master_div->regmap, master_div->layout->offset,
326 + &mckr);
327 + if (ret) {
328 + ret = NOTIFY_STOP_MASK;
329 + goto unlock;
330 + }
331 +
332 + mckr &= master_div->layout->mask;
333 + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
334 +
335 + /* Switch to safe divider. */
336 + clk_master_div_set(master_div,
337 + cnd->old_rate * characteristics->divisors[div],
338 + master_div->safe_div);
339 + break;
340 +
341 + case POST_RATE_CHANGE:
342 + /*
343 + * At this point we want to restore MCK DIV domain to its maximum
344 + * allowed rate.
345 + */
346 + ret = regmap_read(master_div->regmap, master_div->layout->offset,
347 + &mckr);
348 + if (ret) {
349 + ret = NOTIFY_STOP_MASK;
350 + goto unlock;
351 + }
352 +
353 + mckr &= master_div->layout->mask;
354 + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
355 + new_parent_rate = cnd->new_rate * characteristics->divisors[div];
356 +
357 + for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
358 + if (!characteristics->divisors[i])
359 + break;
360 +
361 + new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate,
362 + characteristics->divisors[i]);
363 +
364 + tmp_diff = characteristics->output.max - new_rate;
365 + if (tmp_diff < 0)
366 + continue;
367 +
368 + if (best_diff < 0 || best_diff > tmp_diff) {
369 + new_div = characteristics->divisors[i];
370 + best_diff = tmp_diff;
371 + }
372 +
373 + if (!tmp_diff)
374 + break;
375 + }
376 +
377 + if (!new_div) {
378 + ret = NOTIFY_STOP_MASK;
379 + goto unlock;
380 + }
381 +
382 + /* Update the div to preserve MCK DIV clock rate. */
383 + clk_master_div_set(master_div, new_parent_rate,
384 + new_div);
385 +
386 + ret = NOTIFY_OK;
387 + break;
388 +
389 + default:
390 + ret = NOTIFY_DONE;
391 + break;
392 + }
393 +
394 +unlock:
395 + spin_unlock_irqrestore(master_div->lock, flags);
396 +
397 + return ret;
398 +}
399 +
400 +static struct notifier_block clk_master_div_notifier = {
401 + .notifier_call = clk_master_div_notifier_fn,
402 +};
403 +
404 static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
405 struct clk_hw *parent,
406 unsigned long parent_rate,
407 @@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct regmap *regmap,
408 struct clk_master *master;
409 struct clk_init_data init;
410 struct clk_hw *hw;
411 + unsigned int mckr;
412 + unsigned long irqflags;
413 int ret;
414
415 if (!name || !num_parents || !parent_names || !lock)
416 @@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct regmap *regmap,
417 master->chg_pid = chg_pid;
418 master->lock = lock;
419
420 + if (ops == &master_div_ops_chg) {
421 + spin_lock_irqsave(master->lock, irqflags);
422 + regmap_read(master->regmap, master->layout->offset, &mckr);
423 + spin_unlock_irqrestore(master->lock, irqflags);
424 +
425 + mckr &= layout->mask;
426 + mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
427 + master->div = characteristics->divisors[mckr];
428 + }
429 +
430 hw = &master->hw;
431 ret = clk_hw_register(NULL, &master->hw);
432 if (ret) {
433 @@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regmap *regmap,
434 const char *name, const char *parent_name,
435 const struct clk_master_layout *layout,
436 const struct clk_master_characteristics *characteristics,
437 - spinlock_t *lock, u32 flags)
438 + spinlock_t *lock, u32 flags, u32 safe_div)
439 {
440 const struct clk_ops *ops;
441 + struct clk_hw *hw;
442
443 if (flags & CLK_SET_RATE_GATE)
444 ops = &master_div_ops;
445 else
446 ops = &master_div_ops_chg;
447
448 - return at91_clk_register_master_internal(regmap, name, 1,
449 - &parent_name, layout,
450 - characteristics, ops,
451 - lock, flags, -EINVAL);
452 + hw = at91_clk_register_master_internal(regmap, name, 1,
453 + &parent_name, layout,
454 + characteristics, ops,
455 + lock, flags, -EINVAL);
456 +
457 + if (!IS_ERR(hw) && safe_div) {
458 + master_div = to_clk_master(hw);
459 + master_div->safe_div = safe_div;
460 + clk_notifier_register(hw->clk,
461 + &clk_master_div_notifier);
462 + }
463 +
464 + return hw;
465 }
466
467 static unsigned long
468 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c
469 index a97b99c2dc12..ca2dbb65b9df 100644
470 --- a/drivers/clk/at91/dt-compat.c
471 +++ b/drivers/clk/at91/dt-compat.c
472 @@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_node *np,
473
474 hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
475 layout, characteristics,
476 - &mck_lock, CLK_SET_RATE_GATE);
477 + &mck_lock, CLK_SET_RATE_GATE, 0);
478 if (IS_ERR(hw))
479 goto out_free_characteristics;
480
481 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
482 index 207ecccef29f..3a1bf6194c28 100644
483 --- a/drivers/clk/at91/pmc.h
484 +++ b/drivers/clk/at91/pmc.h
485 @@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regmap *regmap, const char *name,
486 const char *parent_names,
487 const struct clk_master_layout *layout,
488 const struct clk_master_characteristics *characteristics,
489 - spinlock_t *lock, u32 flags);
490 + spinlock_t *lock, u32 flags, u32 safe_div);
491
492 struct clk_hw * __init
493 at91_clk_sama7g5_register_master(struct regmap *regmap,
494 diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
495 index 3d1f78176c3e..d027294a0089 100644
496 --- a/drivers/clk/at91/sama5d2.c
497 +++ b/drivers/clk/at91/sama5d2.c
498 @@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
499 "masterck_pres",
500 &at91sam9x5_master_layout,
501 &mck_characteristics, &mck_lock,
502 - CLK_SET_RATE_GATE);
503 + CLK_SET_RATE_GATE, 0);
504 if (IS_ERR(hw))
505 goto err_free;
506
507 diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c
508 index d376257807d2..339d0f382ff0 100644
509 --- a/drivers/clk/at91/sama5d3.c
510 +++ b/drivers/clk/at91/sama5d3.c
511 @@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
512 "masterck_pres",
513 &at91sam9x5_master_layout,
514 &mck_characteristics, &mck_lock,
515 - CLK_SET_RATE_GATE);
516 + CLK_SET_RATE_GATE, 0);
517 if (IS_ERR(hw))
518 goto err_free;
519
520 diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
521 index 5cbaac68da44..4af75b1e39e9 100644
522 --- a/drivers/clk/at91/sama5d4.c
523 +++ b/drivers/clk/at91/sama5d4.c
524 @@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
525 "masterck_pres",
526 &at91sam9x5_master_layout,
527 &mck_characteristics, &mck_lock,
528 - CLK_SET_RATE_GATE);
529 + CLK_SET_RATE_GATE, 0);
530 if (IS_ERR(hw))
531 goto err_free;
532
533 diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
534 index ae52c10af040..c66bde6f7b47 100644
535 --- a/drivers/clk/at91/sama7g5.c
536 +++ b/drivers/clk/at91/sama7g5.c
537 @@ -1003,7 +1003,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
538
539 hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
540 &mck0_layout, &mck0_characteristics,
541 - &pmc_mck0_lock, 0);
542 + &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
543 if (IS_ERR(hw))
544 goto err_free;
545
546 --
547 2.32.0
548
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