target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch

   1 From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001
   2 From: Eugen Hristev <eugen.hristev@microchip.com>
   3 Date: Tue, 13 Apr 2021 12:57:25 +0200
   4 Subject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more
   5  formats and additional pipeline modules
   6
   7 Add support for additional formats supported by newer pipelines, and for
   8 additional pipeline modules.
   9
  10 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
  11 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
  12 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
  13 ---
  14  drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++----
  15  1 file changed, 38 insertions(+), 10 deletions(-)
  16
  17 --- a/drivers/media/platform/atmel/atmel-isc-base.c
  18 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
  19 @@ -855,6 +855,8 @@ static int isc_try_validate_formats(stru
  20         case V4L2_PIX_FMT_YUV420:
  21         case V4L2_PIX_FMT_YUV422P:
  22         case V4L2_PIX_FMT_YUYV:
  23 +       case V4L2_PIX_FMT_UYVY:
  24 +       case V4L2_PIX_FMT_VYUY:
  25                 ret = 0;
  26                 yuv = true;
  27                 break;
  28 @@ -869,6 +871,7 @@ static int isc_try_validate_formats(stru
  29                 break;
  30         case V4L2_PIX_FMT_GREY:
  31         case V4L2_PIX_FMT_Y10:
  32 +       case V4L2_PIX_FMT_Y16:
  33                 ret = 0;
  34                 grey = true;
  35                 break;
  36 @@ -899,6 +902,8 @@ static int isc_try_validate_formats(stru
  37   */
  38  static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
  39  {
  40 +       isc->try_config.rlp_cfg_mode = 0;
  41 +
  42         switch (isc->try_config.fourcc) {
  43         case V4L2_PIX_FMT_SBGGR8:
  44         case V4L2_PIX_FMT_SGBRG8:
  45 @@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(str
  46                 isc->try_config.bpp = 16;
  47                 break;
  48         case V4L2_PIX_FMT_YUYV:
  49 -               isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
  50 +               isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
  51 +               isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
  52 +               isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
  53 +               isc->try_config.bpp = 16;
  54 +               break;
  55 +       case V4L2_PIX_FMT_UYVY:
  56 +               isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
  57 +               isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
  58 +               isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
  59 +               isc->try_config.bpp = 16;
  60 +               break;
  61 +       case V4L2_PIX_FMT_VYUY:
  62 +               isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
  63                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
  64                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
  65                 isc->try_config.bpp = 16;
  66 @@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(str
  67                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
  68                 isc->try_config.bpp = 8;
  69                 break;
  70 +       case V4L2_PIX_FMT_Y16:
  71 +               isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
  72 +               fallthrough;
  73         case V4L2_PIX_FMT_Y10:
  74 -               isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
  75 +               isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
  76                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
  77                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
  78                 isc->try_config.bpp = 16;
  79 @@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(st
  80                 /* if sensor format is RAW, we convert inside ISC */
  81                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
  82                         isc->try_config.bits_pipeline = CFA_ENABLE |
  83 -                               WB_ENABLE | GAM_ENABLES;
  84 +                               WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
  85 +                               CC_ENABLE;
  86                 } else {
  87                         isc->try_config.bits_pipeline = 0x0;
  88                 }
  89 @@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(st
  90                 /* if sensor format is RAW, we convert inside ISC */
  91                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
  92                         isc->try_config.bits_pipeline = CFA_ENABLE |
  93 -                               CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
  94 -                               SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
  95 +                               CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
  96 +                               SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
  97 +                               DPC_BLCENABLE;
  98                 } else {
  99                         isc->try_config.bits_pipeline = 0x0;
 100                 }
 101 @@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(st
 102                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 103                         isc->try_config.bits_pipeline = CFA_ENABLE |
 104                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 105 -                               SUB422_ENABLE | CBC_ENABLE;
 106 +                               SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 107                 } else {
 108                         isc->try_config.bits_pipeline = 0x0;
 109                 }
 110                 break;
 111         case V4L2_PIX_FMT_YUYV:
 112 +       case V4L2_PIX_FMT_UYVY:
 113 +       case V4L2_PIX_FMT_VYUY:
 114                 /* if sensor format is RAW, we convert inside ISC */
 115                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 116                         isc->try_config.bits_pipeline = CFA_ENABLE |
 117                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 118 -                               SUB422_ENABLE | CBC_ENABLE;
 119 +                               SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 120                 } else {
 121                         isc->try_config.bits_pipeline = 0x0;
 122                 }
 123                 break;
 124         case V4L2_PIX_FMT_GREY:
 125 -               if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 126 +       case V4L2_PIX_FMT_Y16:
 127                 /* if sensor format is RAW, we convert inside ISC */
 128 +               if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 129                         isc->try_config.bits_pipeline = CFA_ENABLE |
 130                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 131 -                               CBC_ENABLE;
 132 +                               CBC_ENABLE | DPC_BLCENABLE;
 133                 } else {
 134                         isc->try_config.bits_pipeline = 0x0;
 135                 }
 136                 break;
 137         default:
 138 -               isc->try_config.bits_pipeline = 0x0;
 139 +               if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
 140 +                       isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
 141 +               else
 142 +                       isc->try_config.bits_pipeline = 0x0;
 143         }
 144
 145         /* Tune the pipeline to product specific */