1 From 9ee7fd7aa956671727752dac6bd131cf511c1137 Mon Sep 17 00:00:00 2001
2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
3 Date: Thu, 15 Apr 2021 13:49:59 +0300
4 Subject: [PATCH 209/247] ARM: at91: pm: add support for MCK1..4 save/restore
7 Add support for MCK1..4 save restore for ULP modes.
9 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
10 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
11 Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com
13 arch/arm/mach-at91/pm_suspend.S | 126 ++++++++++++++++++++++++++++++++
14 1 file changed, 126 insertions(+)
16 --- a/arch/arm/mach-at91/pm_suspend.S
17 +++ b/arch/arm/mach-at91/pm_suspend.S
18 @@ -765,7 +765,122 @@ sr_dis_exit:
23 + * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
25 + * Side effects: overwrites tmp1, tmp2
27 +.macro at91_mckx_ps_enable
28 +#ifdef CONFIG_SOC_SAMA7
31 + /* There are 4 MCKs we need to handle: MCK1..4 */
36 + /* Write MCK ID to retrieve the settings. */
37 + str tmp1, [pmc, #AT91_PMC_MCR_V2]
38 + ldr tmp2, [pmc, #AT91_PMC_MCR_V2]
43 + str tmp2, .saved_mck1
49 + str tmp2, .saved_mck2
55 + str tmp2, .saved_mck3
59 + str tmp2, .saved_mck4
62 + /* Use CSS=MAINCK and DIV=1. */
63 + bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS
64 + bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV
65 + orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK
66 + orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1
67 + str tmp2, [pmc, #AT91_PMC_MCR_V2]
79 + * at91_mckx_ps_restore: restore MCK1..4 settings
81 + * Side effects: overwrites tmp1, tmp2
83 +.macro at91_mckx_ps_restore
84 +#ifdef CONFIG_SOC_SAMA7
87 + /* There are 4 MCKs we need to handle: MCK1..4 */
95 + ldr tmp2, .saved_mck1
101 + ldr tmp2, .saved_mck2
107 + ldr tmp2, .saved_mck3
111 + ldr tmp2, .saved_mck4
114 + /* Write MCK ID to retrieve the settings. */
115 + str tmp1, [pmc, #AT91_PMC_MCR_V2]
116 + ldr tmp3, [pmc, #AT91_PMC_MCR_V2]
118 + /* We need to restore CSS and DIV. */
119 + bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS
120 + bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV
121 + orr tmp3, tmp3, tmp2
122 + bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
123 + orr tmp3, tmp3, tmp1
124 + orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
125 + str tmp2, [pmc, #AT91_PMC_MCR_V2]
136 + at91_mckx_ps_enable
139 ldr tmp2, .mckr_offset
141 @@ -817,6 +932,7 @@ ulp_exit:
145 + at91_mckx_ps_restore
148 .macro at91_backup_mode
149 @@ -946,6 +1062,16 @@ ENDPROC(at91_pm_suspend_in_sram)
153 +#ifdef CONFIG_SOC_SAMA7
164 ENTRY(at91_pm_suspend_in_sram_sz)
165 .word .-at91_pm_suspend_in_sram