1 --- a/drivers/mtd/devices/Kconfig
2 +++ b/drivers/mtd/devices/Kconfig
3 @@ -120,6 +120,10 @@ config MTD_BCM47XXSFLASH
4 registered by bcma as platform devices. This enables driver for
8 + tristate "Atheros AR2315+ SPI Flash support"
9 + depends on SOC_AR2315
12 tristate "Uncached system RAM"
14 --- a/drivers/mtd/devices/Makefile
15 +++ b/drivers/mtd/devices/Makefile
16 @@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_MCHP23K256) += mchp23k2
17 obj-$(CONFIG_MTD_MCHP48L640) += mchp48l640.o
18 obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
19 obj-$(CONFIG_MTD_SST25L) += sst25l.o
20 +obj-$(CONFIG_MTD_AR2315) += ar2315.o
21 obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
22 obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
23 obj-$(CONFIG_MTD_POWERNV_FLASH) += powernv_flash.o
25 +++ b/drivers/mtd/devices/ar2315.c
29 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
31 + * Copyright (c) 2005-2006 Atheros Communications Inc.
32 + * Copyright (C) 2006-2007 FON Technology, SL.
33 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
35 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
37 + * This code is free software; you can redistribute it and/or modify
38 + * it under the terms of the GNU General Public License version 2 as
39 + * published by the Free Software Foundation.
43 +#include <linux/kernel.h>
44 +#include <linux/module.h>
45 +#include <linux/types.h>
46 +#include <linux/errno.h>
47 +#include <linux/slab.h>
48 +#include <linux/mtd/mtd.h>
49 +#include <linux/mtd/partitions.h>
50 +#include <linux/platform_device.h>
51 +#include <linux/sched.h>
52 +#include <linux/delay.h>
53 +#include <linux/io.h>
54 +#include <linux/mutex.h>
56 +#include "ar2315_spiflash.h"
58 +#define DRIVER_NAME "ar2315-spiflash"
60 +#define busy_wait(_priv, _condition, _wait) do { \
61 + while (_condition) { \
64 + else if ((_wait == 1) && need_resched()) \
80 +/* Flash configuration table */
87 +static const struct flashconfig flashconfig_tbl[] = {
88 + [FLASH_NONE] = { 0, 0, 0},
89 + [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
90 + STM_1MB_SECTOR_SIZE},
91 + [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
92 + STM_2MB_SECTOR_SIZE},
93 + [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
94 + STM_4MB_SECTOR_SIZE},
95 + [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
96 + STM_8MB_SECTOR_SIZE},
97 + [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
98 + STM_16MB_SECTOR_SIZE}
101 +/* Mapping of generic opcodes to STM serial flash opcodes */
122 +static const struct opcodes stm_opcodes[] = {
123 + [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
124 + [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
125 + [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
126 + [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
127 + [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
128 + [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
129 + [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
130 + [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
131 + [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
132 + [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
133 + [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
136 +/* Driver private data structure */
137 +struct spiflash_priv {
138 + struct mtd_info mtd;
139 + void __iomem *readaddr; /* memory mapped data for read */
140 + void __iomem *mmraddr; /* memory mapped register space */
141 + struct mutex lock; /* serialize registers access */
144 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
153 +/*****************************************************************************/
156 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
158 + return ioread32(priv->mmraddr + reg);
162 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
164 + iowrite32(data, priv->mmraddr + reg);
168 +spiflash_wait_busy(struct spiflash_priv *priv)
172 + busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
178 +spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
180 + const struct opcodes *op;
183 + op = &stm_opcodes[opcode];
184 + reg = spiflash_wait_busy(priv);
185 + spiflash_write_reg(priv, SPI_FLASH_OPCODE,
186 + ((u32)op->code) | (addr << 8));
188 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
189 + reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
191 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
192 + spiflash_wait_busy(priv);
197 + reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
199 + switch (op->rx_cnt) {
219 + * Probe SPI flash device
220 + * Function returns 0 for failure.
221 + * and flashconfig_tbl array index for success.
224 +spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)
226 + u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
230 + case STM_8MBIT_SIGNATURE:
231 + flash_size = FLASH_1MB;
233 + case STM_16MBIT_SIGNATURE:
234 + flash_size = FLASH_2MB;
236 + case STM_32MBIT_SIGNATURE:
237 + flash_size = FLASH_4MB;
239 + case STM_64MBIT_SIGNATURE:
240 + flash_size = FLASH_8MB;
242 + case STM_128MBIT_SIGNATURE:
243 + flash_size = FLASH_16MB;
246 + dev_warn(&pdev->dev, "read of flash device signature failed!\n");
254 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
256 + busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
257 + SPI_STATUS_WIP, timeout);
261 +spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
263 + struct spiflash_priv *priv = to_spiflash(mtd);
264 + const struct opcodes *op;
267 + if (instr->addr + instr->len > mtd->size)
270 + mutex_lock(&priv->lock);
272 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
273 + reg = spiflash_wait_busy(priv);
275 + op = &stm_opcodes[SPI_SECTOR_ERASE];
276 + temp = ((u32)instr->addr << 8) | (u32)(op->code);
277 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
279 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
280 + reg |= op->tx_cnt | SPI_CTL_START;
281 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
283 + spiflash_wait_complete(priv, 20);
285 + mutex_unlock(&priv->lock);
291 +spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
294 + struct spiflash_priv *priv = to_spiflash(mtd);
299 + if (from + len > mtd->size)
304 + mutex_lock(&priv->lock);
306 + memcpy_fromio(buf, priv->readaddr + from, len);
308 + mutex_unlock(&priv->lock);
314 +spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
317 + struct spiflash_priv *priv = to_spiflash(mtd);
318 + u32 opcode, bytes_left;
325 + if (to + len > mtd->size)
331 + u32 read_len, reg, page_offset, spi_data = 0;
333 + read_len = min(bytes_left, sizeof(u32));
335 + /* 32-bit writes cannot span across a page boundary
336 + * (256 bytes). This types of writes require two page
337 + * program operations to handle it correctly. The STM part
338 + * will write the overflow data to the beginning of the
339 + * current page as opposed to the subsequent page.
341 + page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
343 + if (page_offset > STM_PAGE_SIZE)
344 + read_len -= (page_offset - STM_PAGE_SIZE);
346 + mutex_lock(&priv->lock);
348 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
350 + switch (read_len) {
352 + spi_data |= buf[3] << 24;
355 + spi_data |= buf[2] << 16;
358 + spi_data |= buf[1] << 8;
361 + spi_data |= buf[0] & 0xff;
367 + spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
368 + opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
369 + (to & 0x00ffffff) << 8;
370 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
372 + reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
373 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
374 + reg |= (read_len + 4) | SPI_CTL_START;
375 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
377 + spiflash_wait_complete(priv, 1);
379 + mutex_unlock(&priv->lock);
381 + bytes_left -= read_len;
385 + *retlen += read_len;
386 + } while (bytes_left != 0);
391 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
392 +static const char * const part_probe_types[] = {
393 + "cmdlinepart", "RedBoot", "MyLoader", NULL
398 +spiflash_probe(struct platform_device *pdev)
400 + struct spiflash_priv *priv;
401 + struct mtd_info *mtd;
402 + struct resource *res;
406 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
410 + mutex_init(&priv->lock);
413 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
414 + priv->mmraddr = devm_ioremap_resource(&pdev->dev, res);
415 + if (IS_ERR(priv->mmraddr)) {
416 + dev_warn(&pdev->dev, "failed to map flash MMR\n");
417 + return PTR_ERR(priv->mmraddr);
420 + index = spiflash_probe_chip(pdev, priv);
422 + dev_warn(&pdev->dev, "found no flash device\n");
426 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
427 + priv->readaddr = devm_ioremap_resource(&pdev->dev, res);
428 + if (IS_ERR(priv->readaddr)) {
429 + dev_warn(&pdev->dev, "failed to map flash read mem\n");
430 + return PTR_ERR(priv->readaddr);
433 + platform_set_drvdata(pdev, priv);
434 + mtd->name = "spiflash";
435 + mtd->type = MTD_NORFLASH;
436 + mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
437 + mtd->size = flashconfig_tbl[index].byte_cnt;
438 + mtd->erasesize = flashconfig_tbl[index].sector_size;
439 + mtd->writesize = 1;
440 + mtd->numeraseregions = 0;
441 + mtd->eraseregions = NULL;
442 + mtd->_erase = spiflash_erase;
443 + mtd->_read = spiflash_read;
444 + mtd->_write = spiflash_write;
445 + mtd->owner = THIS_MODULE;
447 + dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
449 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
450 + /* parse redboot partitions */
452 + result = mtd_device_parse_register(mtd, part_probe_types,
460 +spiflash_remove(struct platform_device *pdev)
462 + struct spiflash_priv *priv = platform_get_drvdata(pdev);
464 + mtd_device_unregister(&priv->mtd);
469 +static struct platform_driver spiflash_driver = {
470 + .driver.name = DRIVER_NAME,
471 + .probe = spiflash_probe,
472 + .remove = spiflash_remove,
475 +module_platform_driver(spiflash_driver);
477 +MODULE_LICENSE("GPL");
478 +MODULE_AUTHOR("OpenWrt.org");
479 +MODULE_AUTHOR("Atheros Communications Inc");
480 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC");
481 +MODULE_ALIAS("platform:" DRIVER_NAME);
484 +++ b/drivers/mtd/devices/ar2315_spiflash.h
487 + * Atheros AR2315 SPI Flash Memory support header file.
489 + * Copyright (c) 2005, Atheros Communications Inc.
490 + * Copyright (C) 2006 FON Technology, SL.
491 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
492 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
494 + * This code is free software; you can redistribute it and/or modify
495 + * it under the terms of the GNU General Public License version 2 as
496 + * published by the Free Software Foundation.
499 +#ifndef __AR2315_SPIFLASH_H
500 +#define __AR2315_SPIFLASH_H
502 +#define STM_PAGE_SIZE 256
504 +#define SFI_WRITE_BUFFER_SIZE 4
505 +#define SFI_FLASH_ADDR_MASK 0x00ffffff
507 +#define STM_8MBIT_SIGNATURE 0x13
508 +#define STM_M25P80_BYTE_COUNT 1048576
509 +#define STM_M25P80_SECTOR_COUNT 16
510 +#define STM_M25P80_SECTOR_SIZE 0x10000
512 +#define STM_16MBIT_SIGNATURE 0x14
513 +#define STM_M25P16_BYTE_COUNT 2097152
514 +#define STM_M25P16_SECTOR_COUNT 32
515 +#define STM_M25P16_SECTOR_SIZE 0x10000
517 +#define STM_32MBIT_SIGNATURE 0x15
518 +#define STM_M25P32_BYTE_COUNT 4194304
519 +#define STM_M25P32_SECTOR_COUNT 64
520 +#define STM_M25P32_SECTOR_SIZE 0x10000
522 +#define STM_64MBIT_SIGNATURE 0x16
523 +#define STM_M25P64_BYTE_COUNT 8388608
524 +#define STM_M25P64_SECTOR_COUNT 128
525 +#define STM_M25P64_SECTOR_SIZE 0x10000
527 +#define STM_128MBIT_SIGNATURE 0x17
528 +#define STM_M25P128_BYTE_COUNT 16777216
529 +#define STM_M25P128_SECTOR_COUNT 256
530 +#define STM_M25P128_SECTOR_SIZE 0x10000
532 +#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
533 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
534 +#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
535 +#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
536 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
537 +#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
538 +#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
539 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
540 +#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
541 +#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
542 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
543 +#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
544 +#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
545 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
546 +#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
549 + * ST Microelectronics Opcodes for Serial Flash
552 +#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
553 +#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
554 +#define STM_OP_RD_STATUS 0x05 /* Read Status */
555 +#define STM_OP_WR_STATUS 0x01 /* Write Status */
556 +#define STM_OP_RD_DATA 0x03 /* Read Data */
557 +#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
558 +#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
559 +#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
560 +#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
561 +#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
562 +#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
564 +#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
565 +#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
566 +#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
567 +#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
568 +#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
569 +#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
572 + * SPI Flash Interface Registers
575 +#define SPI_FLASH_CTL 0x00
576 +#define SPI_FLASH_OPCODE 0x04
577 +#define SPI_FLASH_DATA 0x08
579 +#define SPI_CTL_START 0x00000100
580 +#define SPI_CTL_BUSY 0x00010000
581 +#define SPI_CTL_TXCNT_MASK 0x0000000f
582 +#define SPI_CTL_RXCNT_MASK 0x000000f0
583 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
584 +#define SPI_CTL_SIZE_MASK 0x00060000
586 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
587 +#define SPI_OPCODE_MASK 0x000000ff
589 +#define SPI_STATUS_WIP STM_STATUS_WIP
592 --- a/arch/mips/ath25/ar2315.c
593 +++ b/arch/mips/ath25/ar2315.c
594 @@ -218,6 +218,28 @@ static struct platform_device ar2315_gpi
595 .num_resources = ARRAY_SIZE(ar2315_gpio_res)
598 +static struct resource ar2315_spiflash_res[] = {
600 + .name = "spiflash_read",
601 + .flags = IORESOURCE_MEM,
602 + .start = AR2315_SPI_READ_BASE,
603 + .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
606 + .name = "spiflash_mmr",
607 + .flags = IORESOURCE_MEM,
608 + .start = AR2315_SPI_MMR_BASE,
609 + .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
613 +static struct platform_device ar2315_spiflash = {
615 + .name = "ar2315-spiflash",
616 + .resource = ar2315_spiflash_res,
617 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
620 void __init ar2315_init_devices(void)
622 /* Find board configuration */
623 @@ -228,6 +250,8 @@ void __init ar2315_init_devices(void)
624 ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
625 platform_device_register(&ar2315_gpio);
627 + platform_device_register(&ar2315_spiflash);
629 ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
630 ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
631 AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,