12ab7e503941d05a9ec65d1d54fe35556f82d30c
[openwrt/staging/jow.git] / target / linux / ath79 / dts / ar7100.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ath79.dtsi"
4
5 / {
6 compatible = "qca,ar7100";
7
8 chosen {
9 bootargs = "console=ttyS0,115200";
10 };
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@0 {
17 device_type = "cpu";
18 compatible = "mips,mips24Kc";
19 clocks = <&pll ATH79_CLK_CPU>;
20 reg = <0>;
21 };
22 };
23
24 ahb {
25 apb {
26 ddr_ctrl: memory-controller@18000000 {
27 compatible = "qca,ar7100-ddr-controller";
28 reg = <0x18000000 0x100>;
29
30 #qca,ddr-wb-channel-cells = <1>;
31 };
32
33 uart: uart@18020000 {
34 compatible = "ns16550a";
35 reg = <0x18020000 0x20>;
36 interrupts = <3>;
37
38 clocks = <&pll ATH79_CLK_AHB>;
39 clock-names = "uart";
40
41 reg-io-width = <4>;
42 reg-shift = <2>;
43 no-loopback-test;
44 };
45
46 usb_phy: usb-phy@18030000 {
47 compatible = "qca,ar7100-usb-phy";
48 reg = <0x18030000 0x10>;
49
50 reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
51 resets = <&rst 4>, <&rst 5>, <&rst 6>;
52
53 #phy-cells = <0>;
54
55 status = "disabled";
56 };
57
58 gpio: gpio@18040000 {
59 compatible = "qca,ar7100-gpio";
60 reg = <0x18040000 0x28>;
61 interrupts = <2>;
62
63 ngpios = <16>;
64
65 gpio-controller;
66 #gpio-cells = <2>;
67
68 interrupt-controller;
69 #interrupt-cells = <2>;
70 };
71
72 pll: pll-controller@18050000 {
73 compatible = "qca,ar7100-pll", "syscon";
74 reg = <0x18050000 0x20>;
75
76 clock-names = "ref";
77 /* The board must provides the ref clock */
78
79 #clock-cells = <1>;
80 clock-output-names = "cpu", "ddr", "ahb";
81 };
82
83 wdt: wdt@18060008 {
84 compatible = "qca,ar7130-wdt";
85 reg = <0x18060008 0x8>;
86
87 interrupts = <4>;
88
89 clocks = <&pll ATH79_CLK_AHB>;
90 clock-names = "wdt";
91 };
92
93 pci_intc: interrupt-controller@18060018 {
94 compatible = "qca,ar7100-misc-intc";
95 reg = <0x18060018 0x4>;
96 interrupt-parent = <&cpuintc>;
97 interrupts = <2>;
98 interrupt-controller;
99 #interrupt-cells = <1>;
100 };
101
102 rst: reset-controller@18060024 {
103 compatible = "qca,ar7100-reset";
104 reg = <0x18060024 0x4>;
105
106 #reset-cells = <1>;
107 };
108
109 pcie0: pcie-controller@17010000 {
110 compatible = "qca,ar7100-pci";
111 #address-cells = <3>;
112 #size-cells = <2>;
113 bus-range = <0x0 0x0>;
114 reg = <0x17010000 0x100>;
115 reg-names = "cfg_base";
116 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
117 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
118
119 device_type = "pci";
120
121 interrupt-parent = <&pci_intc>;
122 interrupts = <4>;
123
124 #interrupt-cells = <1>;
125
126 interrupt-map-mask = <0xf800 0 0 0>;
127 interrupt-map = <0x8800 0 0 0 &pci_intc 0
128 0x9000 0 0 0 &pci_intc 1
129 0x9800 0 0 0 &pci_intc 2>;
130
131 status = "disabled";
132 };
133 };
134 };
135
136 usb2: usb@1b000000 {
137 compatible = "generic-ehci";
138 reg = <0x1b000000 0x1000>;
139
140 interrupt-parent = <&cpuintc>;
141 interrupts = <3>;
142
143 phy-names = "usb-phy";
144 phys = <&usb_phy>;
145
146 has-synopsys-hc-bug;
147
148 status = "disabled";
149
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 usb1: usb@1c000000 {
155 compatible = "generic-ohci";
156 reg = <0x1c000000 0x1000>;
157
158 interrupt-parent = <&miscintc>;
159 interrupts = <6>;
160
161 phy-names = "usb-phy";
162 phys = <&usb_phy>;
163
164 status = "disabled";
165
166 #address-cells = <1>;
167 #size-cells = <0>;
168 };
169
170 spi: spi@1f000000 {
171 compatible = "qca,ar7100-spi";
172 reg = <0x1f000000 0x10>;
173
174 clocks = <&pll ATH79_CLK_AHB>;
175 clock-names = "ahb";
176
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 status = "disabled";
181 };
182 };
183
184 &cpuintc {
185 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
186 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
187 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
188 };
189
190 &miscintc {
191 compatible = "qca,ar7100-misc-intc";
192 };
193
194 &eth0 {
195 compatible = "qca,ar7100-eth", "syscon";
196 reg = <0x19000000 0x200
197 0x18070000 0x4>;
198
199 pll-data = <0x00110000 0x00001099 0x00991099>;
200 pll-reg = <0x4 0x10 17>;
201 pll-handle = <&pll>;
202 phy-mode = "rgmii";
203
204 resets = <&rst 9>;
205 reset-names = "mac";
206 qca,mac-idx = <0>;
207 };
208
209 &mdio1 {
210 builtin-switch;
211 };
212
213 &eth1 {
214 compatible = "qca,ar7100-eth", "syscon";
215 reg = <0x1a000000 0x200
216 0x18070004 0x4>;
217
218 pll-data = <0x00110000 0x00001099 0x00991099>;
219 pll-reg = <0x4 0x14 19>;
220 pll-handle = <&pll>;
221
222 phy-mode = "rgmii";
223
224 resets = <&rst 13>;
225 reset-names = "mac";
226 qca,mac-idx = <1>;
227 };