1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
9 compatible = "dlink,dir-825-b1", "qca,ar7161";
10 model = "D-Link DIR825B1";
13 led-boot = &led_power_orange;
14 led-failsafe = &led_power_orange;
15 led-running = &led_power_blue;
16 led-upgrade = &led_power_orange;
20 compatible = "gpio-leds";
24 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
25 trigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;
26 linux,default-trigger = "usbport";
29 led_power_orange: power_orange {
30 label = "orange:power";
31 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
35 led_power_blue: power_blue {
37 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
42 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
46 label = "orange:planet";
47 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
51 label = "blue:planet";
52 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
57 compatible = "gpio-leds";
60 label = "blue:wlan2g";
61 gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
62 linux,default-trigger = "phy0tpt";
66 label = "blue:wlan5g";
67 gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
68 linux,default-trigger = "phy1tpt";
73 compatible = "gpio-keys";
77 linux,code = <KEY_RESTART>;
78 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
83 linux,code = <KEY_WPS_BUTTON>;
84 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
89 compatible = "realtek,rtl8366s";
90 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
91 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
92 realtek,initvals = <0x06 0x0108>;
99 phy4: ethernet-phy@4 {
107 compatible = "mtd-concat";
108 devices = <&fwconcat0 &fwconcat1>;
111 compatible = "fixed-partitions";
112 #address-cells = <1>;
116 compatible = "denx,uimage";
125 #address-cells = <1>;
129 usb_ohci_port: port@1 {
131 #trigger-source-cells = <0>;
136 #address-cells = <1>;
140 usb_ehci_port: port@1 {
142 #trigger-source-cells = <0>;
154 compatible = "pci168c,0029";
155 reg = <0x8800 0 0 0 0>;
162 compatible = "pci168c,0029";
163 reg = <0x9000 0 0 0 0>;
174 compatible = "jedec,spi-nor";
176 spi-max-frequency = <25000000>;
179 compatible = "fixed-partitions";
180 #address-cells = <1>;
185 reg = <0x000000 0x040000>;
191 reg = <0x040000 0x010000>;
195 fwconcat0: partition@50000 {
197 reg = <0x050000 0x610000>;
202 reg = <0x660000 0x010000>;
206 fwconcat1: partition@670000 {
208 reg = <0x670000 0x190000>;
217 pll-data = <0x11110000 0x00001099 0x00991099>;
228 pll-data = <0x11110000 0x00001099 0x00991099>;
230 phy-handle = <&phy4>;