1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,ar7240";
12 bootargs = "console=ttyS0,115200";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
28 compatible = "fixed-clock";
30 clock-output-names = "ref";
31 clock-frequency = <40000000>;
36 ddr_ctrl: memory-controller@18000000 {
37 compatible = "qca,ar9132-ddr-controller",
38 "qca,ar7240-ddr-controller";
39 reg = <0x18000000 0x100>;
41 #qca,ddr-wb-channel-cells = <1>;
45 compatible = "ns16550a";
46 reg = <0x18020000 0x20>;
49 clocks = <&pll ATH79_CLK_AHB>;
58 compatible = "qca,ar7240-gpio",
60 reg = <0x18040000 0x28>;
69 #interrupt-cells = <2>;
72 pinmux: pinmux@18040028 {
73 compatible = "pinctrl-single";
75 reg = <0x18040028 0x8>;
77 pinctrl-single,bit-per-mux;
78 pinctrl-single,register-width = <32>;
79 pinctrl-single,function-mask = <0x1>;
82 jtag_disable_pins: pinmux_jtag_disable_pins {
83 pinctrl-single,bits = <0x0 0x1 0x1>;
86 switch_led_disable_pins: pinmux_switch_led_disable_pins {
87 pinctrl-single,bits = <0x0 0x0 0xf8>;
90 clks_disable_pins: pinmux_clks_disable_pins {
91 pinctrl-single,bits = <0x0 0x0 0x81f00>;
95 pll: pll-controller@18050000 {
96 compatible = "qca,ar7240-pll", "syscon";
97 reg = <0x18050000 0x3c>;
103 clock-output-names = "cpu", "ddr", "ahb";
107 compatible = "qca,ar7130-wdt";
108 reg = <0x18060008 0x8>;
112 clocks = <&pll ATH79_CLK_AHB>;
116 rst: reset-controller@1806001c {
117 compatible = "qca,ar7240-reset",
119 reg = <0x1806001c 0x4>;
124 pcie: pcie-controller@180c0000 {
125 compatible = "qcom,ar7240-pci";
126 #address-cells = <3>;
128 bus-range = <0x0 0x0>;
129 reg = <0x180c0000 0x1000>, /* CRP */
130 <0x180f0000 0x100>, /* CTRL */
131 <0x14000000 0x1000>; /* CFG */
132 reg-names = "crp_base", "ctrl_base", "cfg_base";
133 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
134 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
135 interrupt-parent = <&cpuintc>;
138 resets = <&rst 6>, <&rst 7>;
139 reset-names = "hc", "phy";
143 interrupt-controller;
144 #interrupt-cells = <1>;
146 interrupt-map-mask = <0 0 0 1>;
147 interrupt-map = <0 0 0 0 &pcie 0>;
153 compatible = "qca,ar7240-spi",
155 reg = <0x1f000000 0x10>;
157 clocks = <&pll ATH79_CLK_AHB>;
162 #address-cells = <1>;
169 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
170 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
171 <&ddr_ctrl 0>, <&ddr_ctrl 1>;