1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
10 compatible = "enterasys,ws-ap3705i", "qca,ar9344";
11 model = "Enterasys WS-AP3705i";
14 bootargs = "console=ttyS0,115200n8";
18 led-boot = &led_power_green;
19 led-failsafe = &led_power_red;
20 led-running = &led_power_green;
21 led-upgrade = &led_power_red;
22 label-mac-device = ð0;
26 compatible = "mtd-concat";
27 devices = <&fwconcat0 &fwconcat1>;
30 compatible = "fixed-partitions";
35 compatible = "denx,uimage";
37 reg = <0x0 0x1dd0000>;
43 compatible = "gpio-leds";
45 pinctrl-names = "default";
46 pinctrl-0 = <&enable_gpio_11 &enable_gpio_16>;
48 led_power_green: power_green {
49 function = LED_FUNCTION_POWER;
50 color = <LED_COLOR_ID_GREEN>;
51 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
54 led_power_red: power_red {
55 function = LED_FUNCTION_POWER;
56 color = <LED_COLOR_ID_RED>;
57 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
61 function = LED_FUNCTION_LAN;
62 color = <LED_COLOR_ID_BLUE>;
63 gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
67 function = LED_FUNCTION_LAN;
68 color = <LED_COLOR_ID_GREEN>;
69 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
73 label = "green:radio2";
74 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
75 linux,default-trigger = "phy0tpt";
80 compatible = "gpio-leds";
83 label = "green:radio1";
84 gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
85 linux,default-trigger = "phy1tpt";
90 compatible = "gpio-keys";
93 label = "Reset button";
94 linux,code = <KEY_RESTART>;
95 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
101 clock-frequency = <40000000>;
105 enable_gpio_16: pinmux_enable_gpio_16 {
106 pinctrl-single,bits = <0x10 0x0 0x000000ff>;
109 enable_gpio_11: pinmux_enable_gpio_11 {
110 pinctrl-single,bits = <0x8 0x0 0xff000000>;
123 compatible = "jedec,spi-nor";
125 spi-max-frequency = <25000000>;
128 compatible = "fixed-partitions";
129 #address-cells = <1>;
133 label = "u-boot-bak";
139 label = "u-boot-env0";
140 reg = <0x80000 0x10000>;
145 label = "u-boot-env1";
146 reg = <0x90000 0x10000>;
152 reg = <0xa0000 0x80000>;
158 reg = <0x120000 0x10000>;
164 reg = <0x130000 0x100000>;
168 fwconcat0: partition@230000 {
170 reg = <0x230000 0xdd0000>;
176 compatible = "jedec,spi-nor";
178 spi-max-frequency = <25000000>;
181 compatible = "fixed-partitions";
182 #address-cells = <1>;
185 fwconcat1: partition@0 {
187 reg = <0x0 0x1000000>;
197 compatible = "pci168c,0033";
198 reg = <0x0000 0 0 0 0>;
208 phy0: ethernet-phy@0 {
216 pll-data = <0x1e000000 0x08000101 0x08001313>;
219 phy-handle = <&phy0>;