1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,ar9340";
12 bootargs = "console=ttyS0,115200";
21 compatible = "mips,mips74Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
34 compatible = "fixed-clock";
35 clock-output-names = "ref";
40 compatible = "simple-bus";
47 compatible = "simple-bus";
53 ddr_ctrl: memory-controller@18000000 {
54 compatible = "qca,ar9340-ddr-controller",
55 "qca,ar7240-ddr-controller";
56 reg = <0x18000000 0x12c>;
58 #qca,ddr-wb-channel-cells = <1>;
62 compatible = "ns16550a";
63 reg = <0x18020000 0x2c>;
67 clocks = <&pll ATH79_CLK_REF>;
78 compatible = "qca,ar9340-gpio";
79 reg = <0x18040000 0x2c>;
88 #interrupt-cells = <2>;
91 pinmux: pinmux@1804002c {
92 compatible = "pinctrl-single";
94 reg = <0x1804002c 0x44>;
98 pinctrl-single,bit-per-mux;
99 pinctrl-single,register-width = <32>;
100 pinctrl-single,function-mask = <0x1>;
101 #pinctrl-cells = <2>;
103 jtag_disable_pins: pinmux_jtag_disable_pins {
104 pinctrl-single,bits = <0x40 0x2 0x2>;
108 pll: pll-controller@18050000 {
109 compatible = "qca,ar9340-pll", "syscon";
110 reg = <0x18050000 0x4c>;
115 clock-output-names = "cpu", "ddr", "ahb";
119 compatible = "qca,ar9340-wdt", "qca,ar7130-wdt";
120 reg = <0x18060008 0x8>;
124 clocks = <&pll ATH79_CLK_AHB>;
128 rst: reset-controller@1806001c {
129 compatible = "qca,ar9340-reset", "qca,ar7100-reset";
130 reg = <0x1806001c 0x4>;
135 hs_uart: uart@18500000 {
136 compatible = "qca,ar9330-uart";
137 reg = <0x18500000 0x14>;
140 interrupt-parent = <&miscintc>;
142 clocks = <&pll ATH79_CLK_UART1>;
143 clock-names = "uart";
149 gmac: gmac@18070000 {
150 compatible = "qca,ar9340-gmac";
151 reg = <0x18070000 0x14>;
154 wmac: wmac@18100000 {
155 compatible = "qca,ar9340-wmac";
156 reg = <0x18100000 0x20000>;
162 compatible = "generic-ehci";
163 reg = <0x1b000000 0x1d8>;
167 reset-names = "usb-host";
169 has-transaction-translator;
170 caps-offset = <0x100>;
172 phy-names = "usb-phy";
178 nand: nand@1b000200 {
179 compatible = "qca,ar934x-nand";
180 reg = <0x1b000200 0xb8>;
183 interrupt-parent = <&miscintc>;
186 reset-names = "nand";
188 nand-ecc-mode = "hw";
190 #address-cells = <1>;
197 compatible = "qca,ar934x-spi";
198 reg = <0x1f000000 0x1c>;
200 clocks = <&pll ATH79_CLK_AHB>;
202 #address-cells = <1>;
210 compatible = "qca,ar9340-usb-phy", "qca,ar7200-usb-phy";
212 reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
213 resets = <&rst 11>, <&rst 4>, <&rst 3>;
222 compatible = "qca,ar9340-mdio";
226 compatible = "qca,ar9340-eth", "syscon";
228 pll-data = <0x16000000 0x00000101 0x00001616>;
229 pll-reg = <0x4 0x2c 17>;
231 resets = <&rst 9>, <&rst 22>;
232 reset-names = "mac", "mdio";
233 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
234 clock-names = "eth", "mdio";
240 compatible = "qca,ar9340-mdio";
242 reset-names = "mdio";
245 builtin_switch: switch0@1f {
246 compatible = "qca,ar8229";
250 reset-names = "switch";
252 qca,mib-poll-interval = <500>;
256 #address-cells = <1>;
259 swphy0: ethernet-phy@0 {
264 swphy4: ethernet-phy@4 {
273 compatible = "qca,ar9340-eth", "syscon";
277 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
278 clock-names = "eth", "mdio";