ath79: mdio: add address-cells and size-cells defaults
[openwrt/staging/wigyori.git] / target / linux / ath79 / dts / ath79.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 / {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpuintc: interrupt-controller {
7 compatible = "qca,ar7100-cpu-intc";
8
9 interrupt-controller;
10 #interrupt-cells = <1>;
11 };
12
13 ahb {
14 compatible = "simple-bus";
15 ranges;
16
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 interrupt-parent = <&cpuintc>;
21
22 apb {
23 compatible = "simple-bus";
24 ranges;
25
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 interrupt-parent = <&miscintc>;
30
31 miscintc: interrupt-controller@18060010 {
32 compatible = "qca,ar7240-misc-intc";
33 reg = <0x18060010 0x4>;
34
35 interrupt-parent = <&cpuintc>;
36 interrupts = <6>;
37
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 };
41 };
42
43 eth0: eth@19000000 {
44 status = "disabled";
45
46 compatible = "qca,ath79-eth", "syscon";
47 reg = <0x19000000 0x200>;
48
49 interrupts = <4>;
50 phy-mode = "mii";
51
52 mdio0: mdio-bus {
53 status = "disabled";
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 regmap = <&eth0>;
58
59 clocks = <&pll ATH79_CLK_MDIO>;
60 clock-names = "ref";
61 };
62 };
63
64 eth1: eth@1a000000 {
65 status = "disabled";
66
67 compatible = "qca,ath79-eth", "syscon";
68 reg = <0x1a000000 0x200>;
69
70 interrupts = <5>;
71 phy-mode = "mii";
72
73 mdio1: mdio-bus {
74 status = "disabled";
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 regmap = <&eth1>;
79
80 clocks = <&pll ATH79_CLK_MDIO>;
81 clock-names = "ref";
82 };
83 };
84 };
85 };