1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
6 compatible = "qca,qca9557";
17 compatible = "mips,mips74Kc";
18 clocks = <&pll ATH79_CLK_CPU>;
24 compatible = "fixed-clock";
26 clock-output-names = "ref";
27 clock-frequency = <40000000>;
32 ddr_ctrl: memory-controller@18000000 {
33 compatible = "qca,ar9557-ddr-controller",
34 "qca,ar7240-ddr-controller";
35 reg = <0x18000000 0x100>;
37 #qca,ddr-wb-channel-cells = <1>;
41 compatible = "ns16550a";
42 reg = <0x18020000 0x20>;
46 clocks = <&pll ATH79_CLK_REF>;
56 usb_phy0: usb-phy@18030000 {
57 compatible ="qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
59 reset-names = "usb-phy", "usb-suspend-override";
60 resets = <&rst 4>, <&rst 3>;
68 compatible = "qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
70 reset-names = "usb-phy", "usb-suspend-override";
71 resets = <&rst2 4>, <&rst2 3>;
79 compatible = "qca,ar9557-gpio",
81 reg = <0x18040000 0x28>;
90 #interrupt-cells = <2>;
93 pinmux: pinmux@1804002c {
94 compatible = "pinctrl-single";
96 reg = <0x1804002c 0x40>;
100 pinctrl-single,bit-per-mux;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0x1>;
103 #pinctrl-cells = <2>;
105 jtag_disable_pins: pinmux_jtag_disable_pins {
106 pinctrl-single,bits = <0x40 0x2 0x2>;
110 pll: pll-controller@18050000 {
111 compatible = "qca,ar9557-pll",
113 reg = <0x18050000 0x50>;
116 clock-output-names = "cpu", "ddr", "ahb";
122 compatible = "qca,ar7130-wdt";
123 reg = <0x18060008 0x8>;
127 clocks = <&pll ATH79_CLK_AHB>;
131 rst: reset-controller@1806001c {
132 compatible = "qca,qca9550-reset",
135 reg = <0x1806001c 0x4>;
138 interrupt-parent = <&cpuintc>;
140 intc3: interrupt-controller@3 {
141 compatible = "qcom,qca9556-intc";
145 interrupt-controller;
146 #interrupt-cells = <1>;
148 qcom,pending-bits = <0x1f000>, /* pcie rc */
149 <0x1000000>, /* usb1 */
150 <0x10000000>; /* usb2 */
154 rst2: reset-controller@180600c0 {
155 compatible = "qca,qca9550-reset",
158 reg = <0x180600c0 0x4>;
163 pcie: pcie-controller@18250000 {
164 compatible = "qcom,ar7240-pci";
165 #address-cells = <3>;
167 bus-range = <0x0 0x0>;
168 reg = <0x18250000 0x1000>, /* CRP */
169 <0x18280000 0x100>, /* CTRL */
170 <0x16000000 0x1000>; /* CFG */
171 reg-names = "crp_base", "ctrl_base", "cfg_base";
172 ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
173 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
174 interrupt-parent = <&intc3>;
177 interrupt-controller;
178 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 1>;
181 interrupt-map = <0 0 0 0 &pcie 0>;
185 wmac: wmac@18100000 {
186 compatible = "qca,qca9550-wmac";
187 reg = <0x18100000 0x10000>;
189 interrupt-parent = <&cpuintc>;
197 compatible = "generic-ehci";
198 reg = <0x1b000000 0x1fc>;
200 interrupt-parent = <&intc3>;
203 reset-names = "usb-host";
205 has-transaction-translator;
206 caps-offset = <0x100>;
208 phy-names = "usb-phy0";
215 compatible = "generic-ehci";
216 reg = <0x1b400000 0x1fc>;
218 interrupt-parent = <&intc3>;
221 reset-names = "usb-host";
223 has-transaction-translator;
224 caps-offset = <0x100>;
226 phy-names = "usb-phy1";
233 compatible = "qca,ar9557-spi", "qca,ar7100-spi";
234 reg = <0x1f000000 0x10>;
236 clocks = <&pll ATH79_CLK_AHB>;
241 #address-cells = <1>;
249 reset-names = "mdio";
253 compatible = "qca,qca9550-eth", "syscon";
255 pll-data = <0x82000101 0x80000101 0x80001313>;
264 reset-names = "mdio";
268 compatible = "qca,qca9550-eth", "syscon";
270 pll-data = <0x82000101 0x80000101 0x80001313>;