ath79: enable UART in SoC DTSI files
[openwrt/staging/jow.git] / target / linux / ath79 / dts / qca9557_engenius_eap1200h.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
8
9 / {
10 compatible = "engenius,eap1200h", "qca,qca9557";
11 model = "EnGenius EAP1200H";
12
13 aliases {
14 label-mac-device = &eth0;
15 led-boot = &led_power;
16 led-failsafe = &led_power;
17 led-running = &led_power;
18 led-upgrade = &led_power;
19 };
20
21 keys {
22 compatible = "gpio-keys";
23
24 reset {
25 label = "reset";
26 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
27 debounce-interval = <60>;
28 linux,code = <KEY_RESTART>;
29 };
30 };
31
32 leds {
33 compatible = "gpio-leds";
34
35 led_power: power {
36 label = "amber:power";
37 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
38 default-state = "on";
39 };
40
41 wifi2g {
42 label = "blue:wifi2g";
43 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
44 linux,default-trigger = "phy1tpt";
45 };
46
47 wifi5g {
48 label = "green:wifi5g";
49 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
50 linux,default-trigger = "phy0tpt";
51 };
52
53 wps {
54 label = "blue:wps";
55 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
56 };
57 };
58
59 virtual_flash {
60 compatible = "mtd-concat";
61
62 devices = <&fwconcat0 &fwconcat1>;
63
64 partitions {
65 compatible = "fixed-partitions";
66 #address-cells = <1>;
67 #size-cells = <1>;
68
69 partition@0 {
70 compatible = "openwrt,uimage", "denx,uimage";
71 openwrt,ih-magic = <IH_MAGIC_OKLI>;
72 label = "firmware";
73 reg = <0x0 0x0>;
74 };
75 };
76 };
77 };
78
79 &spi {
80 status = "okay";
81
82 flash@0 {
83 compatible = "jedec,spi-nor";
84 reg = <0>;
85 spi-max-frequency = <40000000>;
86
87 partitions {
88 compatible = "fixed-partitions";
89 #address-cells = <1>;
90 #size-cells = <1>;
91
92 partition@0 {
93 label = "u-boot";
94 reg = <0x000000 0x040000>;
95 read-only;
96 };
97
98 partition@40000 {
99 label = "u-boot-env";
100 reg = <0x040000 0x010000>;
101 };
102
103 partition@50000 {
104 label = "custom";
105 reg = <0x050000 0x050000>;
106 read-only;
107 };
108
109 partition@a0000 {
110 label = "loader";
111 reg = <0x0a0000 0x010000>;
112 read-only;
113 };
114
115 fwconcat1: partition@b0000 {
116 label = "fwconcat1";
117 reg = <0x0b0000 0x170000>;
118 };
119
120 partition@220000 {
121 label = "fakeroot";
122 reg = <0x220000 0x010000>;
123 read-only;
124 };
125
126 fwconcat0: partition@230000 {
127 label = "fwconcat0";
128 reg = <0x230000 0xb40000>;
129 };
130
131 partition@d70000 {
132 label = "failsafe";
133 reg = <0xd70000 0x280000>;
134 read-only;
135 };
136
137 art: partition@ff0000 {
138 label = "art";
139 reg = <0xff0000 0x010000>;
140 read-only;
141 };
142 };
143 };
144 };
145
146 &mdio0 {
147 status = "okay";
148
149 phy5: ethernet-phy@5 {
150 reg = <5>;
151 eee-broken-100tx;
152 eee-broken-1000t;
153 };
154 };
155
156 &eth0 {
157 status = "okay";
158
159 mtd-mac-address = <&art 0x0>;
160
161 phy-handle = <&phy5>;
162 phy-mode = "rgmii-id";
163
164 pll-data = <0x82000000 0x80000101 0x80001313>;
165 };
166
167 &pcie0 {
168 status = "okay";
169
170 wifi@0,0,0 {
171 compatible = "qcom,ath10k";
172 reg = <0x0 0 0 0 0>;
173 qca,no-eeprom;
174 };
175 };
176
177 &wmac {
178 status = "okay";
179
180 mtd-cal-data = <&art 0x1000>;
181 mtd-mac-address = <&art 0x0>;
182 mtd-mac-address-increment = <1>;
183 };