1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,qca9560";
12 bootargs = "console=ttyS0,115200n8";
21 compatible = "mips,mips74Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
28 compatible = "fixed-clock";
30 clock-output-names = "ref";
31 clock-frequency = <25000000>;
36 ddr_ctrl: memory-controller@18000000 {
37 compatible = "qca,qca9560-ddr-controller",
38 "qca,ar7240-ddr-controller";
39 reg = <0x18000000 0x100>;
41 #qca,ddr-wb-channel-cells = <1>;
45 compatible = "ns16550a";
46 reg = <0x18020000 0x20>;
50 clocks = <&pll ATH79_CLK_REF>;
59 compatible = "qca,qca9560-gpio",
61 reg = <0x18040000 0x28>;
70 #interrupt-cells = <2>;
73 pinmux: pinmux@1804002c {
74 compatible = "pinctrl-single";
76 reg = <0x1804002c 0x44>;
80 pinctrl-single,bit-per-mux;
81 pinctrl-single,register-width = <32>;
82 pinctrl-single,function-mask = <0x1>;
85 jtag_disable_pins: pinmux_jtag_disable_pins {
86 pinctrl-single,bits = <0x40 0x2 0x2>;
90 pll: pll-controller@18050000 {
91 compatible = "qca,qca9560-pll", "syscon";
92 reg = <0x18050000 0x50>;
95 clock-output-names = "cpu", "ddr", "ahb";
102 compatible = "qca,ar7130-wdt";
103 reg = <0x18060008 0x8>;
107 clocks = <&pll ATH79_CLK_AHB>;
111 rst: reset-controller@1806001c {
112 compatible = "qca,qca9560-reset",
114 reg = <0x1806001c 0x4>;
117 interrupt-parent = <&cpuintc>;
119 intc3: interrupt-controller {
120 compatible = "qca,ar9340-intc";
122 interrupt-parent = <&cpuintc>;
125 interrupt-controller;
126 #interrupt-cells = <1>;
128 qca,int-status-addr = <0xac>;
129 qca,pending-bits = <0x1f000>, /* pcie rc */
130 <0x1000000>, /* usb1 */
131 <0x10000000>; /* usb2 */
135 rst2: reset-controller@180600c0 {
136 compatible = "qca,qca9560-reset",
139 reg = <0x180600c0 0x4>;
145 gmac: gmac@18070000 {
146 compatible = "qca,qca9560-gmac";
147 reg = <0x18070000 0x64>;
150 wmac: wmac@18100000 {
151 compatible = "qca,qca9560-wmac";
152 reg = <0x18100000 0x10000>;
154 interrupt-parent = <&cpuintc>;
160 pcie: pcie-controller@18250000 {
161 compatible = "qcom,ar7240-pci";
162 #address-cells = <3>;
164 bus-range = <0x0 0x0>;
165 reg = <0x18250000 0x1000>, /* CRP */
166 <0x18280000 0x100>, /* CTRL */
167 <0x16000000 0x1000>; /* CFG */
168 reg-names = "crp_base", "ctrl_base", "cfg_base";
169 ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
170 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
171 interrupt-parent = <&intc3>;
176 resets = <&rst 6>, <&rst 7>;
177 reset-names = "hc", "phy";
179 interrupt-controller;
180 #interrupt-cells = <1>;
182 interrupt-map-mask = <0 0 0 1>;
183 interrupt-map = <0 0 0 0 &pcie 0>;
188 compatible = "generic-ehci";
189 reg = <0x1b000000 0x1d8>;
191 interrupt-parent = <&intc3>;
195 reset-names = "usb-host";
197 has-transaction-translator;
198 caps-offset = <0x100>;
200 phy-names = "usb-phy0";
205 #address-cells = <1>;
210 #trigger-source-cells = <0>;
215 compatible = "generic-ehci";
216 reg = <0x1b400000 0x1d8>;
218 interrupt-parent = <&intc3>;
222 reset-names = "usb-host";
224 has-transaction-translator;
225 caps-offset = <0x100>;
227 phy-names = "usb-phy1";
232 #address-cells = <1>;
237 #trigger-source-cells = <0>;
242 compatible = "qca,ar934x-spi";
243 reg = <0x1f000000 0x1c>;
245 clocks = <&pll ATH79_CLK_AHB>;
249 #address-cells = <1>;
255 compatible = "qca,qca9560-usb-phy", "qca,ar7200-usb-phy";
257 reset-names = "usb-phy", "usb-suspend-override";
258 resets = <&rst 4>, <&rst 3>;
266 compatible = "qca,qca9560-usb-phy", "qca,ar7200-usb-phy";
268 reset-names = "usb-phy", "usb-suspend-override";
269 resets = <&rst2 4>, <&rst2 3>;
279 reset-names = "mdio";
283 compatible = "qca,qca9560-eth", "syscon";
285 pll-data = <0x03000000 0x00000101 0x00001919>;
286 pll-reg = <0 0x48 0>;
296 reset-names = "mdio";
299 builtin_switch: switch0@1f {
300 compatible = "qca,ar8229";
303 reset-names = "switch";
306 qca,mib-poll-interval = <500>;
309 #address-cells = <1>;
312 swphy0: ethernet-phy@0 {
317 swphy4: ethernet-phy@4 {
326 compatible = "qca,qca9560-eth", "syscon";