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ath79: ar934x: fix mounting issues if subpage is not supported
[openwrt/staging/chunkeey.git] / target / linux / ath79 / files / drivers / mtd / nand / raw / ar934x_nand.c
1 /*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/version.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/reset.h>
25
26 #define AR934X_NFC_DRIVER_NAME "ar934x-nand"
27
28 #define AR934X_NFC_REG_CMD 0x00
29 #define AR934X_NFC_REG_CTRL 0x04
30 #define AR934X_NFC_REG_STATUS 0x08
31 #define AR934X_NFC_REG_INT_MASK 0x0c
32 #define AR934X_NFC_REG_INT_STATUS 0x10
33 #define AR934X_NFC_REG_ECC_CTRL 0x14
34 #define AR934X_NFC_REG_ECC_OFFSET 0x18
35 #define AR934X_NFC_REG_ADDR0_0 0x1c
36 #define AR934X_NFC_REG_ADDR0_1 0x24
37 #define AR934X_NFC_REG_ADDR1_0 0x20
38 #define AR934X_NFC_REG_ADDR1_1 0x28
39 #define AR934X_NFC_REG_SPARE_SIZE 0x30
40 #define AR934X_NFC_REG_PROTECT 0x38
41 #define AR934X_NFC_REG_LOOKUP_EN 0x40
42 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
43 #define AR934X_NFC_REG_DMA_ADDR 0x64
44 #define AR934X_NFC_REG_DMA_COUNT 0x68
45 #define AR934X_NFC_REG_DMA_CTRL 0x6c
46 #define AR934X_NFC_REG_MEM_CTRL 0x80
47 #define AR934X_NFC_REG_DATA_SIZE 0x84
48 #define AR934X_NFC_REG_READ_STATUS 0x88
49 #define AR934X_NFC_REG_TIME_SEQ 0x8c
50 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
51 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
52 #define AR934X_NFC_REG_FIFO_DATA 0x98
53 #define AR934X_NFC_REG_TIME_MODE 0x9c
54 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
55 #define AR934X_NFC_REG_FIFO_INIT 0xb0
56 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
57
58 #define AR934X_NFC_CMD_CMD_SEQ_S 0
59 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
60 #define AR934X_NFC_CMD_SEQ_1C 0x00
61 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
62 #define AR934X_NFC_CMD_SEQ_12 0x0c
63 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
64 #define AR934X_NFC_CMD_SEQ_S 0x24
65 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
66 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
67 #define AR934X_NFC_CMD_SEQ_18 0x32
68 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
69 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
70 #define AR934X_NFC_CMD_ADDR_SEL_0 0
71 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
72 #define AR934X_NFC_CMD_CMD0_S 8
73 #define AR934X_NFC_CMD_CMD0_M 0xff
74 #define AR934X_NFC_CMD_CMD1_S 16
75 #define AR934X_NFC_CMD_CMD1_M 0xff
76 #define AR934X_NFC_CMD_CMD2_S 24
77 #define AR934X_NFC_CMD_CMD2_M 0xff
78
79 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
80 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
81 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
82 #define AR934X_NFC_CTRL_INT_EN BIT(4)
83 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
86 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
87 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
88 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
89 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
90 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
91 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
92 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
93 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
94 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
95 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
96 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
97 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
98 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
99 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
100 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
101 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
102 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
103 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
104 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
105 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
106 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
107 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
108 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
109 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
110 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
111
112 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
113 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
114 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
115 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
119 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
120 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
121 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
122 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
123 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
124 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
125
126 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
127 #define AR934X_NFC_INT_CMD_END BIT(1)
128
129 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
130 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
131 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
132 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
133 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
137 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
138 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
139 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
140 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
141 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
142 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
143 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
144
145 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
146
147 /* default timing values */
148 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
149 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
150 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
151
152 #define AR934X_NFC_ID_BUF_SIZE 8
153 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
154 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
155 #define AR934X_NFC_DONE_TIMEOUT 1000
156 #define AR934X_NFC_DMA_RETRIES 20
157
158 #define AR934X_NFC_USE_IRQ true
159 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
160
161 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
162
163 #undef AR934X_NFC_DEBUG_DATA
164 #undef AR934X_NFC_DEBUG
165
166 struct mtd_info;
167 struct mtd_partition;
168 struct ar934x_nfc;
169
170 struct ar934x_nfc {
171 struct nand_chip nand_chip;
172 struct device *parent;
173 void __iomem *base;
174 bool swap_dma;
175 int irq;
176 wait_queue_head_t irq_waitq;
177
178 bool spurious_irq_expected;
179 u32 irq_status;
180
181 u32 ctrl_reg;
182 u32 ecc_ctrl_reg;
183 u32 ecc_offset_reg;
184 u32 ecc_thres;
185 u32 ecc_oob_pos;
186
187 bool small_page;
188 unsigned int addr_count0;
189 unsigned int addr_count1;
190
191 u8 *buf;
192 dma_addr_t buf_dma;
193 unsigned int buf_size;
194 int buf_index;
195
196 bool read_id;
197
198 int erase1_page_addr;
199
200 int rndout_page_addr;
201 int rndout_read_cmd;
202
203 int seqin_page_addr;
204 int seqin_column;
205 int seqin_read_cmd;
206
207 struct reset_control *rst;
208 };
209
210 static inline __printf(2, 3)
211 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
212 {
213 }
214
215 #ifdef AR934X_NFC_DEBUG
216 #define nfc_dbg(_nfc, fmt, ...) \
217 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
218 #else
219 #define nfc_dbg(_nfc, fmt, ...) \
220 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
221 #endif /* AR934X_NFC_DEBUG */
222
223 #ifdef AR934X_NFC_DEBUG_DATA
224 static void nfc_debug_data(const char *label, void *data, int len)
225 {
226 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
227 data, len, 0);
228 }
229 #else
230 static inline void nfc_debug_data(const char *label, void *data, int len) {}
231 #endif /* AR934X_NFC_DEBUG_DATA */
232
233 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
234
235 static inline bool is_all_ff(u8 *buf, int len)
236 {
237 while (len--)
238 if (buf[len] != 0xff)
239 return false;
240
241 return true;
242 }
243
244 static inline void ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
245 {
246 __raw_writel(val, nfc->base + reg);
247 }
248
249 static inline u32 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
250 {
251 return __raw_readl(nfc->base + reg);
252 }
253
254 static inline struct ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
255 {
256 struct nand_chip *chip = mtd_to_nand(mtd);
257
258 return container_of(chip, struct ar934x_nfc, nand_chip);
259 }
260
261 static struct mtd_info *ar934x_nfc_to_mtd(struct ar934x_nfc *nfc)
262 {
263 return nand_to_mtd(&nfc->nand_chip);
264 }
265
266 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
267 {
268 return AR934X_NFC_USE_IRQ;
269 }
270
271 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
272 {
273 wmb();
274
275 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
276 /* flush write */
277 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
278 }
279
280 static bool __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
281 {
282 u32 status;
283
284 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
285 return (status & 0xff) == 0xff;
286 }
287
288 static inline bool __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
289 {
290 u32 status;
291
292 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
293 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
294 }
295
296 static int ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
297 {
298 unsigned long timeout;
299
300 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
301 do {
302 if (__ar934x_nfc_dev_ready(nfc))
303 return 0;
304 } while time_before(jiffies, timeout);
305
306 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
307 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
308 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
309 return -ETIMEDOUT;
310 }
311
312 static int ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
313 {
314 unsigned long timeout;
315
316 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
317 do {
318 if (__ar934x_nfc_is_dma_ready(nfc))
319 return 0;
320 } while time_before(jiffies, timeout);
321
322 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
323 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
324 return -ETIMEDOUT;
325 }
326
327 static int ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
328 {
329 long timeout;
330 int ret;
331
332 timeout = wait_event_timeout(nfc->irq_waitq,
333 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
334 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
335
336 ret = 0;
337 if (!timeout) {
338 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
339 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
340 /* flush write */
341 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
342
343 nfc_dbg(nfc,
344 "timeout waiting for interrupt, status:%08x\n",
345 nfc->irq_status);
346 ret = -ETIMEDOUT;
347 }
348
349 nfc->irq_status = 0;
350 return ret;
351 }
352
353 static int ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
354 {
355 int ret;
356
357 if (ar934x_nfc_use_irq(nfc))
358 ret = ar934x_nfc_wait_irq(nfc);
359 else
360 ret = ar934x_nfc_wait_dev_ready(nfc);
361
362 if (ret)
363 return ret;
364
365 return ar934x_nfc_wait_dma_ready(nfc);
366 }
367
368 static int ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
369 {
370 nfc->buf = dma_alloc_coherent(nfc->parent, size,
371 &nfc->buf_dma, GFP_KERNEL);
372 if (nfc->buf == NULL) {
373 dev_err(nfc->parent, "no memory for DMA buffer\n");
374 return -ENOMEM;
375 }
376
377 nfc->buf_size = size;
378 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
379
380 return 0;
381 }
382
383 static void ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
384 {
385 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
386 }
387
388 static void ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column,
389 int page_addr, u32 *addr0, u32 *addr1)
390 {
391 u32 a0, a1;
392
393 a0 = 0;
394 a1 = 0;
395
396 if (column == -1) {
397 /* ERASE1 */
398 a0 = (page_addr & 0xffff) << 16;
399 a1 = (page_addr >> 16) & 0xf;
400 } else if (page_addr != -1) {
401 /* SEQIN, READ0, etc.. */
402
403 /* TODO: handle 16bit bus width */
404 if (nfc->small_page) {
405 a0 = column & 0xff;
406 a0 |= (page_addr & 0xff) << 8;
407 a0 |= ((page_addr >> 8) & 0xff) << 16;
408 a0 |= ((page_addr >> 16) & 0xff) << 24;
409 } else {
410 a0 = column & 0x0FFF;
411 a0 |= (page_addr & 0xffff) << 16;
412
413 if (nfc->addr_count0 > 4)
414 a1 = (page_addr >> 16) & 0xf;
415 }
416 }
417
418 *addr0 = a0;
419 *addr1 = a1;
420 }
421
422 static void ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
423 {
424 u32 cmd_reg;
425
426 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
427 AR934X_NFC_CMD_SEQ_1C;
428 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
429
430 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
431 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
432
433 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
434 ar934x_nfc_wait_dev_ready(nfc);
435 }
436
437 static int ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column,
438 int page_addr, int len, u32 cmd_reg,
439 u32 ctrl_reg, bool write)
440 {
441 u32 addr0, addr1;
442 u32 dma_ctrl;
443 int dir;
444 int err;
445 int retries = 0;
446
447 WARN_ON(len & 3);
448
449 if (WARN_ON(len > nfc->buf_size))
450 dev_err(nfc->parent, "len=%d > buf_size=%d", len,
451 nfc->buf_size);
452
453 if (write) {
454 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
455 dir = DMA_TO_DEVICE;
456 } else {
457 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
458 dir = DMA_FROM_DEVICE;
459 }
460
461 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
462
463 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
464 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
465 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
466
467 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
468 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
469
470 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
471 (write) ? "write" : "read",
472 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
473
474 retry:
475 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
476 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
477 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
478 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
479 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
480 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
481 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
482 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
483 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg);
484 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg);
485
486 if (ar934x_nfc_use_irq(nfc)) {
487 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK,
488 AR934X_NFC_IRQ_MASK);
489 /* flush write */
490 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
491 }
492
493 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
494 err = ar934x_nfc_wait_done(nfc);
495 if (err) {
496 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
497 (write) ? "write" : "read", page_addr);
498
499 ar934x_nfc_restart(nfc);
500 if (retries++ < AR934X_NFC_DMA_RETRIES)
501 goto retry;
502
503 dev_err(nfc->parent, "%s operation failed on page %d\n",
504 (write) ? "write" : "read", page_addr);
505 }
506
507 return err;
508 }
509
510 static int ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
511 {
512 u32 cmd_reg;
513 int err;
514
515 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
516
517 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
518 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
519
520 err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE,
521 cmd_reg, nfc->ctrl_reg, false);
522
523 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
524
525 return err;
526 }
527
528 static int ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command,
529 int column, int page_addr, int len)
530 {
531 u32 cmd_reg;
532 int err;
533
534 nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
535 column, page_addr, len);
536
537 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
538
539 if (nfc->small_page) {
540 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
541 } else {
542 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
543 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
544 }
545
546 err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
547 cmd_reg, nfc->ctrl_reg, false);
548
549 nfc_debug_data("[data] ", nfc->buf, len);
550
551 return err;
552 }
553
554 static void ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command,
555 int column, int page_addr)
556 {
557 u32 addr0, addr1;
558 u32 ctrl_reg;
559 u32 cmd_reg;
560
561 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
562
563 ctrl_reg = nfc->ctrl_reg;
564 if (nfc->small_page) {
565 /* override number of address cycles for the erase command */
566 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
567 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
568 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
569 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
570 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
571 ctrl_reg |= (nfc->addr_count0 + 1) <<
572 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
573 }
574
575 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
576 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
577 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
578
579 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
580 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
581
582 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
583 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
584 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
585 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
586
587 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
588 ar934x_nfc_wait_dev_ready(nfc);
589 }
590
591 static int ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command,
592 int column, int page_addr, int len)
593 {
594 u32 cmd_reg;
595
596 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
597 column, page_addr, len);
598
599 nfc_debug_data("[data] ", nfc->buf, len);
600
601 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
602 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
603 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
604
605 return ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
606 cmd_reg, nfc->ctrl_reg, true);
607 }
608
609 static void ar934x_nfc_read_status(struct ar934x_nfc *nfc)
610 {
611 u32 cmd_reg;
612 u32 status;
613
614 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
615 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
616
617 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
618 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
619
620 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
621 ar934x_nfc_wait_dev_ready(nfc);
622
623 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
624
625 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
626 cmd_reg, (status & 0xff));
627
628 if (nfc->swap_dma)
629 nfc->buf[0 ^ 3] = status;
630 else
631 nfc->buf[0] = status;
632 }
633
634 static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,
635 int column, int page_addr)
636 {
637 struct mtd_info *mtd = nand_to_mtd(nand);
638 struct ar934x_nfc *nfc = nand->priv;
639
640 nfc->read_id = false;
641 if (command != NAND_CMD_PAGEPROG)
642 nfc->buf_index = 0;
643
644 switch (command) {
645 case NAND_CMD_RESET:
646 ar934x_nfc_send_cmd(nfc, command);
647 break;
648
649 case NAND_CMD_READID:
650 nfc->read_id = true;
651 ar934x_nfc_send_readid(nfc, command);
652 break;
653
654 case NAND_CMD_READ0:
655 case NAND_CMD_READ1:
656 if (nfc->small_page) {
657 ar934x_nfc_send_read(nfc, command, column, page_addr,
658 mtd->writesize + mtd->oobsize);
659 } else {
660 ar934x_nfc_send_read(nfc, command, 0, page_addr,
661 mtd->writesize + mtd->oobsize);
662 nfc->buf_index = column;
663 nfc->rndout_page_addr = page_addr;
664 nfc->rndout_read_cmd = command;
665 }
666 break;
667
668 case NAND_CMD_READOOB:
669 if (nfc->small_page)
670 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
671 column, page_addr,
672 mtd->oobsize);
673 else
674 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
675 mtd->writesize, page_addr,
676 mtd->oobsize);
677 break;
678
679 case NAND_CMD_RNDOUT:
680 if (WARN_ON(nfc->small_page))
681 break;
682
683 /* emulate subpage read */
684 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
685 nfc->rndout_page_addr,
686 mtd->writesize + mtd->oobsize);
687 nfc->buf_index = column;
688 break;
689
690 case NAND_CMD_ERASE1:
691 nfc->erase1_page_addr = page_addr;
692 break;
693
694 case NAND_CMD_ERASE2:
695 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
696 break;
697
698 case NAND_CMD_STATUS:
699 ar934x_nfc_read_status(nfc);
700 break;
701
702 case NAND_CMD_SEQIN:
703 if (nfc->small_page) {
704 /* output read command */
705 if (column >= mtd->writesize) {
706 column -= mtd->writesize;
707 nfc->seqin_read_cmd = NAND_CMD_READOOB;
708 } else if (column < 256) {
709 nfc->seqin_read_cmd = NAND_CMD_READ0;
710 } else {
711 column -= 256;
712 nfc->seqin_read_cmd = NAND_CMD_READ1;
713 }
714 } else {
715 nfc->seqin_read_cmd = NAND_CMD_READ0;
716 }
717 nfc->seqin_column = column;
718 nfc->seqin_page_addr = page_addr;
719 break;
720
721 case NAND_CMD_PAGEPROG:
722 if (nand->ecc.mode == NAND_ECC_HW) {
723 /* the data is already written */
724 break;
725 }
726
727 if (nfc->small_page)
728 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
729
730 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
731 nfc->seqin_page_addr,
732 nfc->buf_index);
733 break;
734
735 default:
736 dev_err(nfc->parent,
737 "unsupported command: %x, column:%d page_addr=%d\n",
738 command, column, page_addr);
739 break;
740 }
741 }
742
743 static int ar934x_nfc_dev_ready(struct nand_chip *chip)
744 {
745 struct ar934x_nfc *nfc = chip->priv;
746
747 return __ar934x_nfc_dev_ready(nfc);
748 }
749
750 static u8 ar934x_nfc_read_byte(struct nand_chip *chip)
751 {
752 struct ar934x_nfc *nfc = chip->priv;
753 u8 data;
754
755 WARN_ON(nfc->buf_index >= nfc->buf_size);
756
757 if (nfc->swap_dma || nfc->read_id)
758 data = nfc->buf[nfc->buf_index ^ 3];
759 else
760 data = nfc->buf[nfc->buf_index];
761
762 nfc->buf_index++;
763
764 return data;
765 }
766
767 static void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
768 {
769 struct ar934x_nfc *nfc = chip->priv;
770 int i;
771
772 WARN_ON(nfc->buf_index + len > nfc->buf_size);
773
774 if (nfc->swap_dma) {
775 for (i = 0; i < len; i++) {
776 nfc->buf[nfc->buf_index ^ 3] = buf[i];
777 nfc->buf_index++;
778 }
779 } else {
780 for (i = 0; i < len; i++) {
781 nfc->buf[nfc->buf_index] = buf[i];
782 nfc->buf_index++;
783 }
784 }
785 }
786
787 static void ar934x_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)
788 {
789 struct ar934x_nfc *nfc = chip->priv;
790 int buf_index;
791 int i;
792
793 WARN_ON(nfc->buf_index + len > nfc->buf_size);
794
795 buf_index = nfc->buf_index;
796
797 if (nfc->swap_dma || nfc->read_id) {
798 for (i = 0; i < len; i++) {
799 buf[i] = nfc->buf[buf_index ^ 3];
800 buf_index++;
801 }
802 } else {
803 for (i = 0; i < len; i++) {
804 buf[i] = nfc->buf[buf_index];
805 buf_index++;
806 }
807 }
808
809 nfc->buf_index = buf_index;
810 }
811
812 static inline void ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc)
813 {
814 nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN;
815 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
816 }
817
818 static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
819 {
820 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN;
821 nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
822 }
823
824 static int ar934x_nfc_read_oob(struct nand_chip *chip,
825 int page)
826 {
827 struct ar934x_nfc *nfc = chip->priv;
828 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
829 int err;
830
831 nfc_dbg(nfc, "read_oob: page:%d\n", page);
832
833 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page,
834 mtd->oobsize);
835 if (err)
836 return err;
837
838 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
839
840 return 0;
841 }
842
843 static int ar934x_nfc_write_oob(struct nand_chip *chip,
844 int page)
845 {
846 struct ar934x_nfc *nfc = chip->priv;
847 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
848 nfc_dbg(nfc, "write_oob: page:%d\n", page);
849
850 memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
851
852 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize,
853 page, mtd->oobsize);
854 }
855
856 static int ar934x_nfc_read_page_raw(
857 struct nand_chip *chip, u8 *buf,
858 int oob_required, int page)
859 {
860 struct ar934x_nfc *nfc = chip->priv;
861 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
862 int len;
863 int err;
864
865 nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required);
866
867 len = mtd->writesize;
868 if (oob_required)
869 len += mtd->oobsize;
870
871 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len);
872 if (err)
873 return err;
874
875 memcpy(buf, nfc->buf, mtd->writesize);
876
877 if (oob_required)
878 memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize);
879
880 return 0;
881 }
882
883 static int ar934x_nfc_read_page(struct nand_chip *chip,
884 u8 *buf, int oob_required, int page)
885 {
886 struct ar934x_nfc *nfc = chip->priv;
887 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
888 u32 ecc_ctrl;
889 int max_bitflips = 0;
890 bool ecc_failed;
891 bool ecc_corrected;
892 int err;
893
894 nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required);
895
896 ar934x_nfc_enable_hwecc(nfc);
897 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page,
898 mtd->writesize);
899 ar934x_nfc_disable_hwecc(nfc);
900
901 if (err)
902 return err;
903
904 /* TODO: optimize to avoid memcpy */
905 memcpy(buf, nfc->buf, mtd->writesize);
906
907 /* read the ECC status */
908 ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL);
909 ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT;
910 ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT;
911
912 if (oob_required || ecc_failed) {
913 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize,
914 page, mtd->oobsize);
915 if (err)
916 return err;
917
918 if (oob_required)
919 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
920 }
921
922 if (ecc_failed) {
923 /*
924 * The hardware ECC engine reports uncorrectable errors
925 * on empty pages. Check the ECC bytes and the data. If
926 * both contains 0xff bytes only, dont report a failure.
927 *
928 * TODO: prebuild a buffer with 0xff bytes and use memcmp
929 * for better performance?
930 */
931 if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) ||
932 !is_all_ff(buf, mtd->writesize))
933 mtd->ecc_stats.failed++;
934 } else if (ecc_corrected) {
935 /*
936 * The hardware does not report the exact count of the
937 * corrected bitflips, use assumptions based on the
938 * threshold.
939 */
940 if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) {
941 /*
942 * The number of corrected bitflips exceeds the
943 * threshold. Assume the maximum.
944 */
945 max_bitflips = chip->ecc.strength * chip->ecc.steps;
946 } else {
947 max_bitflips = nfc->ecc_thres * chip->ecc.steps;
948 }
949
950 mtd->ecc_stats.corrected += max_bitflips;
951 }
952
953 return max_bitflips;
954 }
955
956 static int ar934x_nfc_write_page_raw(
957 struct nand_chip *chip, const u8 *buf,
958 int oob_required, int page)
959 {
960 struct ar934x_nfc *nfc = chip->priv;
961 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
962 int len;
963
964 nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
965
966 memcpy(nfc->buf, buf, mtd->writesize);
967 len = mtd->writesize;
968
969 if (oob_required) {
970 memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize);
971 len += mtd->oobsize;
972 }
973
974 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
975 }
976
977 static int ar934x_nfc_write_page(struct nand_chip *chip,
978 const u8 *buf, int oob_required, int page)
979 {
980 struct ar934x_nfc *nfc = chip->priv;
981 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
982 int err;
983
984 nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
985
986 /* write OOB first */
987 if (oob_required &&
988 !is_all_ff(chip->oob_poi, mtd->oobsize)) {
989 err = ar934x_nfc_write_oob(chip, page);
990 if (err)
991 return err;
992 }
993
994 /* TODO: optimize to avoid memcopy */
995 memcpy(nfc->buf, buf, mtd->writesize);
996
997 ar934x_nfc_enable_hwecc(nfc);
998 err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page,
999 mtd->writesize);
1000 ar934x_nfc_disable_hwecc(nfc);
1001
1002 return err;
1003 }
1004
1005 static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc)
1006 {
1007 int err;
1008
1009 err = reset_control_assert(nfc->rst);
1010 udelay(250);
1011 return err;
1012 }
1013
1014 static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc)
1015 {
1016 int err;
1017
1018 err = reset_control_deassert(nfc->rst);
1019 udelay(250);
1020 return err;
1021 }
1022
1023 static int ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
1024 {
1025 ar934x_nfc_hw_reset_assert(nfc);
1026 ar934x_nfc_hw_reset_deassert(nfc);
1027 /*
1028 * setup timings
1029 * TODO: make it configurable via platform data or DT
1030 */
1031 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
1032 AR934X_NFC_TIME_SEQ_DEFAULT);
1033 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
1034 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
1035 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
1036 AR934X_NFC_TIMINGS_SYN_DEFAULT);
1037
1038 /* disable WP on all chips, and select chip 0 */
1039 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
1040
1041 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
1042
1043 /* initialize Control register */
1044 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1045 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1046
1047 if (nfc->small_page) {
1048 /* Setup generic sequence register for small page reads. */
1049 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
1050 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
1051 }
1052
1053 return 0;
1054 }
1055
1056 static void ar934x_nfc_restart(struct ar934x_nfc *nfc)
1057 {
1058 u32 ctrl_reg;
1059
1060 ctrl_reg = nfc->ctrl_reg;
1061 ar934x_nfc_hw_init(nfc);
1062 nfc->ctrl_reg = ctrl_reg;
1063
1064 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
1065 }
1066
1067 static irqreturn_t ar934x_nfc_irq_handler(int irq, void *data)
1068 {
1069 struct ar934x_nfc *nfc = data;
1070 u32 status;
1071
1072 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1073
1074 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
1075 /* flush write */
1076 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1077
1078 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
1079 if (status) {
1080 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
1081
1082 nfc->irq_status = status;
1083 nfc->spurious_irq_expected = true;
1084 wake_up(&nfc->irq_waitq);
1085 } else {
1086 if (nfc->spurious_irq_expected)
1087 nfc->spurious_irq_expected = false;
1088 else
1089 dev_warn(nfc->parent, "spurious interrupt\n");
1090 }
1091
1092 return IRQ_HANDLED;
1093 }
1094
1095 static int ar934x_nfc_init_tail(struct mtd_info *mtd)
1096 {
1097 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
1098 struct nand_chip *chip = &nfc->nand_chip;
1099 u64 chipsize = nanddev_target_size(&chip->base);
1100 u32 ctrl;
1101 u32 t;
1102 int err;
1103
1104 switch (mtd->oobsize) {
1105 case 16:
1106 case 64:
1107 case 128:
1108 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
1109 break;
1110
1111 default:
1112 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
1113 mtd->oobsize);
1114 return -ENXIO;
1115 }
1116
1117 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1118
1119 switch (mtd->erasesize / mtd->writesize) {
1120 case 32:
1121 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
1122 break;
1123
1124 case 64:
1125 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
1126 break;
1127
1128 case 128:
1129 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
1130 break;
1131
1132 case 256:
1133 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
1134 break;
1135
1136 default:
1137 dev_err(nfc->parent, "unsupported block size: %u\n",
1138 mtd->erasesize / mtd->writesize);
1139 return -ENXIO;
1140 }
1141
1142 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
1143
1144 switch (mtd->writesize) {
1145 case 256:
1146 nfc->small_page = 1;
1147 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
1148 break;
1149
1150 case 512:
1151 nfc->small_page = 1;
1152 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
1153 break;
1154
1155 case 1024:
1156 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
1157 break;
1158
1159 case 2048:
1160 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
1161 break;
1162
1163 case 4096:
1164 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
1165 break;
1166
1167 case 8192:
1168 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
1169 break;
1170
1171 case 16384:
1172 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
1173 break;
1174
1175 default:
1176 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
1177 mtd->writesize);
1178 return -ENXIO;
1179 }
1180
1181 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
1182
1183 if (nfc->small_page) {
1184 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
1185
1186 if (chipsize > (32 << 20)) {
1187 nfc->addr_count0 = 4;
1188 nfc->addr_count1 = 3;
1189 } else if (chipsize > (2 << 16)) {
1190 nfc->addr_count0 = 3;
1191 nfc->addr_count1 = 2;
1192 } else {
1193 nfc->addr_count0 = 2;
1194 nfc->addr_count1 = 1;
1195 }
1196 } else {
1197 if (chipsize > (128 << 20)) {
1198 nfc->addr_count0 = 5;
1199 nfc->addr_count1 = 3;
1200 } else if (chipsize > (8 << 16)) {
1201 nfc->addr_count0 = 4;
1202 nfc->addr_count1 = 2;
1203 } else {
1204 nfc->addr_count0 = 3;
1205 nfc->addr_count1 = 1;
1206 }
1207 }
1208
1209 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
1210 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
1211
1212 nfc->ctrl_reg = ctrl;
1213 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1214
1215 ar934x_nfc_free_buf(nfc);
1216 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
1217
1218 return err;
1219 }
1220
1221 static int ar934x_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1222 struct mtd_oob_region *oobregion)
1223 {
1224 if (section)
1225 return -ERANGE;
1226
1227 oobregion->offset = 20;
1228 oobregion->length = 28;
1229
1230 return 0;
1231 }
1232
1233 static int ar934x_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1234 struct mtd_oob_region *oobregion)
1235 {
1236 switch (section) {
1237 case 0:
1238 oobregion->offset = 4;
1239 oobregion->length = 16;
1240 return 0;
1241 case 1:
1242 oobregion->offset = 48;
1243 oobregion->length = 16;
1244 return 0;
1245 default:
1246 return -ERANGE;
1247 }
1248 }
1249
1250 static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops = {
1251 .ecc = ar934x_nfc_ooblayout_ecc,
1252 .free = ar934x_nfc_ooblayout_free,
1253 };
1254
1255 static int ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
1256 {
1257 struct nand_chip *nand = &nfc->nand_chip;
1258 struct mtd_info *mtd = nand_to_mtd(nand);
1259 u32 ecc_cap;
1260 u32 ecc_thres;
1261 struct mtd_oob_region oobregion;
1262
1263 switch (mtd->writesize) {
1264 case 2048:
1265 /*
1266 * Writing a subpage separately is not supported, because
1267 * the controller only does ECC on full-page accesses.
1268 */
1269
1270 nand->ecc.size = 512;
1271 nand->ecc.bytes = 7;
1272 nand->ecc.strength = 4;
1273 mtd_set_ooblayout(mtd, &ar934x_nfc_ecclayout_ops);
1274 break;
1275
1276 default:
1277 dev_err(nfc->parent,
1278 "hardware ECC is not available for %d byte pages\n",
1279 mtd->writesize);
1280 return -EINVAL;
1281 }
1282
1283 BUG_ON(!mtd->ooblayout->ecc);
1284
1285 switch (nand->ecc.strength) {
1286 case 4:
1287 ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4;
1288 ecc_thres = 4;
1289 break;
1290
1291 default:
1292 dev_err(nfc->parent, "unsupported ECC strength %u\n",
1293 nand->ecc.strength);
1294 return -EINVAL;
1295 }
1296
1297 nfc->ecc_thres = ecc_thres;
1298 mtd->ooblayout->ecc(mtd, 0, &oobregion);
1299 nfc->ecc_oob_pos = oobregion.offset;
1300
1301 nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;
1302 nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;
1303
1304 nfc->ecc_offset_reg = mtd->writesize + nfc->ecc_oob_pos;
1305
1306 nand->ecc.read_page = ar934x_nfc_read_page;
1307 nand->ecc.read_page_raw = ar934x_nfc_read_page_raw;
1308 nand->ecc.write_page = ar934x_nfc_write_page;
1309 nand->ecc.write_page_raw = ar934x_nfc_write_page_raw;
1310 nand->ecc.read_oob = ar934x_nfc_read_oob;
1311 nand->ecc.write_oob = ar934x_nfc_write_oob;
1312
1313 return 0;
1314 }
1315
1316 static int ar934x_nfc_attach_chip(struct nand_chip *nand)
1317 {
1318 struct mtd_info *mtd = nand_to_mtd(nand);
1319 struct ar934x_nfc *nfc = nand_get_controller_data(nand);
1320 struct device *dev = mtd->dev.parent;
1321 int ret;
1322
1323 ret = ar934x_nfc_init_tail(mtd);
1324 if (ret)
1325 return ret;
1326
1327 if (mtd->writesize == 2048)
1328 nand->options |= NAND_NO_SUBPAGE_WRITE;
1329
1330 if (nand->ecc.mode == NAND_ECC_HW) {
1331 ret = ar934x_nfc_setup_hwecc(nfc);
1332 if (ret)
1333 return ret;
1334 } else if (nand->ecc.mode != NAND_ECC_SOFT) {
1335 dev_err(dev, "unknown ECC mode %d\n", nand->ecc.mode);
1336 return -EINVAL;
1337 } else if ((nand->ecc.algo != NAND_ECC_BCH) &&
1338 (nand->ecc.algo != NAND_ECC_HAMMING)) {
1339 dev_err(dev, "unknown software ECC algo %d\n", nand->ecc.algo);
1340 return -EINVAL;
1341 }
1342
1343 return 0;
1344 }
1345
1346 static u64 ar934x_nfc_dma_mask = DMA_BIT_MASK(32);
1347
1348 static void ar934x_nfc_cmd_ctrl(struct nand_chip *chip, int dat,
1349 unsigned int ctrl)
1350 {
1351 WARN_ON(dat != NAND_CMD_NONE);
1352 }
1353
1354 static const struct nand_controller_ops ar934x_nfc_controller_ops = {
1355 .attach_chip = ar934x_nfc_attach_chip,
1356 };
1357
1358 static int ar934x_nfc_probe(struct platform_device *pdev)
1359 {
1360 struct ar934x_nfc *nfc;
1361 struct resource *res;
1362 struct mtd_info *mtd;
1363 struct nand_chip *nand;
1364 int ret;
1365
1366 pdev->dev.dma_mask = &ar934x_nfc_dma_mask;
1367 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1368
1369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370 if (!res) {
1371 dev_err(&pdev->dev, "failed to get I/O memory\n");
1372 return -EINVAL;
1373 }
1374
1375 nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL);
1376 if (!nfc) {
1377 dev_err(&pdev->dev, "failed to allocate driver data\n");
1378 return -ENOMEM;
1379 }
1380
1381 nfc->base = devm_ioremap_resource(&pdev->dev, res);
1382 if (IS_ERR(nfc->base)) {
1383 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1384 return PTR_ERR(nfc->base);
1385 }
1386
1387 nfc->irq = platform_get_irq(pdev, 0);
1388 if (nfc->irq < 0) {
1389 dev_err(&pdev->dev, "no IRQ resource specified\n");
1390 return -EINVAL;
1391 }
1392
1393 init_waitqueue_head(&nfc->irq_waitq);
1394 ret = devm_request_irq(&pdev->dev, nfc->irq, ar934x_nfc_irq_handler,
1395 0, AR934X_NFC_DRIVER_NAME, nfc);
1396 if (ret) {
1397 dev_err(&pdev->dev, "devm_request_irq failed, err:%d\n", ret);
1398 return ret;
1399 }
1400
1401 nfc->rst = devm_reset_control_get(&pdev->dev, "nand");
1402 if (IS_ERR(nfc->rst)) {
1403 dev_err(&pdev->dev, "Failed to get reset\n");
1404 return PTR_ERR(nfc->rst);
1405 }
1406
1407 nfc->parent = &pdev->dev;
1408 nfc->swap_dma = of_property_read_bool(pdev->dev.of_node,
1409 "qca,nand-swap-dma");
1410
1411 nand = &nfc->nand_chip;
1412 mtd = nand_to_mtd(nand);
1413
1414 mtd->owner = THIS_MODULE;
1415 mtd->dev.parent = &pdev->dev;
1416 mtd->name = AR934X_NFC_DRIVER_NAME;
1417
1418 nand_set_controller_data(nand, nfc);
1419 nand_set_flash_node(nand, pdev->dev.of_node);
1420 nand->legacy.chip_delay = 25;
1421 nand->legacy.dev_ready = ar934x_nfc_dev_ready;
1422 nand->legacy.cmdfunc = ar934x_nfc_cmdfunc;
1423 nand->legacy.cmd_ctrl = ar934x_nfc_cmd_ctrl; /* dummy */
1424 nand->legacy.read_byte = ar934x_nfc_read_byte;
1425 nand->legacy.write_buf = ar934x_nfc_write_buf;
1426 nand->legacy.read_buf = ar934x_nfc_read_buf;
1427 nand->ecc.mode = NAND_ECC_HW; /* default */
1428 nand->priv = nfc;
1429 platform_set_drvdata(pdev, nfc);
1430
1431 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1432 if (ret)
1433 return ret;
1434
1435 ret = ar934x_nfc_hw_init(nfc);
1436 if (ret) {
1437 dev_err(&pdev->dev, "hardware init failed, err:%d\n", ret);
1438 goto err_free_buf;
1439 }
1440
1441 nand->legacy.dummy_controller.ops = &ar934x_nfc_controller_ops;
1442 ret = nand_scan(nand, 1);
1443 if (ret) {
1444 dev_err(&pdev->dev, "nand_scan failed, err:%d\n", ret);
1445 goto err_free_buf;
1446 }
1447
1448 ret = mtd_device_register(mtd, NULL, 0);
1449 if (ret) {
1450 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1451 goto err_free_buf;
1452 }
1453
1454 return 0;
1455
1456 err_free_buf:
1457 ar934x_nfc_free_buf(nfc);
1458 return ret;
1459 }
1460
1461 static int ar934x_nfc_remove(struct platform_device *pdev)
1462 {
1463 struct ar934x_nfc *nfc;
1464
1465 nfc = platform_get_drvdata(pdev);
1466 if (nfc) {
1467 nand_release(&nfc->nand_chip);
1468 ar934x_nfc_free_buf(nfc);
1469 }
1470
1471 return 0;
1472 }
1473
1474 static const struct of_device_id ar934x_nfc_match[] = {
1475 { .compatible = "qca," AR934X_NFC_DRIVER_NAME },
1476 {},
1477 };
1478
1479 MODULE_DEVICE_TABLE(of, ar934x_nfc_match);
1480
1481 static struct platform_driver ar934x_nfc_driver = {
1482 .probe = ar934x_nfc_probe,
1483 .remove = ar934x_nfc_remove,
1484 .driver = {
1485 .name = AR934X_NFC_DRIVER_NAME,
1486 .owner = THIS_MODULE,
1487 .of_match_table = ar934x_nfc_match,
1488 },
1489 };
1490
1491 module_platform_driver(ar934x_nfc_driver);
1492
1493 MODULE_LICENSE("GPL v2");
1494 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1495 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1496 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
Staging tree of Christian Lamparter