2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/version.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/rawnand.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/slab.h>
24 #include <linux/of_device.h>
25 #include <linux/reset.h>
27 #define AR934X_NFC_DRIVER_NAME "ar934x-nand"
29 #define AR934X_NFC_REG_CMD 0x00
30 #define AR934X_NFC_REG_CTRL 0x04
31 #define AR934X_NFC_REG_STATUS 0x08
32 #define AR934X_NFC_REG_INT_MASK 0x0c
33 #define AR934X_NFC_REG_INT_STATUS 0x10
34 #define AR934X_NFC_REG_ECC_CTRL 0x14
35 #define AR934X_NFC_REG_ECC_OFFSET 0x18
36 #define AR934X_NFC_REG_ADDR0_0 0x1c
37 #define AR934X_NFC_REG_ADDR0_1 0x24
38 #define AR934X_NFC_REG_ADDR1_0 0x20
39 #define AR934X_NFC_REG_ADDR1_1 0x28
40 #define AR934X_NFC_REG_SPARE_SIZE 0x30
41 #define AR934X_NFC_REG_PROTECT 0x38
42 #define AR934X_NFC_REG_LOOKUP_EN 0x40
43 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
44 #define AR934X_NFC_REG_DMA_ADDR 0x64
45 #define AR934X_NFC_REG_DMA_COUNT 0x68
46 #define AR934X_NFC_REG_DMA_CTRL 0x6c
47 #define AR934X_NFC_REG_MEM_CTRL 0x80
48 #define AR934X_NFC_REG_DATA_SIZE 0x84
49 #define AR934X_NFC_REG_READ_STATUS 0x88
50 #define AR934X_NFC_REG_TIME_SEQ 0x8c
51 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
52 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
53 #define AR934X_NFC_REG_FIFO_DATA 0x98
54 #define AR934X_NFC_REG_TIME_MODE 0x9c
55 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
56 #define AR934X_NFC_REG_FIFO_INIT 0xb0
57 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
59 #define AR934X_NFC_CMD_CMD_SEQ_S 0
60 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
61 #define AR934X_NFC_CMD_SEQ_1C 0x00
62 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
63 #define AR934X_NFC_CMD_SEQ_12 0x0c
64 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
65 #define AR934X_NFC_CMD_SEQ_S 0x24
66 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
67 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
68 #define AR934X_NFC_CMD_SEQ_18 0x32
69 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
70 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
71 #define AR934X_NFC_CMD_ADDR_SEL_0 0
72 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
73 #define AR934X_NFC_CMD_CMD0_S 8
74 #define AR934X_NFC_CMD_CMD0_M 0xff
75 #define AR934X_NFC_CMD_CMD1_S 16
76 #define AR934X_NFC_CMD_CMD1_M 0xff
77 #define AR934X_NFC_CMD_CMD2_S 24
78 #define AR934X_NFC_CMD_CMD2_M 0xff
80 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
81 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
82 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
83 #define AR934X_NFC_CTRL_INT_EN BIT(4)
84 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
86 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
87 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
88 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
89 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
90 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
91 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
92 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
93 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
94 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
95 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
96 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
97 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
98 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
99 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
100 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
101 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
102 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
103 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
104 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
105 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
106 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
107 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
108 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
109 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
110 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
111 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
113 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
114 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
115 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
116 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
119 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
120 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
121 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
122 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
123 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
124 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
125 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
127 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
128 #define AR934X_NFC_INT_CMD_END BIT(1)
130 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
131 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
132 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
133 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
137 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
138 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
139 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
140 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
141 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
142 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
143 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
144 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
146 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
148 /* default timing values */
149 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
150 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
151 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
153 #define AR934X_NFC_ID_BUF_SIZE 8
154 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
155 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
156 #define AR934X_NFC_DONE_TIMEOUT 1000
157 #define AR934X_NFC_DMA_RETRIES 20
159 #define AR934X_NFC_USE_IRQ true
160 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
162 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
164 #undef AR934X_NFC_DEBUG_DATA
165 #undef AR934X_NFC_DEBUG
168 struct mtd_partition
;
172 struct nand_chip nand_chip
;
173 struct device
*parent
;
177 wait_queue_head_t irq_waitq
;
179 bool spurious_irq_expected
;
189 unsigned int addr_count0
;
190 unsigned int addr_count1
;
194 unsigned int buf_size
;
199 int erase1_page_addr
;
201 int rndout_page_addr
;
208 struct reset_control
*rst
;
211 static inline __printf(2, 3)
212 void _nfc_dbg(struct ar934x_nfc
*nfc
, const char *fmt
, ...)
216 #ifdef AR934X_NFC_DEBUG
217 #define nfc_dbg(_nfc, fmt, ...) \
218 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
220 #define nfc_dbg(_nfc, fmt, ...) \
221 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
222 #endif /* AR934X_NFC_DEBUG */
224 #ifdef AR934X_NFC_DEBUG_DATA
225 static void nfc_debug_data(const char *label
, void *data
, int len
)
227 print_hex_dump(KERN_WARNING
, label
, DUMP_PREFIX_OFFSET
, 16, 1,
231 static inline void nfc_debug_data(const char *label
, void *data
, int len
) {}
232 #endif /* AR934X_NFC_DEBUG_DATA */
234 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
);
236 static inline bool is_all_ff(u8
*buf
, int len
)
239 if (buf
[len
] != 0xff)
245 static inline void ar934x_nfc_wr(struct ar934x_nfc
*nfc
, unsigned reg
, u32 val
)
247 __raw_writel(val
, nfc
->base
+ reg
);
250 static inline u32
ar934x_nfc_rr(struct ar934x_nfc
*nfc
, unsigned reg
)
252 return __raw_readl(nfc
->base
+ reg
);
255 static inline struct ar934x_nfc
*mtd_to_ar934x_nfc(struct mtd_info
*mtd
)
257 struct nand_chip
*chip
= mtd_to_nand(mtd
);
259 return container_of(chip
, struct ar934x_nfc
, nand_chip
);
262 static struct mtd_info
*ar934x_nfc_to_mtd(struct ar934x_nfc
*nfc
)
264 return nand_to_mtd(&nfc
->nand_chip
);
267 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc
*nfc
)
269 return AR934X_NFC_USE_IRQ
;
272 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc
*nfc
, u32 cmd_reg
)
276 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CMD
, cmd_reg
);
278 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_CMD
);
281 static bool __ar934x_nfc_dev_ready(struct ar934x_nfc
*nfc
)
285 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
);
286 return (status
& 0xff) == 0xff;
289 static inline bool __ar934x_nfc_is_dma_ready(struct ar934x_nfc
*nfc
)
293 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
);
294 return (status
& AR934X_NFC_DMA_CTRL_DMA_READY
) != 0;
297 static int ar934x_nfc_wait_dev_ready(struct ar934x_nfc
*nfc
)
299 unsigned long timeout
;
301 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
);
303 if (__ar934x_nfc_dev_ready(nfc
))
305 } while time_before(jiffies
, timeout
);
307 nfc_dbg(nfc
, "timeout waiting for device ready, status:%08x int:%08x\n",
308 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
),
309 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
));
313 static int ar934x_nfc_wait_dma_ready(struct ar934x_nfc
*nfc
)
315 unsigned long timeout
;
317 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT
);
319 if (__ar934x_nfc_is_dma_ready(nfc
))
321 } while time_before(jiffies
, timeout
);
323 nfc_dbg(nfc
, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
324 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
));
328 static int ar934x_nfc_wait_irq(struct ar934x_nfc
*nfc
)
333 timeout
= wait_event_timeout(nfc
->irq_waitq
,
334 (nfc
->irq_status
& AR934X_NFC_IRQ_MASK
) != 0,
335 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
));
339 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, 0);
340 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
342 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
345 "timeout waiting for interrupt, status:%08x\n",
354 static int ar934x_nfc_wait_done(struct ar934x_nfc
*nfc
)
358 if (ar934x_nfc_use_irq(nfc
))
359 ret
= ar934x_nfc_wait_irq(nfc
);
361 ret
= ar934x_nfc_wait_dev_ready(nfc
);
366 return ar934x_nfc_wait_dma_ready(nfc
);
369 static int ar934x_nfc_alloc_buf(struct ar934x_nfc
*nfc
, unsigned size
)
371 nfc
->buf
= dma_alloc_coherent(nfc
->parent
, size
,
372 &nfc
->buf_dma
, GFP_KERNEL
);
373 if (nfc
->buf
== NULL
) {
374 dev_err(nfc
->parent
, "no memory for DMA buffer\n");
378 nfc
->buf_size
= size
;
379 nfc_dbg(nfc
, "buf:%p size:%u\n", nfc
->buf
, nfc
->buf_size
);
384 static void ar934x_nfc_free_buf(struct ar934x_nfc
*nfc
)
386 dma_free_coherent(nfc
->parent
, nfc
->buf_size
, nfc
->buf
, nfc
->buf_dma
);
389 static void ar934x_nfc_get_addr(struct ar934x_nfc
*nfc
, int column
,
390 int page_addr
, u32
*addr0
, u32
*addr1
)
399 a0
= (page_addr
& 0xffff) << 16;
400 a1
= (page_addr
>> 16) & 0xf;
401 } else if (page_addr
!= -1) {
402 /* SEQIN, READ0, etc.. */
404 /* TODO: handle 16bit bus width */
405 if (nfc
->small_page
) {
407 a0
|= (page_addr
& 0xff) << 8;
408 a0
|= ((page_addr
>> 8) & 0xff) << 16;
409 a0
|= ((page_addr
>> 16) & 0xff) << 24;
411 a0
= column
& 0x0FFF;
412 a0
|= (page_addr
& 0xffff) << 16;
414 if (nfc
->addr_count0
> 4)
415 a1
= (page_addr
>> 16) & 0xf;
423 static void ar934x_nfc_send_cmd(struct ar934x_nfc
*nfc
, unsigned command
)
427 cmd_reg
= AR934X_NFC_CMD_INPUT_SEL_SIU
| AR934X_NFC_CMD_ADDR_SEL_0
|
428 AR934X_NFC_CMD_SEQ_1C
;
429 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
431 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
432 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
434 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
435 ar934x_nfc_wait_dev_ready(nfc
);
438 static int ar934x_nfc_do_rw_command(struct ar934x_nfc
*nfc
, int column
,
439 int page_addr
, int len
, u32 cmd_reg
,
440 u32 ctrl_reg
, bool write
)
450 if (WARN_ON(len
> nfc
->buf_size
))
451 dev_err(nfc
->parent
, "len=%d > buf_size=%d", len
,
455 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE
;
458 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_READ
;
459 dir
= DMA_FROM_DEVICE
;
462 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
464 dma_ctrl
|= AR934X_NFC_DMA_CTRL_DMA_START
|
465 (AR934X_NFC_DMA_CTRL_DMA_BURST_3
<<
466 AR934X_NFC_DMA_CTRL_DMA_BURST_S
);
468 cmd_reg
|= AR934X_NFC_CMD_INPUT_SEL_DMA
| AR934X_NFC_CMD_ADDR_SEL_0
;
469 ctrl_reg
|= AR934X_NFC_CTRL_INT_EN
;
471 nfc_dbg(nfc
, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
472 (write
) ? "write" : "read",
473 addr0
, addr1
, len
, cmd_reg
, dma_ctrl
, ctrl_reg
);
476 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
477 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
478 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
479 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR
, nfc
->buf_dma
);
480 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_COUNT
, len
);
481 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DATA_SIZE
, len
);
482 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
483 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_CTRL
, dma_ctrl
);
484 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_CTRL
, nfc
->ecc_ctrl_reg
);
485 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_OFFSET
, nfc
->ecc_offset_reg
);
487 if (ar934x_nfc_use_irq(nfc
)) {
488 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
,
489 AR934X_NFC_IRQ_MASK
);
491 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
494 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
495 err
= ar934x_nfc_wait_done(nfc
);
497 dev_dbg(nfc
->parent
, "%s operation stuck at page %d\n",
498 (write
) ? "write" : "read", page_addr
);
500 ar934x_nfc_restart(nfc
);
501 if (retries
++ < AR934X_NFC_DMA_RETRIES
)
504 dev_err(nfc
->parent
, "%s operation failed on page %d\n",
505 (write
) ? "write" : "read", page_addr
);
511 static int ar934x_nfc_send_readid(struct ar934x_nfc
*nfc
, unsigned command
)
516 nfc_dbg(nfc
, "readid, cmd:%02x\n", command
);
518 cmd_reg
= AR934X_NFC_CMD_SEQ_1C1AXR
;
519 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
521 err
= ar934x_nfc_do_rw_command(nfc
, -1, -1, AR934X_NFC_ID_BUF_SIZE
,
522 cmd_reg
, nfc
->ctrl_reg
, false);
524 nfc_debug_data("[id] ", nfc
->buf
, AR934X_NFC_ID_BUF_SIZE
);
529 static int ar934x_nfc_send_read(struct ar934x_nfc
*nfc
, unsigned command
,
530 int column
, int page_addr
, int len
)
535 nfc_dbg(nfc
, "read, column=%d page=%d len=%d\n",
536 column
, page_addr
, len
);
538 cmd_reg
= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
540 if (nfc
->small_page
) {
541 cmd_reg
|= AR934X_NFC_CMD_SEQ_18
;
543 cmd_reg
|= NAND_CMD_READSTART
<< AR934X_NFC_CMD_CMD1_S
;
544 cmd_reg
|= AR934X_NFC_CMD_SEQ_1C5A1CXR
;
547 err
= ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
548 cmd_reg
, nfc
->ctrl_reg
, false);
550 nfc_debug_data("[data] ", nfc
->buf
, len
);
555 static void ar934x_nfc_send_erase(struct ar934x_nfc
*nfc
, unsigned command
,
556 int column
, int page_addr
)
562 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
564 ctrl_reg
= nfc
->ctrl_reg
;
565 if (nfc
->small_page
) {
566 /* override number of address cycles for the erase command */
567 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M
<<
568 AR934X_NFC_CTRL_ADDR_CYCLE0_S
);
569 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M
<<
570 AR934X_NFC_CTRL_ADDR_CYCLE1_S
);
571 ctrl_reg
&= ~(AR934X_NFC_CTRL_SMALL_PAGE
);
572 ctrl_reg
|= (nfc
->addr_count0
+ 1) <<
573 AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
576 cmd_reg
= NAND_CMD_ERASE1
<< AR934X_NFC_CMD_CMD0_S
;
577 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
578 cmd_reg
|= AR934X_NFC_CMD_SEQ_ERASE
;
580 nfc_dbg(nfc
, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
581 page_addr
, addr0
, addr1
, cmd_reg
, ctrl_reg
);
583 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
584 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
585 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
586 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
588 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
589 ar934x_nfc_wait_dev_ready(nfc
);
592 static int ar934x_nfc_send_write(struct ar934x_nfc
*nfc
, unsigned command
,
593 int column
, int page_addr
, int len
)
597 nfc_dbg(nfc
, "write, column=%d page=%d len=%d\n",
598 column
, page_addr
, len
);
600 nfc_debug_data("[data] ", nfc
->buf
, len
);
602 cmd_reg
= NAND_CMD_SEQIN
<< AR934X_NFC_CMD_CMD0_S
;
603 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
604 cmd_reg
|= AR934X_NFC_CMD_SEQ_12
;
606 return ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
607 cmd_reg
, nfc
->ctrl_reg
, true);
610 static void ar934x_nfc_read_status(struct ar934x_nfc
*nfc
)
615 cmd_reg
= NAND_CMD_STATUS
<< AR934X_NFC_CMD_CMD0_S
;
616 cmd_reg
|= AR934X_NFC_CMD_SEQ_S
;
618 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
619 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
621 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
622 ar934x_nfc_wait_dev_ready(nfc
);
624 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_READ_STATUS
);
626 nfc_dbg(nfc
, "read status, cmd:%08x status:%02x\n",
627 cmd_reg
, (status
& 0xff));
630 nfc
->buf
[0 ^ 3] = status
;
632 nfc
->buf
[0] = status
;
635 static void ar934x_nfc_cmdfunc(struct nand_chip
*nand
, unsigned int command
,
636 int column
, int page_addr
)
638 struct mtd_info
*mtd
= nand_to_mtd(nand
);
639 struct ar934x_nfc
*nfc
= nand
->priv
;
641 nfc
->read_id
= false;
642 if (command
!= NAND_CMD_PAGEPROG
)
647 ar934x_nfc_send_cmd(nfc
, command
);
650 case NAND_CMD_READID
:
652 ar934x_nfc_send_readid(nfc
, command
);
657 if (nfc
->small_page
) {
658 ar934x_nfc_send_read(nfc
, command
, column
, page_addr
,
659 mtd
->writesize
+ mtd
->oobsize
);
661 ar934x_nfc_send_read(nfc
, command
, 0, page_addr
,
662 mtd
->writesize
+ mtd
->oobsize
);
663 nfc
->buf_index
= column
;
664 nfc
->rndout_page_addr
= page_addr
;
665 nfc
->rndout_read_cmd
= command
;
669 case NAND_CMD_READOOB
:
671 ar934x_nfc_send_read(nfc
, NAND_CMD_READOOB
,
675 ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
,
676 mtd
->writesize
, page_addr
,
680 case NAND_CMD_RNDOUT
:
681 if (WARN_ON(nfc
->small_page
))
684 /* emulate subpage read */
685 ar934x_nfc_send_read(nfc
, nfc
->rndout_read_cmd
, 0,
686 nfc
->rndout_page_addr
,
687 mtd
->writesize
+ mtd
->oobsize
);
688 nfc
->buf_index
= column
;
691 case NAND_CMD_ERASE1
:
692 nfc
->erase1_page_addr
= page_addr
;
695 case NAND_CMD_ERASE2
:
696 ar934x_nfc_send_erase(nfc
, command
, -1, nfc
->erase1_page_addr
);
699 case NAND_CMD_STATUS
:
700 ar934x_nfc_read_status(nfc
);
704 if (nfc
->small_page
) {
705 /* output read command */
706 if (column
>= mtd
->writesize
) {
707 column
-= mtd
->writesize
;
708 nfc
->seqin_read_cmd
= NAND_CMD_READOOB
;
709 } else if (column
< 256) {
710 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
713 nfc
->seqin_read_cmd
= NAND_CMD_READ1
;
716 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
718 nfc
->seqin_column
= column
;
719 nfc
->seqin_page_addr
= page_addr
;
722 case NAND_CMD_PAGEPROG
:
723 if (nand
->ecc
.engine_type
== NAND_ECC_ENGINE_TYPE_ON_HOST
) {
724 /* the data is already written */
729 ar934x_nfc_send_cmd(nfc
, nfc
->seqin_read_cmd
);
731 ar934x_nfc_send_write(nfc
, command
, nfc
->seqin_column
,
732 nfc
->seqin_page_addr
,
738 "unsupported command: %x, column:%d page_addr=%d\n",
739 command
, column
, page_addr
);
744 static int ar934x_nfc_dev_ready(struct nand_chip
*chip
)
746 struct ar934x_nfc
*nfc
= chip
->priv
;
748 return __ar934x_nfc_dev_ready(nfc
);
751 static u8
ar934x_nfc_read_byte(struct nand_chip
*chip
)
753 struct ar934x_nfc
*nfc
= chip
->priv
;
756 WARN_ON(nfc
->buf_index
>= nfc
->buf_size
);
758 if (nfc
->swap_dma
|| nfc
->read_id
)
759 data
= nfc
->buf
[nfc
->buf_index
^ 3];
761 data
= nfc
->buf
[nfc
->buf_index
];
768 static void ar934x_nfc_write_buf(struct nand_chip
*chip
, const u8
*buf
, int len
)
770 struct ar934x_nfc
*nfc
= chip
->priv
;
773 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
776 for (i
= 0; i
< len
; i
++) {
777 nfc
->buf
[nfc
->buf_index
^ 3] = buf
[i
];
781 for (i
= 0; i
< len
; i
++) {
782 nfc
->buf
[nfc
->buf_index
] = buf
[i
];
788 static void ar934x_nfc_read_buf(struct nand_chip
*chip
, u8
*buf
, int len
)
790 struct ar934x_nfc
*nfc
= chip
->priv
;
794 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
796 buf_index
= nfc
->buf_index
;
798 if (nfc
->swap_dma
|| nfc
->read_id
) {
799 for (i
= 0; i
< len
; i
++) {
800 buf
[i
] = nfc
->buf
[buf_index
^ 3];
804 for (i
= 0; i
< len
; i
++) {
805 buf
[i
] = nfc
->buf
[buf_index
];
810 nfc
->buf_index
= buf_index
;
813 static inline void ar934x_nfc_enable_hwecc(struct ar934x_nfc
*nfc
)
815 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_ECC_EN
;
816 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
819 static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc
*nfc
)
821 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_ECC_EN
;
822 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
825 static int ar934x_nfc_read_oob(struct nand_chip
*chip
,
828 struct ar934x_nfc
*nfc
= chip
->priv
;
829 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
832 nfc_dbg(nfc
, "read_oob: page:%d\n", page
);
834 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
, page
,
839 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
844 static int ar934x_nfc_write_oob(struct nand_chip
*chip
,
847 struct ar934x_nfc
*nfc
= chip
->priv
;
848 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
849 nfc_dbg(nfc
, "write_oob: page:%d\n", page
);
851 memcpy(nfc
->buf
, chip
->oob_poi
, mtd
->oobsize
);
853 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, mtd
->writesize
,
857 static int ar934x_nfc_read_page_raw(
858 struct nand_chip
*chip
, u8
*buf
,
859 int oob_required
, int page
)
861 struct ar934x_nfc
*nfc
= chip
->priv
;
862 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
866 nfc_dbg(nfc
, "read_page_raw: page:%d oob:%d\n", page
, oob_required
);
868 len
= mtd
->writesize
;
872 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
, len
);
876 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
879 memcpy(chip
->oob_poi
, &nfc
->buf
[mtd
->writesize
], mtd
->oobsize
);
884 static int ar934x_nfc_read_page(struct nand_chip
*chip
,
885 u8
*buf
, int oob_required
, int page
)
887 struct ar934x_nfc
*nfc
= chip
->priv
;
888 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
890 int max_bitflips
= 0;
895 nfc_dbg(nfc
, "read_page: page:%d oob:%d\n", page
, oob_required
);
897 ar934x_nfc_enable_hwecc(nfc
);
898 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
,
900 ar934x_nfc_disable_hwecc(nfc
);
905 /* TODO: optimize to avoid memcpy */
906 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
908 /* read the ECC status */
909 ecc_ctrl
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_ECC_CTRL
);
910 ecc_failed
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_UNCORRECT
;
911 ecc_corrected
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_CORRECT
;
913 if (oob_required
|| ecc_failed
) {
914 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
,
920 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
925 * The hardware ECC engine reports uncorrectable errors
926 * on empty pages. Check the ECC bytes and the data. If
927 * both contains 0xff bytes only, dont report a failure.
929 * TODO: prebuild a buffer with 0xff bytes and use memcmp
930 * for better performance?
932 if (!is_all_ff(&nfc
->buf
[nfc
->ecc_oob_pos
], chip
->ecc
.total
) ||
933 !is_all_ff(buf
, mtd
->writesize
))
934 mtd
->ecc_stats
.failed
++;
935 } else if (ecc_corrected
) {
937 * The hardware does not report the exact count of the
938 * corrected bitflips, use assumptions based on the
941 if (ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_OVER
) {
943 * The number of corrected bitflips exceeds the
944 * threshold. Assume the maximum.
946 max_bitflips
= chip
->ecc
.strength
* chip
->ecc
.steps
;
948 max_bitflips
= nfc
->ecc_thres
* chip
->ecc
.steps
;
951 mtd
->ecc_stats
.corrected
+= max_bitflips
;
957 static int ar934x_nfc_write_page_raw(
958 struct nand_chip
*chip
, const u8
*buf
,
959 int oob_required
, int page
)
961 struct ar934x_nfc
*nfc
= chip
->priv
;
962 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
965 nfc_dbg(nfc
, "write_page_raw: page:%d oob:%d\n", page
, oob_required
);
967 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
968 len
= mtd
->writesize
;
971 memcpy(&nfc
->buf
[mtd
->writesize
], chip
->oob_poi
, mtd
->oobsize
);
975 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
, len
);
978 static int ar934x_nfc_write_page(struct nand_chip
*chip
,
979 const u8
*buf
, int oob_required
, int page
)
981 struct ar934x_nfc
*nfc
= chip
->priv
;
982 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
985 nfc_dbg(nfc
, "write_page: page:%d oob:%d\n", page
, oob_required
);
987 /* write OOB first */
989 !is_all_ff(chip
->oob_poi
, mtd
->oobsize
)) {
990 err
= ar934x_nfc_write_oob(chip
, page
);
995 /* TODO: optimize to avoid memcopy */
996 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
998 ar934x_nfc_enable_hwecc(nfc
);
999 err
= ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
,
1001 ar934x_nfc_disable_hwecc(nfc
);
1006 static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc
*nfc
)
1010 err
= reset_control_assert(nfc
->rst
);
1015 static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc
*nfc
)
1019 err
= reset_control_deassert(nfc
->rst
);
1024 static int ar934x_nfc_hw_init(struct ar934x_nfc
*nfc
)
1026 ar934x_nfc_hw_reset_assert(nfc
);
1027 ar934x_nfc_hw_reset_deassert(nfc
);
1030 * TODO: make it configurable via platform data or DT
1032 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIME_SEQ
,
1033 AR934X_NFC_TIME_SEQ_DEFAULT
);
1034 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_ASYN
,
1035 AR934X_NFC_TIMINGS_ASYN_DEFAULT
);
1036 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_SYN
,
1037 AR934X_NFC_TIMINGS_SYN_DEFAULT
);
1039 /* disable WP on all chips, and select chip 0 */
1040 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_MEM_CTRL
, 0xff00);
1042 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR_OFFS
, 0);
1044 /* initialize Control register */
1045 nfc
->ctrl_reg
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1046 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1048 if (nfc
->small_page
) {
1049 /* Setup generic sequence register for small page reads. */
1050 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_GEN_SEQ_CTRL
,
1051 AR934X_NFC_GENSEQ_SMALL_PAGE_READ
);
1057 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
)
1061 ctrl_reg
= nfc
->ctrl_reg
;
1062 ar934x_nfc_hw_init(nfc
);
1063 nfc
->ctrl_reg
= ctrl_reg
;
1065 ar934x_nfc_send_cmd(nfc
, NAND_CMD_RESET
);
1068 static irqreturn_t
ar934x_nfc_irq_handler(int irq
, void *data
)
1070 struct ar934x_nfc
*nfc
= data
;
1073 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1075 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
1077 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1079 status
&= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
1081 nfc_dbg(nfc
, "got IRQ, status:%08x\n", status
);
1083 nfc
->irq_status
= status
;
1084 nfc
->spurious_irq_expected
= true;
1085 wake_up(&nfc
->irq_waitq
);
1087 if (nfc
->spurious_irq_expected
)
1088 nfc
->spurious_irq_expected
= false;
1090 dev_warn(nfc
->parent
, "spurious interrupt\n");
1096 static int ar934x_nfc_init_tail(struct mtd_info
*mtd
)
1098 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1099 struct nand_chip
*chip
= &nfc
->nand_chip
;
1100 u64 chipsize
= nanddev_target_size(&chip
->base
);
1105 switch (mtd
->oobsize
) {
1109 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_SPARE_SIZE
, mtd
->oobsize
);
1113 dev_err(nfc
->parent
, "unsupported OOB size: %d bytes\n",
1118 ctrl
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1120 switch (mtd
->erasesize
/ mtd
->writesize
) {
1122 t
= AR934X_NFC_CTRL_BLOCK_SIZE_32
;
1126 t
= AR934X_NFC_CTRL_BLOCK_SIZE_64
;
1130 t
= AR934X_NFC_CTRL_BLOCK_SIZE_128
;
1134 t
= AR934X_NFC_CTRL_BLOCK_SIZE_256
;
1138 dev_err(nfc
->parent
, "unsupported block size: %u\n",
1139 mtd
->erasesize
/ mtd
->writesize
);
1143 ctrl
|= t
<< AR934X_NFC_CTRL_BLOCK_SIZE_S
;
1145 switch (mtd
->writesize
) {
1147 nfc
->small_page
= 1;
1148 t
= AR934X_NFC_CTRL_PAGE_SIZE_256
;
1152 nfc
->small_page
= 1;
1153 t
= AR934X_NFC_CTRL_PAGE_SIZE_512
;
1157 t
= AR934X_NFC_CTRL_PAGE_SIZE_1024
;
1161 t
= AR934X_NFC_CTRL_PAGE_SIZE_2048
;
1165 t
= AR934X_NFC_CTRL_PAGE_SIZE_4096
;
1169 t
= AR934X_NFC_CTRL_PAGE_SIZE_8192
;
1173 t
= AR934X_NFC_CTRL_PAGE_SIZE_16384
;
1177 dev_err(nfc
->parent
, "unsupported write size: %d bytes\n",
1182 ctrl
|= t
<< AR934X_NFC_CTRL_PAGE_SIZE_S
;
1184 if (nfc
->small_page
) {
1185 ctrl
|= AR934X_NFC_CTRL_SMALL_PAGE
;
1187 if (chipsize
> (32 << 20)) {
1188 nfc
->addr_count0
= 4;
1189 nfc
->addr_count1
= 3;
1190 } else if (chipsize
> (2 << 16)) {
1191 nfc
->addr_count0
= 3;
1192 nfc
->addr_count1
= 2;
1194 nfc
->addr_count0
= 2;
1195 nfc
->addr_count1
= 1;
1198 if (chipsize
> (128 << 20)) {
1199 nfc
->addr_count0
= 5;
1200 nfc
->addr_count1
= 3;
1201 } else if (chipsize
> (8 << 16)) {
1202 nfc
->addr_count0
= 4;
1203 nfc
->addr_count1
= 2;
1205 nfc
->addr_count0
= 3;
1206 nfc
->addr_count1
= 1;
1210 ctrl
|= nfc
->addr_count0
<< AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
1211 ctrl
|= nfc
->addr_count1
<< AR934X_NFC_CTRL_ADDR_CYCLE1_S
;
1213 nfc
->ctrl_reg
= ctrl
;
1214 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1216 ar934x_nfc_free_buf(nfc
);
1217 err
= ar934x_nfc_alloc_buf(nfc
, mtd
->writesize
+ mtd
->oobsize
);
1222 static int ar934x_nfc_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1223 struct mtd_oob_region
*oobregion
)
1228 oobregion
->offset
= 20;
1229 oobregion
->length
= 28;
1234 static int ar934x_nfc_ooblayout_free(struct mtd_info
*mtd
, int section
,
1235 struct mtd_oob_region
*oobregion
)
1239 oobregion
->offset
= 4;
1240 oobregion
->length
= 16;
1243 oobregion
->offset
= 48;
1244 oobregion
->length
= 16;
1251 static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops
= {
1252 .ecc
= ar934x_nfc_ooblayout_ecc
,
1253 .free
= ar934x_nfc_ooblayout_free
,
1256 static int ar934x_nfc_setup_hwecc(struct ar934x_nfc
*nfc
)
1258 struct nand_chip
*nand
= &nfc
->nand_chip
;
1259 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1262 struct mtd_oob_region oobregion
;
1264 switch (mtd
->writesize
) {
1267 * Writing a subpage separately is not supported, because
1268 * the controller only does ECC on full-page accesses.
1271 nand
->ecc
.size
= 512;
1272 nand
->ecc
.bytes
= 7;
1273 nand
->ecc
.strength
= 4;
1274 mtd_set_ooblayout(mtd
, &ar934x_nfc_ecclayout_ops
);
1278 dev_err(nfc
->parent
,
1279 "hardware ECC is not available for %d byte pages\n",
1284 BUG_ON(!mtd
->ooblayout
->ecc
);
1286 switch (nand
->ecc
.strength
) {
1288 ecc_cap
= AR934X_NFC_ECC_CTRL_ECC_CAP_4
;
1293 dev_err(nfc
->parent
, "unsupported ECC strength %u\n",
1294 nand
->ecc
.strength
);
1298 nfc
->ecc_thres
= ecc_thres
;
1299 mtd
->ooblayout
->ecc(mtd
, 0, &oobregion
);
1300 nfc
->ecc_oob_pos
= oobregion
.offset
;
1302 nfc
->ecc_ctrl_reg
= ecc_cap
<< AR934X_NFC_ECC_CTRL_ECC_CAP_S
;
1303 nfc
->ecc_ctrl_reg
|= ecc_thres
<< AR934X_NFC_ECC_CTRL_ERR_THRES_S
;
1305 nfc
->ecc_offset_reg
= mtd
->writesize
+ nfc
->ecc_oob_pos
;
1307 nand
->ecc
.read_page
= ar934x_nfc_read_page
;
1308 nand
->ecc
.read_page_raw
= ar934x_nfc_read_page_raw
;
1309 nand
->ecc
.write_page
= ar934x_nfc_write_page
;
1310 nand
->ecc
.write_page_raw
= ar934x_nfc_write_page_raw
;
1311 nand
->ecc
.read_oob
= ar934x_nfc_read_oob
;
1312 nand
->ecc
.write_oob
= ar934x_nfc_write_oob
;
1317 static int ar934x_nfc_attach_chip(struct nand_chip
*nand
)
1319 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1320 struct ar934x_nfc
*nfc
= nand_get_controller_data(nand
);
1321 struct device
*dev
= mtd
->dev
.parent
;
1324 ret
= ar934x_nfc_init_tail(mtd
);
1328 if (mtd
->writesize
== 2048)
1329 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
1331 if (nand
->ecc
.engine_type
== NAND_ECC_ENGINE_TYPE_ON_HOST
) {
1332 ret
= ar934x_nfc_setup_hwecc(nfc
);
1335 } else if (nand
->ecc
.engine_type
!= NAND_ECC_ENGINE_TYPE_SOFT
) {
1336 dev_err(dev
, "unknown ECC mode %d\n", nand
->ecc
.engine_type
);
1338 } else if ((nand
->ecc
.algo
!= NAND_ECC_ALGO_BCH
) &&
1339 (nand
->ecc
.algo
!= NAND_ECC_ALGO_HAMMING
)) {
1340 dev_err(dev
, "unknown software ECC algo %d\n", nand
->ecc
.algo
);
1347 static u64 ar934x_nfc_dma_mask
= DMA_BIT_MASK(32);
1349 static void ar934x_nfc_cmd_ctrl(struct nand_chip
*chip
, int dat
,
1352 WARN_ON(dat
!= NAND_CMD_NONE
);
1355 static const struct nand_controller_ops ar934x_nfc_controller_ops
= {
1356 .attach_chip
= ar934x_nfc_attach_chip
,
1359 static int ar934x_nfc_probe(struct platform_device
*pdev
)
1361 struct ar934x_nfc
*nfc
;
1362 struct resource
*res
;
1363 struct mtd_info
*mtd
;
1364 struct nand_chip
*nand
;
1367 pdev
->dev
.dma_mask
= &ar934x_nfc_dma_mask
;
1368 pdev
->dev
.coherent_dma_mask
= DMA_BIT_MASK(32);
1370 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1372 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
1376 nfc
= devm_kzalloc(&pdev
->dev
, sizeof(struct ar934x_nfc
), GFP_KERNEL
);
1378 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
1382 nfc
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1383 if (IS_ERR(nfc
->base
)) {
1384 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
1385 return PTR_ERR(nfc
->base
);
1388 nfc
->irq
= platform_get_irq(pdev
, 0);
1390 dev_err(&pdev
->dev
, "no IRQ resource specified\n");
1394 init_waitqueue_head(&nfc
->irq_waitq
);
1395 ret
= devm_request_irq(&pdev
->dev
, nfc
->irq
, ar934x_nfc_irq_handler
,
1396 0, AR934X_NFC_DRIVER_NAME
, nfc
);
1398 dev_err(&pdev
->dev
, "devm_request_irq failed, err:%d\n", ret
);
1402 nfc
->rst
= devm_reset_control_get(&pdev
->dev
, "nand");
1403 if (IS_ERR(nfc
->rst
)) {
1404 dev_err(&pdev
->dev
, "Failed to get reset\n");
1405 return PTR_ERR(nfc
->rst
);
1408 nfc
->parent
= &pdev
->dev
;
1409 nfc
->swap_dma
= of_property_read_bool(pdev
->dev
.of_node
,
1410 "qca,nand-swap-dma");
1412 nand
= &nfc
->nand_chip
;
1413 mtd
= nand_to_mtd(nand
);
1415 mtd
->owner
= THIS_MODULE
;
1416 mtd
->dev
.parent
= &pdev
->dev
;
1417 mtd
->name
= AR934X_NFC_DRIVER_NAME
;
1419 nand_set_controller_data(nand
, nfc
);
1420 nand_set_flash_node(nand
, pdev
->dev
.of_node
);
1421 nand
->legacy
.chip_delay
= 25;
1422 nand
->legacy
.dev_ready
= ar934x_nfc_dev_ready
;
1423 nand
->legacy
.cmdfunc
= ar934x_nfc_cmdfunc
;
1424 nand
->legacy
.cmd_ctrl
= ar934x_nfc_cmd_ctrl
; /* dummy */
1425 nand
->legacy
.read_byte
= ar934x_nfc_read_byte
;
1426 nand
->legacy
.write_buf
= ar934x_nfc_write_buf
;
1427 nand
->legacy
.read_buf
= ar934x_nfc_read_buf
;
1428 nand
->ecc
.engine_type
= NAND_ECC_ENGINE_TYPE_ON_HOST
; /* default */
1430 platform_set_drvdata(pdev
, nfc
);
1432 ret
= ar934x_nfc_alloc_buf(nfc
, AR934X_NFC_ID_BUF_SIZE
);
1436 ret
= ar934x_nfc_hw_init(nfc
);
1438 dev_err(&pdev
->dev
, "hardware init failed, err:%d\n", ret
);
1442 nand
->legacy
.dummy_controller
.ops
= &ar934x_nfc_controller_ops
;
1443 ret
= nand_scan(nand
, 1);
1445 dev_err(&pdev
->dev
, "nand_scan failed, err:%d\n", ret
);
1449 ret
= mtd_device_register(mtd
, NULL
, 0);
1451 dev_err(&pdev
->dev
, "unable to register mtd, err:%d\n", ret
);
1458 ar934x_nfc_free_buf(nfc
);
1462 static int ar934x_nfc_remove(struct platform_device
*pdev
)
1464 struct ar934x_nfc
*nfc
;
1466 nfc
= platform_get_drvdata(pdev
);
1468 mtd_device_unregister(nand_to_mtd(&nfc
->nand_chip
));
1469 nand_cleanup(&nfc
->nand_chip
);
1470 ar934x_nfc_free_buf(nfc
);
1476 static const struct of_device_id ar934x_nfc_match
[] = {
1477 { .compatible
= "qca," AR934X_NFC_DRIVER_NAME
},
1481 MODULE_DEVICE_TABLE(of
, ar934x_nfc_match
);
1483 static struct platform_driver ar934x_nfc_driver
= {
1484 .probe
= ar934x_nfc_probe
,
1485 .remove
= ar934x_nfc_remove
,
1487 .name
= AR934X_NFC_DRIVER_NAME
,
1488 .owner
= THIS_MODULE
,
1489 .of_match_table
= ar934x_nfc_match
,
1493 module_platform_driver(ar934x_nfc_driver
);
1495 MODULE_LICENSE("GPL v2");
1496 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1497 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1498 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME
);