2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/version.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
23 #include <linux/of_device.h>
24 #include <linux/reset.h>
26 #define AR934X_NFC_DRIVER_NAME "ar934x-nand"
28 #define AR934X_NFC_REG_CMD 0x00
29 #define AR934X_NFC_REG_CTRL 0x04
30 #define AR934X_NFC_REG_STATUS 0x08
31 #define AR934X_NFC_REG_INT_MASK 0x0c
32 #define AR934X_NFC_REG_INT_STATUS 0x10
33 #define AR934X_NFC_REG_ECC_CTRL 0x14
34 #define AR934X_NFC_REG_ECC_OFFSET 0x18
35 #define AR934X_NFC_REG_ADDR0_0 0x1c
36 #define AR934X_NFC_REG_ADDR0_1 0x24
37 #define AR934X_NFC_REG_ADDR1_0 0x20
38 #define AR934X_NFC_REG_ADDR1_1 0x28
39 #define AR934X_NFC_REG_SPARE_SIZE 0x30
40 #define AR934X_NFC_REG_PROTECT 0x38
41 #define AR934X_NFC_REG_LOOKUP_EN 0x40
42 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
43 #define AR934X_NFC_REG_DMA_ADDR 0x64
44 #define AR934X_NFC_REG_DMA_COUNT 0x68
45 #define AR934X_NFC_REG_DMA_CTRL 0x6c
46 #define AR934X_NFC_REG_MEM_CTRL 0x80
47 #define AR934X_NFC_REG_DATA_SIZE 0x84
48 #define AR934X_NFC_REG_READ_STATUS 0x88
49 #define AR934X_NFC_REG_TIME_SEQ 0x8c
50 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
51 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
52 #define AR934X_NFC_REG_FIFO_DATA 0x98
53 #define AR934X_NFC_REG_TIME_MODE 0x9c
54 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
55 #define AR934X_NFC_REG_FIFO_INIT 0xb0
56 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
58 #define AR934X_NFC_CMD_CMD_SEQ_S 0
59 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
60 #define AR934X_NFC_CMD_SEQ_1C 0x00
61 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
62 #define AR934X_NFC_CMD_SEQ_12 0x0c
63 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
64 #define AR934X_NFC_CMD_SEQ_S 0x24
65 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
66 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
67 #define AR934X_NFC_CMD_SEQ_18 0x32
68 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
69 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
70 #define AR934X_NFC_CMD_ADDR_SEL_0 0
71 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
72 #define AR934X_NFC_CMD_CMD0_S 8
73 #define AR934X_NFC_CMD_CMD0_M 0xff
74 #define AR934X_NFC_CMD_CMD1_S 16
75 #define AR934X_NFC_CMD_CMD1_M 0xff
76 #define AR934X_NFC_CMD_CMD2_S 24
77 #define AR934X_NFC_CMD_CMD2_M 0xff
79 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
80 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
81 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
82 #define AR934X_NFC_CTRL_INT_EN BIT(4)
83 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
86 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
87 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
88 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
89 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
90 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
91 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
92 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
93 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
94 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
95 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
96 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
97 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
98 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
99 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
100 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
101 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
102 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
103 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
104 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
105 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
106 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
107 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
108 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
109 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
110 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
112 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
113 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
114 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
115 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
119 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
120 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
121 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
122 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
123 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
124 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
126 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
127 #define AR934X_NFC_INT_CMD_END BIT(1)
129 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
130 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
131 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
132 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
133 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
137 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
138 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
139 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
140 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
141 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
142 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
143 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
145 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
147 /* default timing values */
148 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
149 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
150 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
152 #define AR934X_NFC_ID_BUF_SIZE 8
153 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
154 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
155 #define AR934X_NFC_DONE_TIMEOUT 1000
156 #define AR934X_NFC_DMA_RETRIES 20
158 #define AR934X_NFC_USE_IRQ true
159 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
161 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
163 #undef AR934X_NFC_DEBUG_DATA
164 #undef AR934X_NFC_DEBUG
167 struct mtd_partition
;
171 struct nand_chip nand_chip
;
172 struct device
*parent
;
176 wait_queue_head_t irq_waitq
;
178 bool spurious_irq_expected
;
188 unsigned int addr_count0
;
189 unsigned int addr_count1
;
193 unsigned int buf_size
;
198 int erase1_page_addr
;
200 int rndout_page_addr
;
207 struct reset_control
*rst
;
210 static inline __printf(2, 3)
211 void _nfc_dbg(struct ar934x_nfc
*nfc
, const char *fmt
, ...)
215 #ifdef AR934X_NFC_DEBUG
216 #define nfc_dbg(_nfc, fmt, ...) \
217 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
219 #define nfc_dbg(_nfc, fmt, ...) \
220 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
221 #endif /* AR934X_NFC_DEBUG */
223 #ifdef AR934X_NFC_DEBUG_DATA
224 static void nfc_debug_data(const char *label
, void *data
, int len
)
226 print_hex_dump(KERN_WARNING
, label
, DUMP_PREFIX_OFFSET
, 16, 1,
230 static inline void nfc_debug_data(const char *label
, void *data
, int len
) {}
231 #endif /* AR934X_NFC_DEBUG_DATA */
233 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
);
235 static inline bool is_all_ff(u8
*buf
, int len
)
238 if (buf
[len
] != 0xff)
244 static inline void ar934x_nfc_wr(struct ar934x_nfc
*nfc
, unsigned reg
, u32 val
)
246 __raw_writel(val
, nfc
->base
+ reg
);
249 static inline u32
ar934x_nfc_rr(struct ar934x_nfc
*nfc
, unsigned reg
)
251 return __raw_readl(nfc
->base
+ reg
);
254 static inline struct ar934x_nfc
*mtd_to_ar934x_nfc(struct mtd_info
*mtd
)
256 struct nand_chip
*chip
= mtd_to_nand(mtd
);
258 return container_of(chip
, struct ar934x_nfc
, nand_chip
);
261 static struct mtd_info
*ar934x_nfc_to_mtd(struct ar934x_nfc
*nfc
)
263 return nand_to_mtd(&nfc
->nand_chip
);
266 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc
*nfc
)
268 return AR934X_NFC_USE_IRQ
;
271 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc
*nfc
, u32 cmd_reg
)
275 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CMD
, cmd_reg
);
277 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_CMD
);
280 static bool __ar934x_nfc_dev_ready(struct ar934x_nfc
*nfc
)
284 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
);
285 return (status
& 0xff) == 0xff;
288 static inline bool __ar934x_nfc_is_dma_ready(struct ar934x_nfc
*nfc
)
292 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
);
293 return (status
& AR934X_NFC_DMA_CTRL_DMA_READY
) != 0;
296 static int ar934x_nfc_wait_dev_ready(struct ar934x_nfc
*nfc
)
298 unsigned long timeout
;
300 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
);
302 if (__ar934x_nfc_dev_ready(nfc
))
304 } while time_before(jiffies
, timeout
);
306 nfc_dbg(nfc
, "timeout waiting for device ready, status:%08x int:%08x\n",
307 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
),
308 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
));
312 static int ar934x_nfc_wait_dma_ready(struct ar934x_nfc
*nfc
)
314 unsigned long timeout
;
316 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT
);
318 if (__ar934x_nfc_is_dma_ready(nfc
))
320 } while time_before(jiffies
, timeout
);
322 nfc_dbg(nfc
, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
323 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
));
327 static int ar934x_nfc_wait_irq(struct ar934x_nfc
*nfc
)
332 timeout
= wait_event_timeout(nfc
->irq_waitq
,
333 (nfc
->irq_status
& AR934X_NFC_IRQ_MASK
) != 0,
334 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
));
338 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, 0);
339 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
341 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
344 "timeout waiting for interrupt, status:%08x\n",
353 static int ar934x_nfc_wait_done(struct ar934x_nfc
*nfc
)
357 if (ar934x_nfc_use_irq(nfc
))
358 ret
= ar934x_nfc_wait_irq(nfc
);
360 ret
= ar934x_nfc_wait_dev_ready(nfc
);
365 return ar934x_nfc_wait_dma_ready(nfc
);
368 static int ar934x_nfc_alloc_buf(struct ar934x_nfc
*nfc
, unsigned size
)
370 nfc
->buf
= dma_alloc_coherent(nfc
->parent
, size
,
371 &nfc
->buf_dma
, GFP_KERNEL
);
372 if (nfc
->buf
== NULL
) {
373 dev_err(nfc
->parent
, "no memory for DMA buffer\n");
377 nfc
->buf_size
= size
;
378 nfc_dbg(nfc
, "buf:%p size:%u\n", nfc
->buf
, nfc
->buf_size
);
383 static void ar934x_nfc_free_buf(struct ar934x_nfc
*nfc
)
385 dma_free_coherent(nfc
->parent
, nfc
->buf_size
, nfc
->buf
, nfc
->buf_dma
);
388 static void ar934x_nfc_get_addr(struct ar934x_nfc
*nfc
, int column
,
389 int page_addr
, u32
*addr0
, u32
*addr1
)
398 a0
= (page_addr
& 0xffff) << 16;
399 a1
= (page_addr
>> 16) & 0xf;
400 } else if (page_addr
!= -1) {
401 /* SEQIN, READ0, etc.. */
403 /* TODO: handle 16bit bus width */
404 if (nfc
->small_page
) {
406 a0
|= (page_addr
& 0xff) << 8;
407 a0
|= ((page_addr
>> 8) & 0xff) << 16;
408 a0
|= ((page_addr
>> 16) & 0xff) << 24;
410 a0
= column
& 0x0FFF;
411 a0
|= (page_addr
& 0xffff) << 16;
413 if (nfc
->addr_count0
> 4)
414 a1
= (page_addr
>> 16) & 0xf;
422 static void ar934x_nfc_send_cmd(struct ar934x_nfc
*nfc
, unsigned command
)
426 cmd_reg
= AR934X_NFC_CMD_INPUT_SEL_SIU
| AR934X_NFC_CMD_ADDR_SEL_0
|
427 AR934X_NFC_CMD_SEQ_1C
;
428 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
430 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
431 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
433 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
434 ar934x_nfc_wait_dev_ready(nfc
);
437 static int ar934x_nfc_do_rw_command(struct ar934x_nfc
*nfc
, int column
,
438 int page_addr
, int len
, u32 cmd_reg
,
439 u32 ctrl_reg
, bool write
)
449 if (WARN_ON(len
> nfc
->buf_size
))
450 dev_err(nfc
->parent
, "len=%d > buf_size=%d", len
,
454 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE
;
457 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_READ
;
458 dir
= DMA_FROM_DEVICE
;
461 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
463 dma_ctrl
|= AR934X_NFC_DMA_CTRL_DMA_START
|
464 (AR934X_NFC_DMA_CTRL_DMA_BURST_3
<<
465 AR934X_NFC_DMA_CTRL_DMA_BURST_S
);
467 cmd_reg
|= AR934X_NFC_CMD_INPUT_SEL_DMA
| AR934X_NFC_CMD_ADDR_SEL_0
;
468 ctrl_reg
|= AR934X_NFC_CTRL_INT_EN
;
470 nfc_dbg(nfc
, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
471 (write
) ? "write" : "read",
472 addr0
, addr1
, len
, cmd_reg
, dma_ctrl
, ctrl_reg
);
475 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
476 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
477 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
478 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR
, nfc
->buf_dma
);
479 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_COUNT
, len
);
480 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DATA_SIZE
, len
);
481 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
482 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_CTRL
, dma_ctrl
);
483 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_CTRL
, nfc
->ecc_ctrl_reg
);
484 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_OFFSET
, nfc
->ecc_offset_reg
);
486 if (ar934x_nfc_use_irq(nfc
)) {
487 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
,
488 AR934X_NFC_IRQ_MASK
);
490 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
493 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
494 err
= ar934x_nfc_wait_done(nfc
);
496 dev_dbg(nfc
->parent
, "%s operation stuck at page %d\n",
497 (write
) ? "write" : "read", page_addr
);
499 ar934x_nfc_restart(nfc
);
500 if (retries
++ < AR934X_NFC_DMA_RETRIES
)
503 dev_err(nfc
->parent
, "%s operation failed on page %d\n",
504 (write
) ? "write" : "read", page_addr
);
510 static int ar934x_nfc_send_readid(struct ar934x_nfc
*nfc
, unsigned command
)
515 nfc_dbg(nfc
, "readid, cmd:%02x\n", command
);
517 cmd_reg
= AR934X_NFC_CMD_SEQ_1C1AXR
;
518 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
520 err
= ar934x_nfc_do_rw_command(nfc
, -1, -1, AR934X_NFC_ID_BUF_SIZE
,
521 cmd_reg
, nfc
->ctrl_reg
, false);
523 nfc_debug_data("[id] ", nfc
->buf
, AR934X_NFC_ID_BUF_SIZE
);
528 static int ar934x_nfc_send_read(struct ar934x_nfc
*nfc
, unsigned command
,
529 int column
, int page_addr
, int len
)
534 nfc_dbg(nfc
, "read, column=%d page=%d len=%d\n",
535 column
, page_addr
, len
);
537 cmd_reg
= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
539 if (nfc
->small_page
) {
540 cmd_reg
|= AR934X_NFC_CMD_SEQ_18
;
542 cmd_reg
|= NAND_CMD_READSTART
<< AR934X_NFC_CMD_CMD1_S
;
543 cmd_reg
|= AR934X_NFC_CMD_SEQ_1C5A1CXR
;
546 err
= ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
547 cmd_reg
, nfc
->ctrl_reg
, false);
549 nfc_debug_data("[data] ", nfc
->buf
, len
);
554 static void ar934x_nfc_send_erase(struct ar934x_nfc
*nfc
, unsigned command
,
555 int column
, int page_addr
)
561 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
563 ctrl_reg
= nfc
->ctrl_reg
;
564 if (nfc
->small_page
) {
565 /* override number of address cycles for the erase command */
566 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M
<<
567 AR934X_NFC_CTRL_ADDR_CYCLE0_S
);
568 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M
<<
569 AR934X_NFC_CTRL_ADDR_CYCLE1_S
);
570 ctrl_reg
&= ~(AR934X_NFC_CTRL_SMALL_PAGE
);
571 ctrl_reg
|= (nfc
->addr_count0
+ 1) <<
572 AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
575 cmd_reg
= NAND_CMD_ERASE1
<< AR934X_NFC_CMD_CMD0_S
;
576 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
577 cmd_reg
|= AR934X_NFC_CMD_SEQ_ERASE
;
579 nfc_dbg(nfc
, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
580 page_addr
, addr0
, addr1
, cmd_reg
, ctrl_reg
);
582 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
583 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
584 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
585 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
587 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
588 ar934x_nfc_wait_dev_ready(nfc
);
591 static int ar934x_nfc_send_write(struct ar934x_nfc
*nfc
, unsigned command
,
592 int column
, int page_addr
, int len
)
596 nfc_dbg(nfc
, "write, column=%d page=%d len=%d\n",
597 column
, page_addr
, len
);
599 nfc_debug_data("[data] ", nfc
->buf
, len
);
601 cmd_reg
= NAND_CMD_SEQIN
<< AR934X_NFC_CMD_CMD0_S
;
602 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
603 cmd_reg
|= AR934X_NFC_CMD_SEQ_12
;
605 return ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
606 cmd_reg
, nfc
->ctrl_reg
, true);
609 static void ar934x_nfc_read_status(struct ar934x_nfc
*nfc
)
614 cmd_reg
= NAND_CMD_STATUS
<< AR934X_NFC_CMD_CMD0_S
;
615 cmd_reg
|= AR934X_NFC_CMD_SEQ_S
;
617 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
618 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
620 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
621 ar934x_nfc_wait_dev_ready(nfc
);
623 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_READ_STATUS
);
625 nfc_dbg(nfc
, "read status, cmd:%08x status:%02x\n",
626 cmd_reg
, (status
& 0xff));
629 nfc
->buf
[0 ^ 3] = status
;
631 nfc
->buf
[0] = status
;
634 static void ar934x_nfc_cmdfunc(struct nand_chip
*nand
, unsigned int command
,
635 int column
, int page_addr
)
637 struct mtd_info
*mtd
= nand_to_mtd(nand
);
638 struct ar934x_nfc
*nfc
= nand
->priv
;
640 nfc
->read_id
= false;
641 if (command
!= NAND_CMD_PAGEPROG
)
646 ar934x_nfc_send_cmd(nfc
, command
);
649 case NAND_CMD_READID
:
651 ar934x_nfc_send_readid(nfc
, command
);
656 if (nfc
->small_page
) {
657 ar934x_nfc_send_read(nfc
, command
, column
, page_addr
,
658 mtd
->writesize
+ mtd
->oobsize
);
660 ar934x_nfc_send_read(nfc
, command
, 0, page_addr
,
661 mtd
->writesize
+ mtd
->oobsize
);
662 nfc
->buf_index
= column
;
663 nfc
->rndout_page_addr
= page_addr
;
664 nfc
->rndout_read_cmd
= command
;
668 case NAND_CMD_READOOB
:
670 ar934x_nfc_send_read(nfc
, NAND_CMD_READOOB
,
674 ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
,
675 mtd
->writesize
, page_addr
,
679 case NAND_CMD_RNDOUT
:
680 if (WARN_ON(nfc
->small_page
))
683 /* emulate subpage read */
684 ar934x_nfc_send_read(nfc
, nfc
->rndout_read_cmd
, 0,
685 nfc
->rndout_page_addr
,
686 mtd
->writesize
+ mtd
->oobsize
);
687 nfc
->buf_index
= column
;
690 case NAND_CMD_ERASE1
:
691 nfc
->erase1_page_addr
= page_addr
;
694 case NAND_CMD_ERASE2
:
695 ar934x_nfc_send_erase(nfc
, command
, -1, nfc
->erase1_page_addr
);
698 case NAND_CMD_STATUS
:
699 ar934x_nfc_read_status(nfc
);
703 if (nfc
->small_page
) {
704 /* output read command */
705 if (column
>= mtd
->writesize
) {
706 column
-= mtd
->writesize
;
707 nfc
->seqin_read_cmd
= NAND_CMD_READOOB
;
708 } else if (column
< 256) {
709 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
712 nfc
->seqin_read_cmd
= NAND_CMD_READ1
;
715 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
717 nfc
->seqin_column
= column
;
718 nfc
->seqin_page_addr
= page_addr
;
721 case NAND_CMD_PAGEPROG
:
722 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
723 /* the data is already written */
728 ar934x_nfc_send_cmd(nfc
, nfc
->seqin_read_cmd
);
730 ar934x_nfc_send_write(nfc
, command
, nfc
->seqin_column
,
731 nfc
->seqin_page_addr
,
737 "unsupported command: %x, column:%d page_addr=%d\n",
738 command
, column
, page_addr
);
743 static int ar934x_nfc_dev_ready(struct nand_chip
*chip
)
745 struct ar934x_nfc
*nfc
= chip
->priv
;
747 return __ar934x_nfc_dev_ready(nfc
);
750 static u8
ar934x_nfc_read_byte(struct nand_chip
*chip
)
752 struct ar934x_nfc
*nfc
= chip
->priv
;
755 WARN_ON(nfc
->buf_index
>= nfc
->buf_size
);
757 if (nfc
->swap_dma
|| nfc
->read_id
)
758 data
= nfc
->buf
[nfc
->buf_index
^ 3];
760 data
= nfc
->buf
[nfc
->buf_index
];
767 static void ar934x_nfc_write_buf(struct nand_chip
*chip
, const u8
*buf
, int len
)
769 struct ar934x_nfc
*nfc
= chip
->priv
;
772 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
775 for (i
= 0; i
< len
; i
++) {
776 nfc
->buf
[nfc
->buf_index
^ 3] = buf
[i
];
780 for (i
= 0; i
< len
; i
++) {
781 nfc
->buf
[nfc
->buf_index
] = buf
[i
];
787 static void ar934x_nfc_read_buf(struct nand_chip
*chip
, u8
*buf
, int len
)
789 struct ar934x_nfc
*nfc
= chip
->priv
;
793 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
795 buf_index
= nfc
->buf_index
;
797 if (nfc
->swap_dma
|| nfc
->read_id
) {
798 for (i
= 0; i
< len
; i
++) {
799 buf
[i
] = nfc
->buf
[buf_index
^ 3];
803 for (i
= 0; i
< len
; i
++) {
804 buf
[i
] = nfc
->buf
[buf_index
];
809 nfc
->buf_index
= buf_index
;
812 static inline void ar934x_nfc_enable_hwecc(struct ar934x_nfc
*nfc
)
814 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_ECC_EN
;
815 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
818 static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc
*nfc
)
820 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_ECC_EN
;
821 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
824 static int ar934x_nfc_read_oob(struct nand_chip
*chip
,
827 struct ar934x_nfc
*nfc
= chip
->priv
;
828 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
831 nfc_dbg(nfc
, "read_oob: page:%d\n", page
);
833 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
, page
,
838 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
843 static int ar934x_nfc_write_oob(struct nand_chip
*chip
,
846 struct ar934x_nfc
*nfc
= chip
->priv
;
847 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
848 nfc_dbg(nfc
, "write_oob: page:%d\n", page
);
850 memcpy(nfc
->buf
, chip
->oob_poi
, mtd
->oobsize
);
852 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, mtd
->writesize
,
856 static int ar934x_nfc_read_page_raw(
857 struct nand_chip
*chip
, u8
*buf
,
858 int oob_required
, int page
)
860 struct ar934x_nfc
*nfc
= chip
->priv
;
861 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
865 nfc_dbg(nfc
, "read_page_raw: page:%d oob:%d\n", page
, oob_required
);
867 len
= mtd
->writesize
;
871 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
, len
);
875 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
878 memcpy(chip
->oob_poi
, &nfc
->buf
[mtd
->writesize
], mtd
->oobsize
);
883 static int ar934x_nfc_read_page(struct nand_chip
*chip
,
884 u8
*buf
, int oob_required
, int page
)
886 struct ar934x_nfc
*nfc
= chip
->priv
;
887 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
889 int max_bitflips
= 0;
894 nfc_dbg(nfc
, "read_page: page:%d oob:%d\n", page
, oob_required
);
896 ar934x_nfc_enable_hwecc(nfc
);
897 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
,
899 ar934x_nfc_disable_hwecc(nfc
);
904 /* TODO: optimize to avoid memcpy */
905 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
907 /* read the ECC status */
908 ecc_ctrl
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_ECC_CTRL
);
909 ecc_failed
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_UNCORRECT
;
910 ecc_corrected
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_CORRECT
;
912 if (oob_required
|| ecc_failed
) {
913 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
,
919 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
924 * The hardware ECC engine reports uncorrectable errors
925 * on empty pages. Check the ECC bytes and the data. If
926 * both contains 0xff bytes only, dont report a failure.
928 * TODO: prebuild a buffer with 0xff bytes and use memcmp
929 * for better performance?
931 if (!is_all_ff(&nfc
->buf
[nfc
->ecc_oob_pos
], chip
->ecc
.total
) ||
932 !is_all_ff(buf
, mtd
->writesize
))
933 mtd
->ecc_stats
.failed
++;
934 } else if (ecc_corrected
) {
936 * The hardware does not report the exact count of the
937 * corrected bitflips, use assumptions based on the
940 if (ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_OVER
) {
942 * The number of corrected bitflips exceeds the
943 * threshold. Assume the maximum.
945 max_bitflips
= chip
->ecc
.strength
* chip
->ecc
.steps
;
947 max_bitflips
= nfc
->ecc_thres
* chip
->ecc
.steps
;
950 mtd
->ecc_stats
.corrected
+= max_bitflips
;
956 static int ar934x_nfc_write_page_raw(
957 struct nand_chip
*chip
, const u8
*buf
,
958 int oob_required
, int page
)
960 struct ar934x_nfc
*nfc
= chip
->priv
;
961 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
964 nfc_dbg(nfc
, "write_page_raw: page:%d oob:%d\n", page
, oob_required
);
966 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
967 len
= mtd
->writesize
;
970 memcpy(&nfc
->buf
[mtd
->writesize
], chip
->oob_poi
, mtd
->oobsize
);
974 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
, len
);
977 static int ar934x_nfc_write_page(struct nand_chip
*chip
,
978 const u8
*buf
, int oob_required
, int page
)
980 struct ar934x_nfc
*nfc
= chip
->priv
;
981 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
984 nfc_dbg(nfc
, "write_page: page:%d oob:%d\n", page
, oob_required
);
986 /* write OOB first */
988 !is_all_ff(chip
->oob_poi
, mtd
->oobsize
)) {
989 err
= ar934x_nfc_write_oob(chip
, page
);
994 /* TODO: optimize to avoid memcopy */
995 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
997 ar934x_nfc_enable_hwecc(nfc
);
998 err
= ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
,
1000 ar934x_nfc_disable_hwecc(nfc
);
1005 static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc
*nfc
)
1009 err
= reset_control_assert(nfc
->rst
);
1014 static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc
*nfc
)
1018 err
= reset_control_deassert(nfc
->rst
);
1023 static int ar934x_nfc_hw_init(struct ar934x_nfc
*nfc
)
1025 ar934x_nfc_hw_reset_assert(nfc
);
1026 ar934x_nfc_hw_reset_deassert(nfc
);
1029 * TODO: make it configurable via platform data or DT
1031 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIME_SEQ
,
1032 AR934X_NFC_TIME_SEQ_DEFAULT
);
1033 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_ASYN
,
1034 AR934X_NFC_TIMINGS_ASYN_DEFAULT
);
1035 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_SYN
,
1036 AR934X_NFC_TIMINGS_SYN_DEFAULT
);
1038 /* disable WP on all chips, and select chip 0 */
1039 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_MEM_CTRL
, 0xff00);
1041 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR_OFFS
, 0);
1043 /* initialize Control register */
1044 nfc
->ctrl_reg
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1045 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1047 if (nfc
->small_page
) {
1048 /* Setup generic sequence register for small page reads. */
1049 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_GEN_SEQ_CTRL
,
1050 AR934X_NFC_GENSEQ_SMALL_PAGE_READ
);
1056 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
)
1060 ctrl_reg
= nfc
->ctrl_reg
;
1061 ar934x_nfc_hw_init(nfc
);
1062 nfc
->ctrl_reg
= ctrl_reg
;
1064 ar934x_nfc_send_cmd(nfc
, NAND_CMD_RESET
);
1067 static irqreturn_t
ar934x_nfc_irq_handler(int irq
, void *data
)
1069 struct ar934x_nfc
*nfc
= data
;
1072 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1074 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
1076 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1078 status
&= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
1080 nfc_dbg(nfc
, "got IRQ, status:%08x\n", status
);
1082 nfc
->irq_status
= status
;
1083 nfc
->spurious_irq_expected
= true;
1084 wake_up(&nfc
->irq_waitq
);
1086 if (nfc
->spurious_irq_expected
)
1087 nfc
->spurious_irq_expected
= false;
1089 dev_warn(nfc
->parent
, "spurious interrupt\n");
1095 static int ar934x_nfc_init_tail(struct mtd_info
*mtd
)
1097 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1098 struct nand_chip
*chip
= &nfc
->nand_chip
;
1099 u64 chipsize
= nanddev_target_size(&chip
->base
);
1104 switch (mtd
->oobsize
) {
1108 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_SPARE_SIZE
, mtd
->oobsize
);
1112 dev_err(nfc
->parent
, "unsupported OOB size: %d bytes\n",
1117 ctrl
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1119 switch (mtd
->erasesize
/ mtd
->writesize
) {
1121 t
= AR934X_NFC_CTRL_BLOCK_SIZE_32
;
1125 t
= AR934X_NFC_CTRL_BLOCK_SIZE_64
;
1129 t
= AR934X_NFC_CTRL_BLOCK_SIZE_128
;
1133 t
= AR934X_NFC_CTRL_BLOCK_SIZE_256
;
1137 dev_err(nfc
->parent
, "unsupported block size: %u\n",
1138 mtd
->erasesize
/ mtd
->writesize
);
1142 ctrl
|= t
<< AR934X_NFC_CTRL_BLOCK_SIZE_S
;
1144 switch (mtd
->writesize
) {
1146 nfc
->small_page
= 1;
1147 t
= AR934X_NFC_CTRL_PAGE_SIZE_256
;
1151 nfc
->small_page
= 1;
1152 t
= AR934X_NFC_CTRL_PAGE_SIZE_512
;
1156 t
= AR934X_NFC_CTRL_PAGE_SIZE_1024
;
1160 t
= AR934X_NFC_CTRL_PAGE_SIZE_2048
;
1164 t
= AR934X_NFC_CTRL_PAGE_SIZE_4096
;
1168 t
= AR934X_NFC_CTRL_PAGE_SIZE_8192
;
1172 t
= AR934X_NFC_CTRL_PAGE_SIZE_16384
;
1176 dev_err(nfc
->parent
, "unsupported write size: %d bytes\n",
1181 ctrl
|= t
<< AR934X_NFC_CTRL_PAGE_SIZE_S
;
1183 if (nfc
->small_page
) {
1184 ctrl
|= AR934X_NFC_CTRL_SMALL_PAGE
;
1186 if (chipsize
> (32 << 20)) {
1187 nfc
->addr_count0
= 4;
1188 nfc
->addr_count1
= 3;
1189 } else if (chipsize
> (2 << 16)) {
1190 nfc
->addr_count0
= 3;
1191 nfc
->addr_count1
= 2;
1193 nfc
->addr_count0
= 2;
1194 nfc
->addr_count1
= 1;
1197 if (chipsize
> (128 << 20)) {
1198 nfc
->addr_count0
= 5;
1199 nfc
->addr_count1
= 3;
1200 } else if (chipsize
> (8 << 16)) {
1201 nfc
->addr_count0
= 4;
1202 nfc
->addr_count1
= 2;
1204 nfc
->addr_count0
= 3;
1205 nfc
->addr_count1
= 1;
1209 ctrl
|= nfc
->addr_count0
<< AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
1210 ctrl
|= nfc
->addr_count1
<< AR934X_NFC_CTRL_ADDR_CYCLE1_S
;
1212 nfc
->ctrl_reg
= ctrl
;
1213 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1215 ar934x_nfc_free_buf(nfc
);
1216 err
= ar934x_nfc_alloc_buf(nfc
, mtd
->writesize
+ mtd
->oobsize
);
1221 static int ar934x_nfc_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1222 struct mtd_oob_region
*oobregion
)
1227 oobregion
->offset
= 20;
1228 oobregion
->length
= 28;
1233 static int ar934x_nfc_ooblayout_free(struct mtd_info
*mtd
, int section
,
1234 struct mtd_oob_region
*oobregion
)
1238 oobregion
->offset
= 4;
1239 oobregion
->length
= 16;
1242 oobregion
->offset
= 48;
1243 oobregion
->length
= 16;
1250 static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops
= {
1251 .ecc
= ar934x_nfc_ooblayout_ecc
,
1252 .free
= ar934x_nfc_ooblayout_free
,
1255 static int ar934x_nfc_setup_hwecc(struct ar934x_nfc
*nfc
)
1257 struct nand_chip
*nand
= &nfc
->nand_chip
;
1258 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1261 struct mtd_oob_region oobregion
;
1263 switch (mtd
->writesize
) {
1266 * Writing a subpage separately is not supported, because
1267 * the controller only does ECC on full-page accesses.
1269 nand
->options
= NAND_NO_SUBPAGE_WRITE
;
1271 nand
->ecc
.size
= 512;
1272 nand
->ecc
.bytes
= 7;
1273 nand
->ecc
.strength
= 4;
1274 mtd_set_ooblayout(mtd
, &ar934x_nfc_ecclayout_ops
);
1278 dev_err(nfc
->parent
,
1279 "hardware ECC is not available for %d byte pages\n",
1284 BUG_ON(!mtd
->ooblayout
->ecc
);
1286 switch (nand
->ecc
.strength
) {
1288 ecc_cap
= AR934X_NFC_ECC_CTRL_ECC_CAP_4
;
1293 dev_err(nfc
->parent
, "unsupported ECC strength %u\n",
1294 nand
->ecc
.strength
);
1298 nfc
->ecc_thres
= ecc_thres
;
1299 mtd
->ooblayout
->ecc(mtd
, 0, &oobregion
);
1300 nfc
->ecc_oob_pos
= oobregion
.offset
;
1302 nfc
->ecc_ctrl_reg
= ecc_cap
<< AR934X_NFC_ECC_CTRL_ECC_CAP_S
;
1303 nfc
->ecc_ctrl_reg
|= ecc_thres
<< AR934X_NFC_ECC_CTRL_ERR_THRES_S
;
1305 nfc
->ecc_offset_reg
= mtd
->writesize
+ nfc
->ecc_oob_pos
;
1307 nand
->ecc
.read_page
= ar934x_nfc_read_page
;
1308 nand
->ecc
.read_page_raw
= ar934x_nfc_read_page_raw
;
1309 nand
->ecc
.write_page
= ar934x_nfc_write_page
;
1310 nand
->ecc
.write_page_raw
= ar934x_nfc_write_page_raw
;
1311 nand
->ecc
.read_oob
= ar934x_nfc_read_oob
;
1312 nand
->ecc
.write_oob
= ar934x_nfc_write_oob
;
1317 static int ar934x_nfc_attach_chip(struct nand_chip
*nand
)
1319 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1320 struct ar934x_nfc
*nfc
= nand_get_controller_data(nand
);
1321 struct device
*dev
= mtd
->dev
.parent
;
1324 ret
= ar934x_nfc_init_tail(mtd
);
1328 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
1329 ret
= ar934x_nfc_setup_hwecc(nfc
);
1332 } else if (nand
->ecc
.mode
!= NAND_ECC_SOFT
) {
1333 dev_err(dev
, "unknown ECC mode %d\n", nand
->ecc
.mode
);
1335 } else if ((nand
->ecc
.algo
!= NAND_ECC_BCH
) &&
1336 (nand
->ecc
.algo
!= NAND_ECC_HAMMING
)) {
1337 dev_err(dev
, "unknown software ECC algo %d\n", nand
->ecc
.algo
);
1344 static u64 ar934x_nfc_dma_mask
= DMA_BIT_MASK(32);
1346 static void ar934x_nfc_cmd_ctrl(struct nand_chip
*chip
, int dat
,
1349 WARN_ON(dat
!= NAND_CMD_NONE
);
1352 static const struct nand_controller_ops ar934x_nfc_controller_ops
= {
1353 .attach_chip
= ar934x_nfc_attach_chip
,
1356 static int ar934x_nfc_probe(struct platform_device
*pdev
)
1358 struct ar934x_nfc
*nfc
;
1359 struct resource
*res
;
1360 struct mtd_info
*mtd
;
1361 struct nand_chip
*nand
;
1364 pdev
->dev
.dma_mask
= &ar934x_nfc_dma_mask
;
1365 pdev
->dev
.coherent_dma_mask
= DMA_BIT_MASK(32);
1367 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1369 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
1373 nfc
= devm_kzalloc(&pdev
->dev
, sizeof(struct ar934x_nfc
), GFP_KERNEL
);
1375 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
1379 nfc
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1380 if (IS_ERR(nfc
->base
)) {
1381 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
1382 return PTR_ERR(nfc
->base
);
1385 nfc
->irq
= platform_get_irq(pdev
, 0);
1387 dev_err(&pdev
->dev
, "no IRQ resource specified\n");
1391 init_waitqueue_head(&nfc
->irq_waitq
);
1392 ret
= devm_request_irq(&pdev
->dev
, nfc
->irq
, ar934x_nfc_irq_handler
,
1393 0, AR934X_NFC_DRIVER_NAME
, nfc
);
1395 dev_err(&pdev
->dev
, "devm_request_irq failed, err:%d\n", ret
);
1399 nfc
->rst
= devm_reset_control_get(&pdev
->dev
, "nand");
1400 if (IS_ERR(nfc
->rst
)) {
1401 dev_err(&pdev
->dev
, "Failed to get reset\n");
1402 return PTR_ERR(nfc
->rst
);
1405 nfc
->parent
= &pdev
->dev
;
1406 nfc
->swap_dma
= of_property_read_bool(pdev
->dev
.of_node
,
1407 "qca,nand-swap-dma");
1409 nand
= &nfc
->nand_chip
;
1410 mtd
= nand_to_mtd(nand
);
1412 mtd
->owner
= THIS_MODULE
;
1413 mtd
->dev
.parent
= &pdev
->dev
;
1414 mtd
->name
= AR934X_NFC_DRIVER_NAME
;
1416 nand_set_controller_data(nand
, nfc
);
1417 nand_set_flash_node(nand
, pdev
->dev
.of_node
);
1418 nand
->legacy
.chip_delay
= 25;
1419 nand
->legacy
.dev_ready
= ar934x_nfc_dev_ready
;
1420 nand
->legacy
.cmdfunc
= ar934x_nfc_cmdfunc
;
1421 nand
->legacy
.cmd_ctrl
= ar934x_nfc_cmd_ctrl
; /* dummy */
1422 nand
->legacy
.read_byte
= ar934x_nfc_read_byte
;
1423 nand
->legacy
.write_buf
= ar934x_nfc_write_buf
;
1424 nand
->legacy
.read_buf
= ar934x_nfc_read_buf
;
1425 nand
->ecc
.mode
= NAND_ECC_HW
; /* default */
1427 platform_set_drvdata(pdev
, nfc
);
1429 ret
= ar934x_nfc_alloc_buf(nfc
, AR934X_NFC_ID_BUF_SIZE
);
1433 ret
= ar934x_nfc_hw_init(nfc
);
1435 dev_err(&pdev
->dev
, "hardware init failed, err:%d\n", ret
);
1439 nand
->legacy
.dummy_controller
.ops
= &ar934x_nfc_controller_ops
;
1440 ret
= nand_scan(nand
, 1);
1442 dev_err(&pdev
->dev
, "nand_scan failed, err:%d\n", ret
);
1446 ret
= mtd_device_register(mtd
, NULL
, 0);
1448 dev_err(&pdev
->dev
, "unable to register mtd, err:%d\n", ret
);
1455 ar934x_nfc_free_buf(nfc
);
1459 static int ar934x_nfc_remove(struct platform_device
*pdev
)
1461 struct ar934x_nfc
*nfc
;
1463 nfc
= platform_get_drvdata(pdev
);
1465 nand_release(&nfc
->nand_chip
);
1466 ar934x_nfc_free_buf(nfc
);
1472 static const struct of_device_id ar934x_nfc_match
[] = {
1473 { .compatible
= "qca," AR934X_NFC_DRIVER_NAME
},
1477 MODULE_DEVICE_TABLE(of
, ar934x_nfc_match
);
1479 static struct platform_driver ar934x_nfc_driver
= {
1480 .probe
= ar934x_nfc_probe
,
1481 .remove
= ar934x_nfc_remove
,
1483 .name
= AR934X_NFC_DRIVER_NAME
,
1484 .owner
= THIS_MODULE
,
1485 .of_match_table
= ar934x_nfc_match
,
1489 module_platform_driver(ar934x_nfc_driver
);
1491 MODULE_LICENSE("GPL v2");
1492 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1493 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1494 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME
);