target/linux/ath79/files/drivers/mtd/nand/raw/rb91x_nand.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  MikroTik RB91x NAND flash driver
   4  *
   5  *  Main part is copied from original driver written by Gabor Juhos.
   6  *
   7  *  Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
   8  */
   9
  10 /*
  11  * WARNING: to speed up NAND reading/writing we are working with SoC GPIO
  12  * controller registers directly -- not through standard GPIO API.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mtd/rawnand.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/version.h>
  23 #include <linux/of_platform.h>
  24
  25 #include <asm/mach-ath79/ar71xx_regs.h>
  26
  27 /* Bit masks for NAND data lines in ath79 gpio 32-bit register */
  28 #define RB91X_NAND_NRW_BIT BIT(12)
  29 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) \
  30                             | BIT(13) | BIT(14) | BIT(15))
  31 #define RB91X_NAND_LOW_DATA_MASK        0x1f
  32 #define RB91X_NAND_HIGH_DATA_MASK       0xe0
  33 #define RB91X_NAND_HIGH_DATA_SHIFT      8
  34
  35 enum rb91x_nand_gpios {
  36         RB91X_NAND_READ,/* Read */
  37         RB91X_NAND_RDY, /* NAND Ready */
  38         RB91X_NAND_NCE, /* Chip Enable. Active low */
  39         RB91X_NAND_CLE, /* Command Latch Enable */
  40         RB91X_NAND_ALE, /* Address Latch Enable */
  41         RB91X_NAND_NRW, /* Read/Write. Active low */
  42         RB91X_NAND_NLE, /* Latch Enable. Active low */
  43         RB91X_NAND_PDIS, /* Reset Key Poll Disable. Active high */
  44
  45         RB91X_NAND_GPIOS,
  46 };
  47
  48 struct rb91x_nand_drvdata {
  49         struct nand_chip chip;
  50         struct device *dev;
  51         struct gpio_desc **gpio;
  52         void __iomem *ath79_gpio_base;
  53 };
  54
  55 static inline void rb91x_nand_latch_lock(struct rb91x_nand_drvdata *drvdata,
  56                                          int lock)
  57 {
  58         gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NLE], lock);
  59 }
  60
  61 static inline void rb91x_nand_rst_key_poll_disable(struct rb91x_nand_drvdata *drvdata,
  62                                                    int disable)
  63 {
  64         gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_PDIS], disable);
  65 }
  66
  67 static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
  68                                struct mtd_oob_region *oobregion)
  69 {
  70         switch (section) {
  71         case 0:
  72                 oobregion->offset = 8;
  73                 oobregion->length = 3;
  74                 return 0;
  75         case 1:
  76                 oobregion->offset = 13;
  77                 oobregion->length = 3;
  78                 return 0;
  79         default:
  80                 return -ERANGE;
  81         }
  82 }
  83
  84 static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
  85                                 struct mtd_oob_region *oobregion)
  86 {
  87         switch (section) {
  88         case 0:
  89                 oobregion->offset = 0;
  90                 oobregion->length = 4;
  91                 return 0;
  92         case 1:
  93                 oobregion->offset = 4;
  94                 oobregion->length = 1;
  95                 return 0;
  96         case 2:
  97                 oobregion->offset = 6;
  98                 oobregion->length = 2;
  99                 return 0;
 100         case 3:
 101                 oobregion->offset = 11;
 102                 oobregion->length = 2;
 103                 return 0;
 104         default:
 105                 return -ERANGE;
 106         }
 107 }
 108
 109 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
 110         .ecc = rb91x_ooblayout_ecc,
 111         .free = rb91x_ooblayout_free,
 112 };
 113
 114 static void rb91x_nand_write(struct rb91x_nand_drvdata *drvdata,
 115                              const u8 *buf,
 116                              unsigned len)
 117 {
 118         void __iomem *base = drvdata->ath79_gpio_base;
 119         u32 oe_reg;
 120         u32 out_reg;
 121         u32 out;
 122         unsigned i;
 123
 124         rb91x_nand_latch_lock(drvdata, 1);
 125         rb91x_nand_rst_key_poll_disable(drvdata, 1);
 126
 127         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 128         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 129
 130         /* Set data lines to output mode */
 131         __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT),
 132                      base + AR71XX_GPIO_REG_OE);
 133
 134         out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT);
 135         for (i = 0; i != len; i++) {
 136                 u32 data;
 137
 138                 data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
 139                         RB91X_NAND_HIGH_DATA_SHIFT;
 140                 data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
 141                 data |= out;
 142                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 143
 144                 /* Deactivate WE line */
 145                 data |= RB91X_NAND_NRW_BIT;
 146                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 147                 /* Flush write */
 148                 __raw_readl(base + AR71XX_GPIO_REG_OUT);
 149         }
 150
 151         /* Restore registers */
 152         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 153         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 154         /* Flush write */
 155         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 156
 157         rb91x_nand_rst_key_poll_disable(drvdata, 0);
 158         rb91x_nand_latch_lock(drvdata, 0);
 159 }
 160
 161 static void rb91x_nand_read(struct rb91x_nand_drvdata *drvdata,
 162                             u8 *read_buf,
 163                             unsigned len)
 164 {
 165         void __iomem *base = drvdata->ath79_gpio_base;
 166         u32 oe_reg;
 167         u32 out_reg;
 168         unsigned i;
 169
 170         /* Enable read mode */
 171         gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 1);
 172
 173         rb91x_nand_latch_lock(drvdata, 1);
 174         rb91x_nand_rst_key_poll_disable(drvdata, 1);
 175
 176         /* Save registers */
 177         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 178         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 179
 180         /* Set data lines to input mode */
 181         __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
 182                      base + AR71XX_GPIO_REG_OE);
 183
 184         for (i = 0; i < len; i++) {
 185                 u32 in;
 186                 u8 data;
 187
 188                 /* Activate RE line */
 189                 __raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_CLEAR);
 190                 /* Flush write */
 191                 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
 192
 193                 /* Read input lines */
 194                 in = __raw_readl(base + AR71XX_GPIO_REG_IN);
 195
 196                 /* Deactivate RE line */
 197                 __raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_SET);
 198
 199                 data = (in & RB91X_NAND_LOW_DATA_MASK);
 200                 data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
 201                         RB91X_NAND_HIGH_DATA_MASK;
 202
 203                 read_buf[i] = data;
 204         }
 205
 206         /* Restore  registers */
 207         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 208         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 209         /* Flush write */
 210         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 211
 212         rb91x_nand_rst_key_poll_disable(drvdata, 0);
 213         rb91x_nand_latch_lock(drvdata, 0);
 214
 215         /* Disable read mode */
 216         gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 0);
 217 }
 218
 219 static int rb91x_nand_dev_ready(struct nand_chip *chip)
 220 {
 221         struct rb91x_nand_drvdata *drvdata = (struct rb91x_nand_drvdata *)(chip->priv);
 222
 223         return gpiod_get_value_cansleep(drvdata->gpio[RB91X_NAND_RDY]);
 224 }
 225
 226 static void rb91x_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
 227                                 unsigned int ctrl)
 228 {
 229         struct rb91x_nand_drvdata *drvdata = chip->priv;
 230
 231         if (ctrl & NAND_CTRL_CHANGE) {
 232                 gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_CLE],
 233                                         (ctrl & NAND_CLE) ? 1 : 0);
 234                 gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_ALE],
 235                                         (ctrl & NAND_ALE) ? 1 : 0);
 236                 gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NCE],
 237                                         (ctrl & NAND_NCE) ? 1 : 0);
 238         }
 239
 240         if (cmd != NAND_CMD_NONE) {
 241                 u8 t = cmd;
 242
 243                 rb91x_nand_write(drvdata, &t, 1);
 244         }
 245 }
 246
 247 static u8 rb91x_nand_read_byte(struct nand_chip *chip)
 248 {
 249         u8 data = 0xff;
 250
 251         rb91x_nand_read(chip->priv, &data, 1);
 252
 253         return data;
 254 }
 255
 256 static void rb91x_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
 257 {
 258         rb91x_nand_read(chip->priv, buf, len);
 259 }
 260
 261 static void rb91x_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
 262 {
 263         rb91x_nand_write(chip->priv, buf, len);
 264 }
 265
 266 static void rb91x_nand_release(struct rb91x_nand_drvdata *drvdata)
 267 {
 268         mtd_device_unregister(nand_to_mtd(&drvdata->chip));
 269         nand_cleanup(&drvdata->chip);
 270 }
 271
 272 static int rb91x_nand_probe(struct platform_device *pdev)
 273 {
 274         struct rb91x_nand_drvdata *drvdata;
 275         struct mtd_info *mtd;
 276         int r;
 277         struct device *dev = &pdev->dev;
 278         struct gpio_descs *gpios;
 279
 280         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 281         if (!drvdata)
 282                 return -ENOMEM;
 283
 284         platform_set_drvdata(pdev, drvdata);
 285
 286         gpios = gpiod_get_array(dev, NULL, GPIOD_OUT_LOW);
 287         if (IS_ERR(gpios)) {
 288                 if (PTR_ERR(gpios) != -EPROBE_DEFER) {
 289                         dev_err(dev, "failed to get gpios: %d\n",
 290                                 PTR_ERR(gpios));
 291                 }
 292                 return PTR_ERR(gpios);
 293         }
 294
 295         if (gpios->ndescs != RB91X_NAND_GPIOS) {
 296                 dev_err(dev, "expected %d gpios\n", RB91X_NAND_GPIOS);
 297                 return -EINVAL;
 298         }
 299
 300         drvdata->gpio = gpios->desc;
 301
 302         gpiod_direction_input(drvdata->gpio[RB91X_NAND_RDY]);
 303
 304         drvdata->ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 305
 306         drvdata->dev = dev;
 307
 308         drvdata->chip.priv = drvdata;
 309
 310         drvdata->chip.legacy.cmd_ctrl = rb91x_nand_cmd_ctrl;
 311         drvdata->chip.legacy.dev_ready = rb91x_nand_dev_ready;
 312         drvdata->chip.legacy.read_byte = rb91x_nand_read_byte;
 313         drvdata->chip.legacy.write_buf = rb91x_nand_write_buf;
 314         drvdata->chip.legacy.read_buf = rb91x_nand_read_buf;
 315
 316         drvdata->chip.legacy.chip_delay = 25;
 317         drvdata->chip.ecc.engine_type      = NAND_ECC_ENGINE_TYPE_SOFT;
 318         drvdata->chip.ecc.algo             = NAND_ECC_ALGO_HAMMING;
 319         drvdata->chip.options = NAND_NO_SUBPAGE_WRITE;
 320
 321         r = nand_scan(&drvdata->chip, 1);
 322         if (r) {
 323                 dev_err(dev, "nand_scan() failed: %d\n", r);
 324                 return r;
 325         }
 326
 327         mtd = nand_to_mtd(&drvdata->chip);
 328         mtd->dev.parent = dev;
 329         mtd_set_of_node(mtd, dev->of_node);
 330         mtd->owner = THIS_MODULE;
 331         if (mtd->writesize == 512)
 332                 mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
 333
 334         r = mtd_device_register(mtd, NULL, 0);
 335         if (r) {
 336                 dev_err(dev, "mtd_device_register() failed: %d\n",
 337                         r);
 338                 goto err_release_nand;
 339         }
 340
 341         return 0;
 342
 343 err_release_nand:
 344         rb91x_nand_release(drvdata);
 345         return r;
 346 }
 347
 348 static int rb91x_nand_remove(struct platform_device *pdev)
 349 {
 350         struct rb91x_nand_drvdata *drvdata = platform_get_drvdata(pdev);
 351
 352         rb91x_nand_release(drvdata);
 353
 354         return 0;
 355 }
 356
 357 static const struct of_device_id rb91x_nand_match[] = {
 358         { .compatible = "mikrotik,rb91x-nand" },
 359         {},
 360 };
 361
 362 MODULE_DEVICE_TABLE(of, rb91x_nand_match);
 363
 364 static struct platform_driver rb91x_nand_driver = {
 365         .probe  = rb91x_nand_probe,
 366         .remove = rb91x_nand_remove,
 367         .driver = {
 368                 .name   = "rb91x-nand",
 369                 .owner  = THIS_MODULE,
 370                 .of_match_table = rb91x_nand_match,
 371         },
 372 };
 373
 374 module_platform_driver(rb91x_nand_driver);
 375
 376 MODULE_DESCRIPTION("MikrotTik RB91x NAND flash driver");
 377 MODULE_VERSION(DRV_VERSION);
 378 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 379 MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
 380 MODULE_LICENSE("GPL v2");