target/linux/ath79/files/drivers/mtd/nand/raw/rb91x_nand.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  MikroTik RB91x NAND flash driver
   4  *
   5  *  Main part is copied from original driver written by Gabor Juhos.
   6  *
   7  *  Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
   8  */
   9
  10 /*
  11  * WARNING: to speed up NAND reading/writing we are working with SoC GPIO
  12  * controller registers directly -- not through standard GPIO API.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mtd/rawnand.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/version.h>
  23 #include <linux/of_platform.h>
  24
  25 #include <asm/mach-ath79/ar71xx_regs.h>
  26
  27 /* Bit masks for NAND data lines in ath79 gpio 32-bit register */
  28 #define RB91X_NAND_NRW_BIT BIT(12)
  29 #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) \
  30                             | BIT(13) | BIT(14) | BIT(15))
  31 #define RB91X_NAND_LOW_DATA_MASK        0x1f
  32 #define RB91X_NAND_HIGH_DATA_MASK       0xe0
  33 #define RB91X_NAND_HIGH_DATA_SHIFT      8
  34
  35 enum rb91x_nand_gpios {
  36         RB91X_NAND_READ,/* Read */
  37         RB91X_NAND_RDY, /* NAND Ready */
  38         RB91X_NAND_NCE, /* Chip Enable. Active low */
  39         RB91X_NAND_CLE, /* Command Latch Enable */
  40         RB91X_NAND_ALE, /* Address Latch Enable */
  41         RB91X_NAND_NRW, /* Read/Write. Active low */
  42         RB91X_NAND_NLE, /* Latch Enable. Active low */
  43
  44         RB91X_NAND_GPIOS,
  45 };
  46
  47 struct rb91x_nand_drvdata {
  48         struct nand_chip chip;
  49         struct device *dev;
  50         struct gpio_desc **gpio;
  51         void __iomem *ath79_gpio_base;
  52 };
  53
  54 static inline void rb91x_nand_latch_lock(struct rb91x_nand_drvdata *drvdata,
  55                                          int lock)
  56 {
  57         gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NLE], lock);
  58 }
  59
  60 static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
  61                                struct mtd_oob_region *oobregion)
  62 {
  63         switch (section) {
  64         case 0:
  65                 oobregion->offset = 8;
  66                 oobregion->length = 3;
  67                 return 0;
  68         case 1:
  69                 oobregion->offset = 13;
  70                 oobregion->length = 3;
  71                 return 0;
  72         default:
  73                 return -ERANGE;
  74         }
  75 }
  76
  77 static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
  78                                 struct mtd_oob_region *oobregion)
  79 {
  80         switch (section) {
  81         case 0:
  82                 oobregion->offset = 0;
  83                 oobregion->length = 4;
  84                 return 0;
  85         case 1:
  86                 oobregion->offset = 4;
  87                 oobregion->length = 1;
  88                 return 0;
  89         case 2:
  90                 oobregion->offset = 6;
  91                 oobregion->length = 2;
  92                 return 0;
  93         case 3:
  94                 oobregion->offset = 11;
  95                 oobregion->length = 2;
  96                 return 0;
  97         default:
  98                 return -ERANGE;
  99         }
 100 }
 101
 102 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
 103         .ecc = rb91x_ooblayout_ecc,
 104         .free = rb91x_ooblayout_free,
 105 };
 106
 107 static void rb91x_nand_write(struct rb91x_nand_drvdata *drvdata,
 108                              const u8 *buf,
 109                              unsigned len)
 110 {
 111         void __iomem *base = drvdata->ath79_gpio_base;
 112         u32 oe_reg;
 113         u32 out_reg;
 114         u32 out;
 115         unsigned i;
 116
 117         rb91x_nand_latch_lock(drvdata, 1);
 118
 119         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 120         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 121
 122         /* Set data lines to output mode */
 123         __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT),
 124                      base + AR71XX_GPIO_REG_OE);
 125
 126         out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT);
 127         for (i = 0; i != len; i++) {
 128                 u32 data;
 129
 130                 data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
 131                         RB91X_NAND_HIGH_DATA_SHIFT;
 132                 data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
 133                 data |= out;
 134                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 135
 136                 /* Deactivate WE line */
 137                 data |= RB91X_NAND_NRW_BIT;
 138                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 139                 /* Flush write */
 140                 __raw_readl(base + AR71XX_GPIO_REG_OUT);
 141         }
 142
 143         /* Restore registers */
 144         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 145         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 146         /* Flush write */
 147         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 148
 149         rb91x_nand_latch_lock(drvdata, 0);
 150 }
 151
 152 static void rb91x_nand_read(struct rb91x_nand_drvdata *drvdata,
 153                             u8 *read_buf,
 154                             unsigned len)
 155 {
 156         void __iomem *base = drvdata->ath79_gpio_base;
 157         u32 oe_reg;
 158         u32 out_reg;
 159         unsigned i;
 160
 161         /* Enable read mode */
 162         gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 1);
 163
 164         rb91x_nand_latch_lock(drvdata, 1);
 165
 166         /* Save registers */
 167         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 168         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 169
 170         /* Set data lines to input mode */
 171         __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
 172                      base + AR71XX_GPIO_REG_OE);
 173
 174         for (i = 0; i < len; i++) {
 175                 u32 in;
 176                 u8 data;
 177
 178                 /* Activate RE line */
 179                 __raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_CLEAR);
 180                 /* Flush write */
 181                 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
 182
 183                 /* Read input lines */
 184                 in = __raw_readl(base + AR71XX_GPIO_REG_IN);
 185
 186                 /* Deactivate RE line */
 187                 __raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_SET);
 188
 189                 data = (in & RB91X_NAND_LOW_DATA_MASK);
 190                 data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
 191                         RB91X_NAND_HIGH_DATA_MASK;
 192
 193                 read_buf[i] = data;
 194         }
 195
 196         /* Restore  registers */
 197         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 198         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 199         /* Flush write */
 200         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 201
 202         rb91x_nand_latch_lock(drvdata, 0);
 203
 204         /* Disable read mode */
 205         gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 0);
 206 }
 207
 208 static int rb91x_nand_dev_ready(struct nand_chip *chip)
 209 {
 210         struct rb91x_nand_drvdata *drvdata = (struct rb91x_nand_drvdata *)(chip->priv);
 211
 212         return gpiod_get_value_cansleep(drvdata->gpio[RB91X_NAND_RDY]);
 213 }
 214
 215 static void rb91x_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
 216                                 unsigned int ctrl)
 217 {
 218         struct rb91x_nand_drvdata *drvdata = chip->priv;
 219
 220         if (ctrl & NAND_CTRL_CHANGE) {
 221                 gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_CLE],
 222                                         (ctrl & NAND_CLE) ? 1 : 0);
 223                 gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_ALE],
 224                                         (ctrl & NAND_ALE) ? 1 : 0);
 225                 gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NCE],
 226                                         (ctrl & NAND_NCE) ? 1 : 0);
 227         }
 228
 229         if (cmd != NAND_CMD_NONE) {
 230                 u8 t = cmd;
 231
 232                 rb91x_nand_write(drvdata, &t, 1);
 233         }
 234 }
 235
 236 static u8 rb91x_nand_read_byte(struct nand_chip *chip)
 237 {
 238         u8 data = 0xff;
 239
 240         rb91x_nand_read(chip->priv, &data, 1);
 241
 242         return data;
 243 }
 244
 245 static void rb91x_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
 246 {
 247         rb91x_nand_read(chip->priv, buf, len);
 248 }
 249
 250 static void rb91x_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
 251 {
 252         rb91x_nand_write(chip->priv, buf, len);
 253 }
 254
 255 static void rb91x_nand_release(struct rb91x_nand_drvdata *drvdata)
 256 {
 257         mtd_device_unregister(nand_to_mtd(&drvdata->chip));
 258         nand_cleanup(&drvdata->chip);
 259 }
 260
 261 static int rb91x_nand_probe(struct platform_device *pdev)
 262 {
 263         struct rb91x_nand_drvdata *drvdata;
 264         struct mtd_info *mtd;
 265         int r;
 266         struct device *dev = &pdev->dev;
 267         struct gpio_descs *gpios;
 268
 269         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 270         if (!drvdata)
 271                 return -ENOMEM;
 272
 273         platform_set_drvdata(pdev, drvdata);
 274
 275         gpios = gpiod_get_array(dev, NULL, GPIOD_OUT_LOW);
 276         if (IS_ERR(gpios)) {
 277                 dev_err(dev, "failed to get gpios: %d\n", (int)gpios);
 278                 return -EINVAL;
 279         }
 280
 281         if (gpios->ndescs != RB91X_NAND_GPIOS) {
 282                 dev_err(dev, "expected %d gpios\n", RB91X_NAND_GPIOS);
 283                 return -EINVAL;
 284         }
 285
 286         drvdata->gpio = gpios->desc;
 287
 288         gpiod_direction_input(drvdata->gpio[RB91X_NAND_RDY]);
 289
 290         drvdata->ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 291
 292         drvdata->dev = dev;
 293
 294         drvdata->chip.priv = drvdata;
 295
 296         drvdata->chip.legacy.cmd_ctrl = rb91x_nand_cmd_ctrl;
 297         drvdata->chip.legacy.dev_ready = rb91x_nand_dev_ready;
 298         drvdata->chip.legacy.read_byte = rb91x_nand_read_byte;
 299         drvdata->chip.legacy.write_buf = rb91x_nand_write_buf;
 300         drvdata->chip.legacy.read_buf = rb91x_nand_read_buf;
 301
 302         drvdata->chip.legacy.chip_delay = 25;
 303         drvdata->chip.ecc.engine_type      = NAND_ECC_ENGINE_TYPE_SOFT;
 304         drvdata->chip.ecc.algo             = NAND_ECC_ALGO_HAMMING;
 305         drvdata->chip.options = NAND_NO_SUBPAGE_WRITE;
 306
 307         r = nand_scan(&drvdata->chip, 1);
 308         if (r) {
 309                 dev_err(dev, "nand_scan() failed: %d\n", r);
 310                 return r;
 311         }
 312
 313         mtd = nand_to_mtd(&drvdata->chip);
 314         mtd->dev.parent = dev;
 315         mtd_set_of_node(mtd, dev->of_node);
 316         mtd->owner = THIS_MODULE;
 317         if (mtd->writesize == 512)
 318                 mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
 319
 320         r = mtd_device_register(mtd, NULL, 0);
 321         if (r) {
 322                 dev_err(dev, "mtd_device_register() failed: %d\n",
 323                         r);
 324                 goto err_release_nand;
 325         }
 326
 327         return 0;
 328
 329 err_release_nand:
 330         rb91x_nand_release(drvdata);
 331         return r;
 332 }
 333
 334 static int rb91x_nand_remove(struct platform_device *pdev)
 335 {
 336         struct rb91x_nand_drvdata *drvdata = platform_get_drvdata(pdev);
 337
 338         rb91x_nand_release(drvdata);
 339
 340         return 0;
 341 }
 342
 343 static const struct of_device_id rb91x_nand_match[] = {
 344         { .compatible = "mikrotik,rb91x-nand" },
 345         {},
 346 };
 347
 348 MODULE_DEVICE_TABLE(of, rb91x_nand_match);
 349
 350 static struct platform_driver rb91x_nand_driver = {
 351         .probe  = rb91x_nand_probe,
 352         .remove = rb91x_nand_remove,
 353         .driver = {
 354                 .name   = "rb91x-nand",
 355                 .owner  = THIS_MODULE,
 356                 .of_match_table = rb91x_nand_match,
 357         },
 358 };
 359
 360 module_platform_driver(rb91x_nand_driver);
 361
 362 MODULE_DESCRIPTION("MikrotTik RB91x NAND flash driver");
 363 MODULE_VERSION(DRV_VERSION);
 364 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 365 MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
 366 MODULE_LICENSE("GPL v2");