2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@nbd.name>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/of_mdio.h>
16 #include <linux/of_net.h>
17 #include <linux/phy.h>
18 #include <linux/mii.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
23 #define BITM(_count) (BIT(_count) - 1)
24 #define BITS(_shift, _count) (BITM(_count) << _shift)
26 #define AR7240_REG_MASK_CTRL 0x00
27 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
28 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
29 #define AR7240_MASK_CTRL_VERSION_S 8
30 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
31 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
32 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
34 #define AR7240_REG_MAC_ADDR0 0x20
35 #define AR7240_REG_MAC_ADDR1 0x24
37 #define AR7240_REG_FLOOD_MASK 0x2c
38 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
40 #define AR7240_REG_GLOBAL_CTRL 0x30
41 #define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
42 #define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
44 #define AR7240_REG_VTU 0x0040
45 #define AR7240_VTU_OP BITM(3)
46 #define AR7240_VTU_OP_NOOP 0x0
47 #define AR7240_VTU_OP_FLUSH 0x1
48 #define AR7240_VTU_OP_LOAD 0x2
49 #define AR7240_VTU_OP_PURGE 0x3
50 #define AR7240_VTU_OP_REMOVE_PORT 0x4
51 #define AR7240_VTU_ACTIVE BIT(3)
52 #define AR7240_VTU_FULL BIT(4)
53 #define AR7240_VTU_PORT BITS(8, 4)
54 #define AR7240_VTU_PORT_S 8
55 #define AR7240_VTU_VID BITS(16, 12)
56 #define AR7240_VTU_VID_S 16
57 #define AR7240_VTU_PRIO BITS(28, 3)
58 #define AR7240_VTU_PRIO_S 28
59 #define AR7240_VTU_PRIO_EN BIT(31)
61 #define AR7240_REG_VTU_DATA 0x0044
62 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
63 #define AR7240_VTUDATA_VALID BIT(11)
65 #define AR7240_REG_ATU 0x50
66 #define AR7240_ATU_FLUSH_ALL 0x1
68 #define AR7240_REG_AT_CTRL 0x5c
69 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
70 #define AR7240_AT_CTRL_AGE_EN BIT(17)
71 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
72 #define AR7240_AT_CTRL_RESERVED BIT(19)
73 #define AR7240_AT_CTRL_ARP_EN BIT(20)
75 #define AR7240_REG_TAG_PRIORITY 0x70
77 #define AR7240_REG_SERVICE_TAG 0x74
78 #define AR7240_SERVICE_TAG_M BITM(16)
80 #define AR7240_REG_CPU_PORT 0x78
81 #define AR7240_MIRROR_PORT_S 4
82 #define AR7240_MIRROR_PORT_M BITM(4)
83 #define AR7240_CPU_PORT_EN BIT(8)
85 #define AR7240_REG_MIB_FUNCTION0 0x80
86 #define AR7240_MIB_TIMER_M BITM(16)
87 #define AR7240_MIB_AT_HALF_EN BIT(16)
88 #define AR7240_MIB_BUSY BIT(17)
89 #define AR7240_MIB_FUNC_S 24
90 #define AR7240_MIB_FUNC_M BITM(3)
91 #define AR7240_MIB_FUNC_NO_OP 0x0
92 #define AR7240_MIB_FUNC_FLUSH 0x1
93 #define AR7240_MIB_FUNC_CAPTURE 0x3
95 #define AR7240_REG_MDIO_CTRL 0x98
96 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
97 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
98 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
99 #define AR7240_MDIO_CTRL_CMD_WRITE 0
100 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
101 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
102 #define AR7240_MDIO_CTRL_BUSY BIT(31)
104 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
106 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
107 #define AR7240_PORT_STATUS_SPEED_S 0
108 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
109 #define AR7240_PORT_STATUS_SPEED_10 0
110 #define AR7240_PORT_STATUS_SPEED_100 1
111 #define AR7240_PORT_STATUS_SPEED_1000 2
112 #define AR7240_PORT_STATUS_TXMAC BIT(2)
113 #define AR7240_PORT_STATUS_RXMAC BIT(3)
114 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
115 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
116 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
117 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
118 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
119 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
121 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
122 #define AR7240_PORT_CTRL_STATE_M BITM(3)
123 #define AR7240_PORT_CTRL_STATE_DISABLED 0
124 #define AR7240_PORT_CTRL_STATE_BLOCK 1
125 #define AR7240_PORT_CTRL_STATE_LISTEN 2
126 #define AR7240_PORT_CTRL_STATE_LEARN 3
127 #define AR7240_PORT_CTRL_STATE_FORWARD 4
128 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
129 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
130 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
131 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
132 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
133 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
134 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
135 #define AR7240_PORT_CTRL_HEADER BIT(11)
136 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
137 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
138 #define AR7240_PORT_CTRL_LEARN BIT(14)
139 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
140 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
141 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
143 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
145 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
146 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
147 #define AR7240_PORT_VLAN_MODE_S 30
148 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
149 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
150 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
151 #define AR7240_PORT_VLAN_MODE_SECURE 3
154 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
156 #define AR7240_STATS_RXBROAD 0x00
157 #define AR7240_STATS_RXPAUSE 0x04
158 #define AR7240_STATS_RXMULTI 0x08
159 #define AR7240_STATS_RXFCSERR 0x0c
160 #define AR7240_STATS_RXALIGNERR 0x10
161 #define AR7240_STATS_RXRUNT 0x14
162 #define AR7240_STATS_RXFRAGMENT 0x18
163 #define AR7240_STATS_RX64BYTE 0x1c
164 #define AR7240_STATS_RX128BYTE 0x20
165 #define AR7240_STATS_RX256BYTE 0x24
166 #define AR7240_STATS_RX512BYTE 0x28
167 #define AR7240_STATS_RX1024BYTE 0x2c
168 #define AR7240_STATS_RX1518BYTE 0x30
169 #define AR7240_STATS_RXMAXBYTE 0x34
170 #define AR7240_STATS_RXTOOLONG 0x38
171 #define AR7240_STATS_RXGOODBYTE 0x3c
172 #define AR7240_STATS_RXBADBYTE 0x44
173 #define AR7240_STATS_RXOVERFLOW 0x4c
174 #define AR7240_STATS_FILTERED 0x50
175 #define AR7240_STATS_TXBROAD 0x54
176 #define AR7240_STATS_TXPAUSE 0x58
177 #define AR7240_STATS_TXMULTI 0x5c
178 #define AR7240_STATS_TXUNDERRUN 0x60
179 #define AR7240_STATS_TX64BYTE 0x64
180 #define AR7240_STATS_TX128BYTE 0x68
181 #define AR7240_STATS_TX256BYTE 0x6c
182 #define AR7240_STATS_TX512BYTE 0x70
183 #define AR7240_STATS_TX1024BYTE 0x74
184 #define AR7240_STATS_TX1518BYTE 0x78
185 #define AR7240_STATS_TXMAXBYTE 0x7c
186 #define AR7240_STATS_TXOVERSIZE 0x80
187 #define AR7240_STATS_TXBYTE 0x84
188 #define AR7240_STATS_TXCOLLISION 0x8c
189 #define AR7240_STATS_TXABORTCOL 0x90
190 #define AR7240_STATS_TXMULTICOL 0x94
191 #define AR7240_STATS_TXSINGLECOL 0x98
192 #define AR7240_STATS_TXEXCDEFER 0x9c
193 #define AR7240_STATS_TXDEFER 0xa0
194 #define AR7240_STATS_TXLATECOL 0xa4
196 #define AR7240_PORT_CPU 0
197 #define AR7240_NUM_PORTS 6
198 #define AR7240_NUM_PHYS 5
200 #define AR7240_PHY_ID1 0x004d
201 #define AR7240_PHY_ID2 0xd041
203 #define AR934X_PHY_ID1 0x004d
204 #define AR934X_PHY_ID2 0xd042
206 #define AR7240_MAX_VLANS 16
208 #define AR934X_REG_OPER_MODE0 0x04
209 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
210 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
212 #define AR934X_REG_OPER_MODE1 0x08
213 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
215 #define AR934X_REG_FLOOD_MASK 0x2c
216 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
217 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
219 #define AR934X_REG_QM_CTRL 0x3c
220 #define AR934X_QM_CTRL_ARP_EN BIT(15)
222 #define AR934X_REG_AT_CTRL 0x5c
223 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
224 #define AR934X_AT_CTRL_AGE_EN BIT(17)
225 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
227 #define AR934X_MIB_ENABLE BIT(30)
229 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
231 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
232 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
233 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
234 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
235 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
236 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
237 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
238 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
239 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
241 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
242 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
243 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
244 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
245 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
246 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
247 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
249 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
251 struct ar7240sw_port_stat
{
252 unsigned long rx_broadcast
;
253 unsigned long rx_pause
;
254 unsigned long rx_multicast
;
255 unsigned long rx_fcs_error
;
256 unsigned long rx_align_error
;
257 unsigned long rx_runt
;
258 unsigned long rx_fragments
;
259 unsigned long rx_64byte
;
260 unsigned long rx_128byte
;
261 unsigned long rx_256byte
;
262 unsigned long rx_512byte
;
263 unsigned long rx_1024byte
;
264 unsigned long rx_1518byte
;
265 unsigned long rx_maxbyte
;
266 unsigned long rx_toolong
;
267 unsigned long rx_good_byte
;
268 unsigned long rx_bad_byte
;
269 unsigned long rx_overflow
;
270 unsigned long filtered
;
272 unsigned long tx_broadcast
;
273 unsigned long tx_pause
;
274 unsigned long tx_multicast
;
275 unsigned long tx_underrun
;
276 unsigned long tx_64byte
;
277 unsigned long tx_128byte
;
278 unsigned long tx_256byte
;
279 unsigned long tx_512byte
;
280 unsigned long tx_1024byte
;
281 unsigned long tx_1518byte
;
282 unsigned long tx_maxbyte
;
283 unsigned long tx_oversize
;
284 unsigned long tx_byte
;
285 unsigned long tx_collision
;
286 unsigned long tx_abortcol
;
287 unsigned long tx_multicol
;
288 unsigned long tx_singlecol
;
289 unsigned long tx_excdefer
;
290 unsigned long tx_defer
;
291 unsigned long tx_xlatecol
;
295 struct mii_bus
*mii_bus
;
296 struct mii_bus
*switch_mii_bus
;
297 struct device_node
*of_node
;
298 struct device_node
*mdio_node
;
299 struct switch_dev swdev
;
303 u16 vlan_id
[AR7240_MAX_VLANS
];
304 u8 vlan_table
[AR7240_MAX_VLANS
];
306 u16 pvid
[AR7240_NUM_PORTS
];
310 struct ar7240sw_port_stat port_stats
[AR7240_NUM_PORTS
];
313 struct ar7240sw_hw_stat
{
314 char string
[ETH_GSTRING_LEN
];
319 static DEFINE_MUTEX(reg_mutex
);
321 static inline int sw_is_ar7240(struct ar7240sw
*as
)
323 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR7240
;
326 static inline int sw_is_ar934x(struct ar7240sw
*as
)
328 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR934X
;
331 static inline u32
ar7240sw_port_mask(struct ar7240sw
*as
, int port
)
336 static inline u32
ar7240sw_port_mask_all(struct ar7240sw
*as
)
338 return BIT(as
->swdev
.ports
) - 1;
341 static inline u32
ar7240sw_port_mask_but(struct ar7240sw
*as
, int port
)
343 return ar7240sw_port_mask_all(as
) & ~BIT(port
);
346 static inline u16
mk_phy_addr(u32 reg
)
348 return 0x17 & ((reg
>> 4) | 0x10);
351 static inline u16
mk_phy_reg(u32 reg
)
353 return (reg
<< 1) & 0x1e;
356 static inline u16
mk_high_addr(u32 reg
)
358 return (reg
>> 7) & 0x1ff;
361 static u32
__ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg
)
368 reg
= (reg
& 0xfffffffc) >> 2;
369 phy_addr
= mk_phy_addr(reg
);
370 phy_reg
= mk_phy_reg(reg
);
372 local_irq_save(flags
);
373 mutex_lock(&mii
->mdio_lock
);
374 mii
->write(mii
, 0x1f, 0x10, mk_high_addr(reg
));
375 lo
= (u32
) mii
->read(mii
, phy_addr
, phy_reg
);
376 hi
= (u32
) mii
->read(mii
, phy_addr
, phy_reg
+ 1);
377 mutex_unlock(&mii
->mdio_lock
);
378 local_irq_restore(flags
);
380 return (hi
<< 16) | lo
;
383 static void __ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg
, u32 val
)
389 reg
= (reg
& 0xfffffffc) >> 2;
390 phy_addr
= mk_phy_addr(reg
);
391 phy_reg
= mk_phy_reg(reg
);
393 local_irq_save(flags
);
394 mutex_lock(&mii
->mdio_lock
);
395 mii
->write(mii
, 0x1f, 0x10, mk_high_addr(reg
));
396 mii
->write(mii
, phy_addr
, phy_reg
+ 1, (val
>> 16));
397 mii
->write(mii
, phy_addr
, phy_reg
, (val
& 0xffff));
398 mutex_unlock(&mii
->mdio_lock
);
399 local_irq_restore(flags
);
402 static u32
ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg_addr
)
406 mutex_lock(®_mutex
);
407 ret
= __ar7240sw_reg_read(mii
, reg_addr
);
408 mutex_unlock(®_mutex
);
413 static void ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg_addr
, u32 reg_val
)
415 mutex_lock(®_mutex
);
416 __ar7240sw_reg_write(mii
, reg_addr
, reg_val
);
417 mutex_unlock(®_mutex
);
420 static u32
ar7240sw_reg_rmw(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
)
424 mutex_lock(®_mutex
);
425 t
= __ar7240sw_reg_read(mii
, reg
);
428 __ar7240sw_reg_write(mii
, reg
, t
);
429 mutex_unlock(®_mutex
);
434 static void ar7240sw_reg_set(struct mii_bus
*mii
, u32 reg
, u32 val
)
438 mutex_lock(®_mutex
);
439 t
= __ar7240sw_reg_read(mii
, reg
);
441 __ar7240sw_reg_write(mii
, reg
, t
);
442 mutex_unlock(®_mutex
);
445 static int __ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
450 for (i
= 0; i
< timeout
; i
++) {
453 t
= __ar7240sw_reg_read(mii
, reg
);
454 if ((t
& mask
) == val
)
457 usleep_range(1000, 2000);
463 static int ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
468 mutex_lock(®_mutex
);
469 ret
= __ar7240sw_reg_wait(mii
, reg
, mask
, val
, timeout
);
470 mutex_unlock(®_mutex
);
474 int ar7240sw_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
478 struct ar7240sw
*as
= bus
->priv
;
479 struct mii_bus
*mii
= as
->mii_bus
;
481 if (phy_addr
>= AR7240_NUM_PHYS
)
484 mutex_lock(®_mutex
);
485 t
= (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
486 (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
487 AR7240_MDIO_CTRL_MASTER_EN
|
488 AR7240_MDIO_CTRL_BUSY
|
489 AR7240_MDIO_CTRL_CMD_READ
;
491 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
492 err
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
493 AR7240_MDIO_CTRL_BUSY
, 0, 5);
495 val
= __ar7240sw_reg_read(mii
, AR7240_REG_MDIO_CTRL
);
496 mutex_unlock(®_mutex
);
498 return val
& AR7240_MDIO_CTRL_DATA_M
;
501 int ar7240sw_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
506 struct ar7240sw
*as
= bus
->priv
;
507 struct mii_bus
*mii
= as
->mii_bus
;
509 if (phy_addr
>= AR7240_NUM_PHYS
)
512 mutex_lock(®_mutex
);
513 t
= (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
514 (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
515 AR7240_MDIO_CTRL_MASTER_EN
|
516 AR7240_MDIO_CTRL_BUSY
|
517 AR7240_MDIO_CTRL_CMD_WRITE
|
520 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
521 ret
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
522 AR7240_MDIO_CTRL_BUSY
, 0, 5);
523 mutex_unlock(®_mutex
);
528 static int ar7240sw_capture_stats(struct ar7240sw
*as
)
530 struct mii_bus
*mii
= as
->mii_bus
;
534 write_lock(&as
->stats_lock
);
536 /* Capture the hardware statistics for all ports */
537 ar7240sw_reg_rmw(mii
, AR7240_REG_MIB_FUNCTION0
,
538 (AR7240_MIB_FUNC_M
<< AR7240_MIB_FUNC_S
),
539 (AR7240_MIB_FUNC_CAPTURE
<< AR7240_MIB_FUNC_S
));
541 /* Wait for the capturing to complete. */
542 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MIB_FUNCTION0
,
543 AR7240_MIB_BUSY
, 0, 10);
548 for (port
= 0; port
< AR7240_NUM_PORTS
; port
++) {
550 struct ar7240sw_port_stat
*stats
;
552 base
= AR7240_REG_STATS_BASE(port
);
553 stats
= &as
->port_stats
[port
];
555 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
557 stats
->rx_good_byte
+= READ_STAT(RXGOODBYTE
);
558 stats
->tx_byte
+= READ_STAT(TXBYTE
);
566 write_unlock(&as
->stats_lock
);
570 static void ar7240sw_disable_port(struct ar7240sw
*as
, unsigned port
)
572 ar7240sw_reg_write(as
->mii_bus
, AR7240_REG_PORT_CTRL(port
),
573 AR7240_PORT_CTRL_STATE_DISABLED
);
576 static void ar7240sw_setup(struct ar7240sw
*as
)
578 struct mii_bus
*mii
= as
->mii_bus
;
580 /* Enable CPU port, and disable mirror port */
581 ar7240sw_reg_write(mii
, AR7240_REG_CPU_PORT
,
583 (15 << AR7240_MIRROR_PORT_S
));
585 /* Setup TAG priority mapping */
586 ar7240sw_reg_write(mii
, AR7240_REG_TAG_PRIORITY
, 0xfa50);
588 if (sw_is_ar934x(as
)) {
589 /* Enable aging, MAC replacing */
590 ar7240sw_reg_write(mii
, AR934X_REG_AT_CTRL
,
591 0x2b /* 5 min age time */ |
592 AR934X_AT_CTRL_AGE_EN
|
593 AR934X_AT_CTRL_LEARN_CHANGE
);
594 /* Enable ARP frame acknowledge */
595 ar7240sw_reg_set(mii
, AR934X_REG_QM_CTRL
,
596 AR934X_QM_CTRL_ARP_EN
);
597 /* Enable Broadcast/Multicast frames transmitted to the CPU */
598 ar7240sw_reg_set(mii
, AR934X_REG_FLOOD_MASK
,
599 AR934X_FLOOD_MASK_BC_DP(0) |
600 AR934X_FLOOD_MASK_MC_DP(0));
603 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
,
604 AR9340_GLOBAL_CTRL_MTU_M
,
605 AR9340_GLOBAL_CTRL_MTU_M
);
607 /* Enable MIB counters */
608 ar7240sw_reg_set(mii
, AR7240_REG_MIB_FUNCTION0
,
612 /* Enable ARP frame acknowledge, aging, MAC replacing */
613 ar7240sw_reg_write(mii
, AR7240_REG_AT_CTRL
,
614 AR7240_AT_CTRL_RESERVED
|
615 0x2b /* 5 min age time */ |
616 AR7240_AT_CTRL_AGE_EN
|
617 AR7240_AT_CTRL_ARP_EN
|
618 AR7240_AT_CTRL_LEARN_CHANGE
);
619 /* Enable Broadcast frames transmitted to the CPU */
620 ar7240sw_reg_set(mii
, AR7240_REG_FLOOD_MASK
,
621 AR7240_FLOOD_MASK_BROAD_TO_CPU
);
624 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
,
625 AR7240_GLOBAL_CTRL_MTU_M
,
626 AR7240_GLOBAL_CTRL_MTU_M
);
629 /* setup Service TAG */
630 ar7240sw_reg_rmw(mii
, AR7240_REG_SERVICE_TAG
, AR7240_SERVICE_TAG_M
, 0);
633 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
635 ar7240sw_phy_poll_reset(struct mii_bus
*bus
)
637 const unsigned int sleep_msecs
= 20;
640 for (elapsed
= sleep_msecs
; elapsed
<= 600;
641 elapsed
+= sleep_msecs
) {
643 for (i
= 0; i
< AR7240_NUM_PHYS
; i
++) {
644 ret
= ar7240sw_phy_read(bus
, i
, MII_BMCR
);
647 if (ret
& BMCR_RESET
)
649 if (i
== AR7240_NUM_PHYS
- 1) {
650 usleep_range(1000, 2000);
658 static int ar7240sw_reset(struct ar7240sw
*as
)
660 struct mii_bus
*mii
= as
->mii_bus
;
661 struct mii_bus
*swmii
= as
->switch_mii_bus
;
665 /* Set all ports to disabled state. */
666 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
667 ar7240sw_disable_port(as
, i
);
669 /* Wait for transmit queues to drain. */
670 usleep_range(2000, 3000);
672 /* Reset the switch. */
673 ar7240sw_reg_write(mii
, AR7240_REG_MASK_CTRL
,
674 AR7240_MASK_CTRL_SOFT_RESET
);
676 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MASK_CTRL
,
677 AR7240_MASK_CTRL_SOFT_RESET
, 0, 1000);
680 for (i
= 0; i
< AR7240_NUM_PHYS
; i
++) {
681 ar7240sw_phy_write(swmii
, i
, MII_ADVERTISE
,
682 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
683 ADVERTISE_PAUSE_ASYM
);
684 ar7240sw_phy_write(swmii
, i
, MII_BMCR
,
685 BMCR_RESET
| BMCR_ANENABLE
);
687 ret
= ar7240sw_phy_poll_reset(swmii
);
695 static void ar7240sw_setup_port(struct ar7240sw
*as
, unsigned port
, u8 portmask
)
697 struct mii_bus
*mii
= as
->mii_bus
;
701 ctrl
= AR7240_PORT_CTRL_STATE_FORWARD
| AR7240_PORT_CTRL_LEARN
|
702 AR7240_PORT_CTRL_SINGLE_VLAN
;
704 if (port
== AR7240_PORT_CPU
) {
705 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
706 AR7240_PORT_STATUS_SPEED_1000
|
707 AR7240_PORT_STATUS_TXFLOW
|
708 AR7240_PORT_STATUS_RXFLOW
|
709 AR7240_PORT_STATUS_TXMAC
|
710 AR7240_PORT_STATUS_RXMAC
|
711 AR7240_PORT_STATUS_DUPLEX
);
713 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
714 AR7240_PORT_STATUS_LINK_AUTO
);
717 /* Set the default VID for this port */
719 vid
= as
->vlan_id
[as
->pvid
[port
]];
720 mode
= AR7240_PORT_VLAN_MODE_SECURE
;
723 mode
= AR7240_PORT_VLAN_MODE_PORT_ONLY
;
727 if (as
->vlan_tagged
& BIT(port
))
728 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_ADD
<<
729 AR7240_PORT_CTRL_VLAN_MODE_S
;
731 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_STRIP
<<
732 AR7240_PORT_CTRL_VLAN_MODE_S
;
734 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_KEEP
<<
735 AR7240_PORT_CTRL_VLAN_MODE_S
;
739 if (port
== AR7240_PORT_CPU
)
740 portmask
= ar7240sw_port_mask_but(as
, AR7240_PORT_CPU
);
742 portmask
= ar7240sw_port_mask(as
, AR7240_PORT_CPU
);
745 /* preserve mirror rx&tx flags */
746 ctrl
|= ar7240sw_reg_read(mii
, AR7240_REG_PORT_CTRL(port
)) &
747 (AR7240_PORT_CTRL_MIRROR_RX
| AR7240_PORT_CTRL_MIRROR_TX
);
749 /* allow the port to talk to all other ports, but exclude its
750 * own ID to prevent frames from being reflected back to the
751 * port that they came from */
752 portmask
&= ar7240sw_port_mask_but(as
, port
);
754 ar7240sw_reg_write(mii
, AR7240_REG_PORT_CTRL(port
), ctrl
);
755 if (sw_is_ar934x(as
)) {
758 vlan1
= (vid
<< AR934X_PORT_VLAN1_DEFAULT_CVID_S
);
759 vlan2
= (portmask
<< AR934X_PORT_VLAN2_PORT_VID_MEM_S
) |
760 (mode
<< AR934X_PORT_VLAN2_8021Q_MODE_S
);
761 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN1(port
), vlan1
);
762 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN2(port
), vlan2
);
766 vlan
= vid
| (mode
<< AR7240_PORT_VLAN_MODE_S
) |
767 (portmask
<< AR7240_PORT_VLAN_DEST_PORTS_S
);
769 ar7240sw_reg_write(mii
, AR7240_REG_PORT_VLAN(port
), vlan
);
774 ar7240_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
775 struct switch_val
*val
)
777 struct ar7240sw
*as
= sw_to_ar7240(dev
);
778 as
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
783 ar7240_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
784 struct switch_val
*val
)
786 struct ar7240sw
*as
= sw_to_ar7240(dev
);
787 val
->value
.i
= as
->vlan_id
[val
->port_vlan
];
792 ar7240_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
794 struct ar7240sw
*as
= sw_to_ar7240(dev
);
796 /* make sure no invalid PVIDs get set */
798 if (vlan
>= dev
->vlans
)
801 as
->pvid
[port
] = vlan
;
806 ar7240_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
808 struct ar7240sw
*as
= sw_to_ar7240(dev
);
809 *vlan
= as
->pvid
[port
];
814 ar7240_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
816 struct ar7240sw
*as
= sw_to_ar7240(dev
);
817 u8 ports
= as
->vlan_table
[val
->port_vlan
];
821 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
822 struct switch_port
*p
;
824 if (!(ports
& (1 << i
)))
827 p
= &val
->value
.ports
[val
->len
++];
829 if (as
->vlan_tagged
& (1 << i
))
830 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
838 ar7240_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
840 struct ar7240sw
*as
= sw_to_ar7240(dev
);
841 u8
*vt
= &as
->vlan_table
[val
->port_vlan
];
845 for (i
= 0; i
< val
->len
; i
++) {
846 struct switch_port
*p
= &val
->value
.ports
[i
];
848 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
849 as
->vlan_tagged
|= (1 << p
->id
);
851 as
->vlan_tagged
&= ~(1 << p
->id
);
852 as
->pvid
[p
->id
] = val
->port_vlan
;
854 /* make sure that an untagged port does not
855 * appear in other vlans */
856 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
857 if (j
== val
->port_vlan
)
859 as
->vlan_table
[j
] &= ~(1 << p
->id
);
869 ar7240_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
870 struct switch_val
*val
)
872 struct ar7240sw
*as
= sw_to_ar7240(dev
);
873 as
->vlan
= !!val
->value
.i
;
878 ar7240_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
879 struct switch_val
*val
)
881 struct ar7240sw
*as
= sw_to_ar7240(dev
);
882 val
->value
.i
= as
->vlan
;
887 ar7240_vtu_op(struct ar7240sw
*as
, u32 op
, u32 val
)
889 struct mii_bus
*mii
= as
->mii_bus
;
891 if (ar7240sw_reg_wait(mii
, AR7240_REG_VTU
, AR7240_VTU_ACTIVE
, 0, 5))
894 if ((op
& AR7240_VTU_OP
) == AR7240_VTU_OP_LOAD
) {
895 val
&= AR7240_VTUDATA_MEMBER
;
896 val
|= AR7240_VTUDATA_VALID
;
897 ar7240sw_reg_write(mii
, AR7240_REG_VTU_DATA
, val
);
899 op
|= AR7240_VTU_ACTIVE
;
900 ar7240sw_reg_write(mii
, AR7240_REG_VTU
, op
);
904 ar7240_hw_apply(struct switch_dev
*dev
)
906 struct ar7240sw
*as
= sw_to_ar7240(dev
);
907 u8 portmask
[AR7240_NUM_PORTS
];
910 /* flush all vlan translation unit entries */
911 ar7240_vtu_op(as
, AR7240_VTU_OP_FLUSH
, 0);
913 memset(portmask
, 0, sizeof(portmask
));
915 /* calculate the port destination masks and load vlans
916 * into the vlan translation unit */
917 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
918 u8 vp
= as
->vlan_table
[j
];
923 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
926 portmask
[i
] |= vp
& ~mask
;
931 (as
->vlan_id
[j
] << AR7240_VTU_VID_S
),
936 * isolate all ports, but connect them to the cpu port */
937 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
938 if (i
== AR7240_PORT_CPU
)
941 portmask
[i
] = 1 << AR7240_PORT_CPU
;
942 portmask
[AR7240_PORT_CPU
] |= (1 << i
);
946 /* update the port destination mask registers and tag settings */
947 for (i
= 0; i
< as
->swdev
.ports
; i
++)
948 ar7240sw_setup_port(as
, i
, portmask
[i
]);
954 ar7240_reset_switch(struct switch_dev
*dev
)
956 struct ar7240sw
*as
= sw_to_ar7240(dev
);
962 ar7240_get_port_link(struct switch_dev
*dev
, int port
,
963 struct switch_port_link
*link
)
965 struct ar7240sw
*as
= sw_to_ar7240(dev
);
966 struct mii_bus
*mii
= as
->mii_bus
;
969 if (port
>= AR7240_NUM_PORTS
)
972 status
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_STATUS(port
));
973 link
->aneg
= !!(status
& AR7240_PORT_STATUS_LINK_AUTO
);
975 link
->link
= !!(status
& AR7240_PORT_STATUS_LINK_UP
);
982 link
->duplex
= !!(status
& AR7240_PORT_STATUS_DUPLEX
);
983 link
->tx_flow
= !!(status
& AR7240_PORT_STATUS_TXFLOW
);
984 link
->rx_flow
= !!(status
& AR7240_PORT_STATUS_RXFLOW
);
985 switch (status
& AR7240_PORT_STATUS_SPEED_M
) {
986 case AR7240_PORT_STATUS_SPEED_10
:
987 link
->speed
= SWITCH_PORT_SPEED_10
;
989 case AR7240_PORT_STATUS_SPEED_100
:
990 link
->speed
= SWITCH_PORT_SPEED_100
;
992 case AR7240_PORT_STATUS_SPEED_1000
:
993 link
->speed
= SWITCH_PORT_SPEED_1000
;
1001 ar7240_get_port_stats(struct switch_dev
*dev
, int port
,
1002 struct switch_port_stats
*stats
)
1004 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1006 if (port
>= AR7240_NUM_PORTS
)
1009 ar7240sw_capture_stats(as
);
1011 read_lock(&as
->stats_lock
);
1012 stats
->rx_bytes
= as
->port_stats
[port
].rx_good_byte
;
1013 stats
->tx_bytes
= as
->port_stats
[port
].tx_byte
;
1014 read_unlock(&as
->stats_lock
);
1020 ar7240_set_mirror_monitor_port(struct switch_dev
*dev
,
1021 const struct switch_attr
*attr
,
1022 struct switch_val
*val
)
1024 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1025 struct mii_bus
*mii
= as
->mii_bus
;
1027 int port
= val
->value
.i
;
1032 ar7240sw_reg_rmw(mii
, AR7240_REG_CPU_PORT
,
1033 AR7240_MIRROR_PORT_M
<< AR7240_MIRROR_PORT_S
,
1034 port
<< AR7240_MIRROR_PORT_S
);
1040 ar7240_get_mirror_monitor_port(struct switch_dev
*dev
,
1041 const struct switch_attr
*attr
,
1042 struct switch_val
*val
)
1044 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1045 struct mii_bus
*mii
= as
->mii_bus
;
1049 ret
= ar7240sw_reg_read(mii
, AR7240_REG_CPU_PORT
);
1050 val
->value
.i
= (ret
>> AR7240_MIRROR_PORT_S
) & AR7240_MIRROR_PORT_M
;
1056 ar7240_set_mirror_rx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1057 struct switch_val
*val
)
1059 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1060 struct mii_bus
*mii
= as
->mii_bus
;
1062 int port
= val
->port_vlan
;
1064 if (port
>= dev
->ports
)
1067 if (val
&& val
->value
.i
== 1)
1068 ar7240sw_reg_set(mii
, AR7240_REG_PORT_CTRL(port
),
1069 AR7240_PORT_CTRL_MIRROR_RX
);
1071 ar7240sw_reg_rmw(mii
, AR7240_REG_PORT_CTRL(port
),
1072 AR7240_PORT_CTRL_MIRROR_RX
, 0);
1078 ar7240_get_mirror_rx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1079 struct switch_val
*val
)
1081 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1082 struct mii_bus
*mii
= as
->mii_bus
;
1086 int port
= val
->port_vlan
;
1088 if (port
>= dev
->ports
)
1091 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_CTRL(port
));
1093 if ((ctrl
& AR7240_PORT_CTRL_MIRROR_RX
) == AR7240_PORT_CTRL_MIRROR_RX
)
1102 ar7240_set_mirror_tx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1103 struct switch_val
*val
)
1105 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1106 struct mii_bus
*mii
= as
->mii_bus
;
1108 int port
= val
->port_vlan
;
1110 if (port
>= dev
->ports
)
1113 if (val
&& val
->value
.i
== 1)
1114 ar7240sw_reg_set(mii
, AR7240_REG_PORT_CTRL(port
),
1115 AR7240_PORT_CTRL_MIRROR_TX
);
1117 ar7240sw_reg_rmw(mii
, AR7240_REG_PORT_CTRL(port
),
1118 AR7240_PORT_CTRL_MIRROR_TX
, 0);
1124 ar7240_get_mirror_tx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1125 struct switch_val
*val
)
1127 struct ar7240sw
*as
= sw_to_ar7240(dev
);
1128 struct mii_bus
*mii
= as
->mii_bus
;
1132 int port
= val
->port_vlan
;
1134 if (port
>= dev
->ports
)
1137 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_CTRL(port
));
1139 if ((ctrl
& AR7240_PORT_CTRL_MIRROR_TX
) == AR7240_PORT_CTRL_MIRROR_TX
)
1147 static struct switch_attr ar7240_globals
[] = {
1149 .type
= SWITCH_TYPE_INT
,
1150 .name
= "enable_vlan",
1151 .description
= "Enable VLAN mode",
1152 .set
= ar7240_set_vlan
,
1153 .get
= ar7240_get_vlan
,
1157 .type
= SWITCH_TYPE_INT
,
1158 .name
= "mirror_monitor_port",
1159 .description
= "Mirror monitor port",
1160 .set
= ar7240_set_mirror_monitor_port
,
1161 .get
= ar7240_get_mirror_monitor_port
,
1166 static struct switch_attr ar7240_port
[] = {
1168 .type
= SWITCH_TYPE_INT
,
1169 .name
= "enable_mirror_rx",
1170 .description
= "Enable mirroring of RX packets",
1171 .set
= ar7240_set_mirror_rx
,
1172 .get
= ar7240_get_mirror_rx
,
1176 .type
= SWITCH_TYPE_INT
,
1177 .name
= "enable_mirror_tx",
1178 .description
= "Enable mirroring of TX packets",
1179 .set
= ar7240_set_mirror_tx
,
1180 .get
= ar7240_get_mirror_tx
,
1185 static struct switch_attr ar7240_vlan
[] = {
1187 .type
= SWITCH_TYPE_INT
,
1189 .description
= "VLAN ID",
1190 .set
= ar7240_set_vid
,
1191 .get
= ar7240_get_vid
,
1196 static const struct switch_dev_ops ar7240_ops
= {
1198 .attr
= ar7240_globals
,
1199 .n_attr
= ARRAY_SIZE(ar7240_globals
),
1202 .attr
= ar7240_port
,
1203 .n_attr
= ARRAY_SIZE(ar7240_port
),
1206 .attr
= ar7240_vlan
,
1207 .n_attr
= ARRAY_SIZE(ar7240_vlan
),
1209 .get_port_pvid
= ar7240_get_pvid
,
1210 .set_port_pvid
= ar7240_set_pvid
,
1211 .get_vlan_ports
= ar7240_get_ports
,
1212 .set_vlan_ports
= ar7240_set_ports
,
1213 .apply_config
= ar7240_hw_apply
,
1214 .reset_switch
= ar7240_reset_switch
,
1215 .get_port_link
= ar7240_get_port_link
,
1216 .get_port_stats
= ar7240_get_port_stats
,
1220 ag71xx_ar7240_probe(struct mdio_device
*mdiodev
)
1222 struct mii_bus
*mii
= mdiodev
->bus
;
1223 struct ar7240sw
*as
;
1224 struct switch_dev
*swdev
;
1225 struct reset_control
*switch_reset
;
1227 int phy_if_mode
, err
, i
;
1229 as
= devm_kzalloc(&mdiodev
->dev
, sizeof(*as
), GFP_KERNEL
);
1234 as
->of_node
= mdiodev
->dev
.of_node
;
1235 as
->mdio_node
= of_get_child_by_name(as
->of_node
, "mdio-bus");
1239 switch_reset
= devm_reset_control_get_optional(&mdiodev
->dev
, "switch");
1241 reset_control_assert(switch_reset
);
1243 reset_control_deassert(switch_reset
);
1247 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_MASK_CTRL
);
1248 as
->ver
= (ctrl
>> AR7240_MASK_CTRL_VERSION_S
) &
1249 AR7240_MASK_CTRL_VERSION_M
;
1251 if (sw_is_ar7240(as
)) {
1252 swdev
->name
= "AR7240/AR9330 built-in switch";
1253 swdev
->ports
= AR7240_NUM_PORTS
- 1;
1254 } else if (sw_is_ar934x(as
)) {
1255 swdev
->name
= "AR934X built-in switch";
1256 phy_if_mode
= of_get_phy_mode(as
->of_node
);
1258 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
1259 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
1260 AR934X_OPER_MODE0_MAC_GMII_EN
);
1261 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
1262 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
1263 AR934X_OPER_MODE0_PHY_MII_EN
);
1265 pr_err("%s: invalid PHY interface mode\n",
1266 dev_name(&mdiodev
->dev
));
1270 if (of_property_read_bool(as
->of_node
, "phy4-mii-enable")) {
1271 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE1
,
1272 AR934X_REG_OPER_MODE1_PHY4_MII_EN
);
1273 swdev
->ports
= AR7240_NUM_PORTS
- 1;
1275 swdev
->ports
= AR7240_NUM_PORTS
;
1278 pr_err("%s: unsupported chip, ctrl=%08x\n",
1279 dev_name(&mdiodev
->dev
), ctrl
);
1283 swdev
->cpu_port
= AR7240_PORT_CPU
;
1284 swdev
->vlans
= AR7240_MAX_VLANS
;
1285 swdev
->ops
= &ar7240_ops
;
1286 swdev
->alias
= dev_name(&mdiodev
->dev
);
1288 if ((err
= register_switch(&as
->swdev
, NULL
)) < 0)
1291 pr_info("%s: Found an %s\n", dev_name(&mdiodev
->dev
), swdev
->name
);
1293 as
->switch_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
1294 as
->switch_mii_bus
->name
= "ar7240sw_mdio";
1295 as
->switch_mii_bus
->read
= ar7240sw_phy_read
;
1296 as
->switch_mii_bus
->write
= ar7240sw_phy_write
;
1297 as
->switch_mii_bus
->priv
= as
;
1298 as
->switch_mii_bus
->parent
= &mdiodev
->dev
;
1299 snprintf(as
->switch_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s", dev_name(&mdiodev
->dev
));
1302 err
= of_mdiobus_register(as
->switch_mii_bus
, as
->mdio_node
);
1307 /* initialize defaults */
1308 for (i
= 0; i
< AR7240_MAX_VLANS
; i
++)
1311 as
->vlan_table
[0] = ar7240sw_port_mask_all(as
);
1313 ar7240_hw_apply(&as
->swdev
);
1314 rwlock_init(&as
->stats_lock
);
1315 dev_set_drvdata(&mdiodev
->dev
, as
);
1320 ag71xx_ar7240_remove(struct mdio_device
*mdiodev
)
1322 struct ar7240sw
*as
= dev_get_drvdata(&mdiodev
->dev
);
1324 mdiobus_unregister(as
->switch_mii_bus
);
1325 unregister_switch(&as
->swdev
);
1328 static const struct of_device_id ag71xx_sw_of_match
[] = {
1329 { .compatible
= "qca,ar8216-builtin" },
1330 { .compatible
= "qca,ar8229-builtin" },
1334 static struct mdio_driver ag71xx_sw_driver
= {
1335 .probe
= ag71xx_ar7240_probe
,
1336 .remove
= ag71xx_ar7240_remove
,
1338 .name
= "ag71xx-switch",
1339 .of_match_table
= ag71xx_sw_of_match
,
1343 mdio_module_driver(ag71xx_sw_driver
);
1344 MODULE_LICENSE("GPL");