2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
20 #define AG71XX_DEFAULT_MSG_ENABLE \
30 static int ag71xx_msg_level
= -1;
32 module_param_named(msg_level
, ag71xx_msg_level
, int, 0);
33 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
35 #define ETH_SWITCH_HEADER_LEN 2
37 static int ag71xx_tx_packets(struct ag71xx
*ag
, bool flush
);
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu
)
41 return ETH_SWITCH_HEADER_LEN
+ ETH_HLEN
+ VLAN_HLEN
+ mtu
+ ETH_FCS_LEN
;
44 static void ag71xx_dump_dma_regs(struct ag71xx
*ag
)
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
48 ag71xx_rr(ag
, AG71XX_REG_TX_CTRL
),
49 ag71xx_rr(ag
, AG71XX_REG_TX_DESC
),
50 ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
));
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
54 ag71xx_rr(ag
, AG71XX_REG_RX_CTRL
),
55 ag71xx_rr(ag
, AG71XX_REG_RX_DESC
),
56 ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
));
59 static void ag71xx_dump_regs(struct ag71xx
*ag
)
61 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
63 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
64 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
65 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
66 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
67 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
68 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
70 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
71 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
72 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
73 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
75 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
76 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
77 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
78 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
80 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
81 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
82 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
85 static inline void ag71xx_dump_intr(struct ag71xx
*ag
, char *label
, u32 intr
)
87 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
88 ag
->dev
->name
, label
, intr
,
89 (intr
& AG71XX_INT_TX_PS
) ? "TXPS " : "",
90 (intr
& AG71XX_INT_TX_UR
) ? "TXUR " : "",
91 (intr
& AG71XX_INT_TX_BE
) ? "TXBE " : "",
92 (intr
& AG71XX_INT_RX_PR
) ? "RXPR " : "",
93 (intr
& AG71XX_INT_RX_OF
) ? "RXOF " : "",
94 (intr
& AG71XX_INT_RX_BE
) ? "RXBE " : "");
97 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
99 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
100 struct net_device
*dev
= ag
->dev
;
101 int ring_mask
= BIT(ring
->order
) - 1;
102 u32 bytes_compl
= 0, pkts_compl
= 0;
104 while (ring
->curr
!= ring
->dirty
) {
105 struct ag71xx_desc
*desc
;
106 u32 i
= ring
->dirty
& ring_mask
;
108 desc
= ag71xx_ring_desc(ring
, i
);
109 if (!ag71xx_desc_empty(desc
)) {
111 dev
->stats
.tx_errors
++;
114 if (ring
->buf
[i
].skb
) {
115 bytes_compl
+= ring
->buf
[i
].len
;
117 dev_kfree_skb_any(ring
->buf
[i
].skb
);
119 ring
->buf
[i
].skb
= NULL
;
123 /* flush descriptors */
126 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
129 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
131 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
132 int ring_size
= BIT(ring
->order
);
133 int ring_mask
= ring_size
- 1;
136 for (i
= 0; i
< ring_size
; i
++) {
137 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
139 desc
->next
= (u32
) (ring
->descs_dma
+
140 AG71XX_DESC_SIZE
* ((i
+ 1) & ring_mask
));
142 desc
->ctrl
= DESC_EMPTY
;
143 ring
->buf
[i
].skb
= NULL
;
146 /* flush descriptors */
151 netdev_reset_queue(ag
->dev
);
154 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
156 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
157 int ring_size
= BIT(ring
->order
);
163 for (i
= 0; i
< ring_size
; i
++)
164 if (ring
->buf
[i
].rx_buf
) {
165 dma_unmap_single(&ag
->pdev
->dev
, ring
->buf
[i
].dma_addr
,
166 ag
->rx_buf_size
, DMA_FROM_DEVICE
);
167 skb_free_frag(ring
->buf
[i
].rx_buf
);
171 static int ag71xx_buffer_size(struct ag71xx
*ag
)
173 return ag
->rx_buf_size
+
174 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
177 static bool ag71xx_fill_rx_buf(struct ag71xx
*ag
, struct ag71xx_buf
*buf
,
179 void *(*alloc
)(unsigned int size
))
181 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
182 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, buf
- &ring
->buf
[0]);
185 data
= alloc(ag71xx_buffer_size(ag
));
190 buf
->dma_addr
= dma_map_single(&ag
->pdev
->dev
, data
, ag
->rx_buf_size
,
192 desc
->data
= (u32
) buf
->dma_addr
+ offset
;
196 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
198 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
199 int ring_size
= BIT(ring
->order
);
200 int ring_mask
= BIT(ring
->order
) - 1;
205 for (i
= 0; i
< ring_size
; i
++) {
206 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
208 desc
->next
= (u32
) (ring
->descs_dma
+
209 AG71XX_DESC_SIZE
* ((i
+ 1) & ring_mask
));
211 DBG("ag71xx: RX desc at %p, next is %08x\n",
215 for (i
= 0; i
< ring_size
; i
++) {
216 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
218 if (!ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], ag
->rx_buf_offset
,
219 netdev_alloc_frag
)) {
224 desc
->ctrl
= DESC_EMPTY
;
227 /* flush descriptors */
236 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
238 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
239 int ring_mask
= BIT(ring
->order
) - 1;
241 int offset
= ag
->rx_buf_offset
;
244 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
245 struct ag71xx_desc
*desc
;
248 i
= ring
->dirty
& ring_mask
;
249 desc
= ag71xx_ring_desc(ring
, i
);
251 if (!ring
->buf
[i
].rx_buf
&&
252 !ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], offset
,
256 desc
->ctrl
= DESC_EMPTY
;
260 /* flush descriptors */
263 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
268 static int ag71xx_rings_init(struct ag71xx
*ag
)
270 struct ag71xx_ring
*tx
= &ag
->tx_ring
;
271 struct ag71xx_ring
*rx
= &ag
->rx_ring
;
272 int ring_size
= BIT(tx
->order
) + BIT(rx
->order
);
273 int tx_size
= BIT(tx
->order
);
275 tx
->buf
= kzalloc(ring_size
* sizeof(*tx
->buf
), GFP_KERNEL
);
279 tx
->descs_cpu
= dma_alloc_coherent(&ag
->pdev
->dev
, ring_size
* AG71XX_DESC_SIZE
,
280 &tx
->descs_dma
, GFP_ATOMIC
);
281 if (!tx
->descs_cpu
) {
287 rx
->buf
= &tx
->buf
[BIT(tx
->order
)];
288 rx
->descs_cpu
= ((void *)tx
->descs_cpu
) + tx_size
* AG71XX_DESC_SIZE
;
289 rx
->descs_dma
= tx
->descs_dma
+ tx_size
* AG71XX_DESC_SIZE
;
291 ag71xx_ring_tx_init(ag
);
292 return ag71xx_ring_rx_init(ag
);
295 static void ag71xx_rings_free(struct ag71xx
*ag
)
297 struct ag71xx_ring
*tx
= &ag
->tx_ring
;
298 struct ag71xx_ring
*rx
= &ag
->rx_ring
;
299 int ring_size
= BIT(tx
->order
) + BIT(rx
->order
);
302 dma_free_coherent(&ag
->pdev
->dev
, ring_size
* AG71XX_DESC_SIZE
,
303 tx
->descs_cpu
, tx
->descs_dma
);
307 tx
->descs_cpu
= NULL
;
308 rx
->descs_cpu
= NULL
;
313 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
315 ag71xx_ring_rx_clean(ag
);
316 ag71xx_ring_tx_clean(ag
);
317 ag71xx_rings_free(ag
);
319 netdev_reset_queue(ag
->dev
);
322 static unsigned char *ag71xx_speed_str(struct ag71xx
*ag
)
336 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
340 t
= (((u32
) mac
[5]) << 24) | (((u32
) mac
[4]) << 16)
341 | (((u32
) mac
[3]) << 8) | ((u32
) mac
[2]);
343 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
345 t
= (((u32
) mac
[1]) << 24) | (((u32
) mac
[0]) << 16);
346 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
349 static void ag71xx_dma_reset(struct ag71xx
*ag
)
354 ag71xx_dump_dma_regs(ag
);
357 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
358 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
361 * give the hardware some time to really stop all rx/tx activity
362 * clearing the descriptors too early causes random memory corruption
366 /* clear descriptor addresses */
367 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->stop_desc_dma
);
368 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->stop_desc_dma
);
370 /* clear pending RX/TX interrupts */
371 for (i
= 0; i
< 256; i
++) {
372 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
373 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
376 /* clear pending errors */
377 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
| RX_STATUS_OF
);
378 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
| TX_STATUS_UR
);
380 val
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
382 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
385 val
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
387 /* mask out reserved bits */
391 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
394 ag71xx_dump_dma_regs(ag
);
397 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
398 MAC_CFG1_SRX | MAC_CFG1_STX)
400 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
402 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
403 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
404 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
405 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
406 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
409 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
410 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
411 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
412 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
413 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
414 FIFO_CFG5_17 | FIFO_CFG5_SF)
416 static void ag71xx_hw_stop(struct ag71xx
*ag
)
418 /* disable all interrupts and stop the rx/tx engine */
419 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
420 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
421 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
424 static void ag71xx_hw_setup(struct ag71xx
*ag
)
426 struct device_node
*np
= ag
->pdev
->dev
.of_node
;
427 u32 init
= MAC_CFG1_INIT
;
429 /* setup MAC configuration registers */
430 if (of_property_read_bool(np
, "flow-control"))
431 init
|= MAC_CFG1_TFC
| MAC_CFG1_RFC
;
432 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, init
);
434 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
435 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
437 /* setup max frame length to zero */
438 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, 0);
440 /* setup FIFO configuration registers */
441 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
442 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, ag
->fifodata
[0]);
443 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, ag
->fifodata
[1]);
444 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, FIFO_CFG4_INIT
);
445 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, FIFO_CFG5_INIT
);
448 static void ag71xx_hw_init(struct ag71xx
*ag
)
452 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
455 reset_control_assert(ag
->mac_reset
);
457 reset_control_assert(ag
->mdio_reset
);
459 reset_control_deassert(ag
->mac_reset
);
461 reset_control_deassert(ag
->mdio_reset
);
466 ag71xx_dma_reset(ag
);
469 static void ag71xx_fast_reset(struct ag71xx
*ag
)
471 struct net_device
*dev
= ag
->dev
;
478 mii_reg
= ag71xx_rr(ag
, AG71XX_REG_MII_CFG
);
479 rx_ds
= ag71xx_rr(ag
, AG71XX_REG_RX_DESC
);
481 ag71xx_tx_packets(ag
, true);
483 reset_control_assert(ag
->mac_reset
);
485 reset_control_deassert(ag
->mac_reset
);
488 ag71xx_dma_reset(ag
);
490 ag
->tx_ring
.curr
= 0;
491 ag
->tx_ring
.dirty
= 0;
492 netdev_reset_queue(ag
->dev
);
494 /* setup max frame length */
495 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
,
496 ag71xx_max_frame_len(ag
->dev
->mtu
));
498 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, rx_ds
);
499 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
500 ag71xx_wr(ag
, AG71XX_REG_MII_CFG
, mii_reg
);
502 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
505 static void ag71xx_hw_start(struct ag71xx
*ag
)
507 /* start RX engine */
508 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
510 /* enable interrupts */
511 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
513 netif_wake_queue(ag
->dev
);
516 static void ath79_set_pllval(struct ag71xx
*ag
)
518 u32 pll_reg
= ag
->pllreg
[1];
526 pll_val
= ag
->plldata
[2];
529 pll_val
= ag
->plldata
[1];
532 pll_val
= ag
->plldata
[0];
539 regmap_write(ag
->pllregmap
, pll_reg
, pll_val
);
542 static void ath79_set_pll(struct ag71xx
*ag
)
544 u32 pll_cfg
= ag
->pllreg
[0];
545 u32 pll_shift
= ag
->pllreg
[2];
550 regmap_update_bits(ag
->pllregmap
, pll_cfg
, 3 << pll_shift
, 2 << pll_shift
);
553 ath79_set_pllval(ag
);
555 regmap_update_bits(ag
->pllregmap
, pll_cfg
, 3 << pll_shift
, 3 << pll_shift
);
558 regmap_update_bits(ag
->pllregmap
, pll_cfg
, 3 << pll_shift
, 0);
562 static void ath79_mii_ctrl_set_if(struct ag71xx
*ag
, unsigned int mii_if
)
566 t
= __raw_readl(ag
->mii_base
);
567 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
568 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
569 __raw_writel(t
, ag
->mii_base
);
572 static void ath79_mii0_ctrl_set_if(struct ag71xx
*ag
)
576 switch (ag
->phy_if_mode
) {
577 case PHY_INTERFACE_MODE_MII
:
578 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
580 case PHY_INTERFACE_MODE_GMII
:
581 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
583 case PHY_INTERFACE_MODE_RGMII
:
584 case PHY_INTERFACE_MODE_RGMII_ID
:
585 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
587 case PHY_INTERFACE_MODE_RMII
:
588 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
591 WARN(1, "Impossible PHY mode defined.\n");
595 ath79_mii_ctrl_set_if(ag
, mii_if
);
598 static void ath79_mii1_ctrl_set_if(struct ag71xx
*ag
)
602 switch (ag
->phy_if_mode
) {
603 case PHY_INTERFACE_MODE_RMII
:
604 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
606 case PHY_INTERFACE_MODE_RGMII
:
607 case PHY_INTERFACE_MODE_RGMII_ID
:
608 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
611 WARN(1, "Impossible PHY mode defined.\n");
615 ath79_mii_ctrl_set_if(ag
, mii_if
);
618 static void ath79_mii_ctrl_set_speed(struct ag71xx
*ag
)
620 unsigned int mii_speed
;
628 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
631 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
634 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
640 t
= __raw_readl(ag
->mii_base
);
641 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
642 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
643 __raw_writel(t
, ag
->mii_base
);
647 __ag71xx_link_adjust(struct ag71xx
*ag
, bool update
)
649 struct device_node
*np
= ag
->pdev
->dev
.of_node
;
654 if (!ag
->link
&& update
) {
656 netif_carrier_off(ag
->dev
);
657 if (netif_msg_link(ag
))
658 pr_info("%s: link down\n", ag
->dev
->name
);
662 if (!of_device_is_compatible(np
, "qca,ar9130-eth") &&
663 !of_device_is_compatible(np
, "qca,ar7100-eth"))
664 ag71xx_fast_reset(ag
);
666 cfg2
= ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
);
667 cfg2
&= ~(MAC_CFG2_IF_1000
| MAC_CFG2_IF_10_100
| MAC_CFG2_FDX
);
668 cfg2
|= (ag
->duplex
) ? MAC_CFG2_FDX
: 0;
670 ifctl
= ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
);
671 ifctl
&= ~(MAC_IFCTL_SPEED
);
673 fifo5
= ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
);
674 fifo5
&= ~FIFO_CFG5_BM
;
678 cfg2
|= MAC_CFG2_IF_1000
;
679 fifo5
|= FIFO_CFG5_BM
;
682 cfg2
|= MAC_CFG2_IF_10_100
;
683 ifctl
|= MAC_IFCTL_SPEED
;
686 cfg2
|= MAC_CFG2_IF_10_100
;
693 if (ag
->tx_ring
.desc_split
) {
694 ag
->fifodata
[2] &= 0xffff;
695 ag
->fifodata
[2] |= ((2048 - ag
->tx_ring
.desc_split
) / 4) << 16;
698 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, ag
->fifodata
[2]);
701 if (of_device_is_compatible(np
, "qca,ar7100-eth") ||
702 of_device_is_compatible(np
, "qca,ar9130-eth")) {
704 ath79_mii_ctrl_set_speed(ag
);
705 } else if (of_device_is_compatible(np
, "qca,ar7242-eth") ||
706 of_device_is_compatible(np
, "qca,ar9340-eth") ||
707 of_device_is_compatible(np
, "qca,qca9550-eth") ||
708 of_device_is_compatible(np
, "qca,qca9560-eth")) {
709 ath79_set_pllval(ag
);
713 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG2
, cfg2
);
714 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, fifo5
);
715 ag71xx_wr(ag
, AG71XX_REG_MAC_IFCTL
, ifctl
);
717 if (of_device_is_compatible(np
, "qca,qca9530-eth") ||
718 of_device_is_compatible(np
, "qca,qca9560-eth")) {
720 * The rx ring buffer can stall on small packets on QCA953x and
721 * QCA956x. Disabling the inline checksum engine fixes the stall.
722 * The wr, rr functions cannot be used since this hidden register
723 * is outside of the normal ag71xx register block.
725 void __iomem
*dam
= ioremap_nocache(0xb90001bc, 0x4);
727 __raw_writel(__raw_readl(dam
) & ~BIT(27), dam
);
728 (void)__raw_readl(dam
);
735 netif_carrier_on(ag
->dev
);
736 if (update
&& netif_msg_link(ag
))
737 pr_info("%s: link up (%sMbps/%s duplex)\n",
739 ag71xx_speed_str(ag
),
740 (DUPLEX_FULL
== ag
->duplex
) ? "Full" : "Half");
742 ag71xx_dump_regs(ag
);
745 void ag71xx_link_adjust(struct ag71xx
*ag
)
747 __ag71xx_link_adjust(ag
, true);
750 static int ag71xx_hw_enable(struct ag71xx
*ag
)
754 ret
= ag71xx_rings_init(ag
);
758 napi_enable(&ag
->napi
);
759 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
760 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
761 netif_start_queue(ag
->dev
);
766 static void ag71xx_hw_disable(struct ag71xx
*ag
)
770 spin_lock_irqsave(&ag
->lock
, flags
);
772 netif_stop_queue(ag
->dev
);
775 ag71xx_dma_reset(ag
);
777 napi_disable(&ag
->napi
);
778 del_timer_sync(&ag
->oom_timer
);
780 spin_unlock_irqrestore(&ag
->lock
, flags
);
782 ag71xx_rings_cleanup(ag
);
785 static int ag71xx_open(struct net_device
*dev
)
787 struct ag71xx
*ag
= netdev_priv(dev
);
788 unsigned int max_frame_len
;
791 netif_carrier_off(dev
);
792 max_frame_len
= ag71xx_max_frame_len(dev
->mtu
);
793 ag
->rx_buf_size
= SKB_DATA_ALIGN(max_frame_len
+ NET_SKB_PAD
+ NET_IP_ALIGN
);
795 /* setup max frame length */
796 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, max_frame_len
);
797 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
799 ret
= ag71xx_hw_enable(ag
);
803 phy_start(ag
->phy_dev
);
808 ag71xx_rings_cleanup(ag
);
812 static int ag71xx_stop(struct net_device
*dev
)
815 struct ag71xx
*ag
= netdev_priv(dev
);
817 netif_carrier_off(dev
);
818 phy_stop(ag
->phy_dev
);
820 spin_lock_irqsave(&ag
->lock
, flags
);
823 ag71xx_link_adjust(ag
);
825 spin_unlock_irqrestore(&ag
->lock
, flags
);
827 ag71xx_hw_disable(ag
);
832 static int ag71xx_fill_dma_desc(struct ag71xx_ring
*ring
, u32 addr
, int len
)
835 struct ag71xx_desc
*desc
;
836 int ring_mask
= BIT(ring
->order
) - 1;
838 int split
= ring
->desc_split
;
844 unsigned int cur_len
= len
;
846 i
= (ring
->curr
+ ndesc
) & ring_mask
;
847 desc
= ag71xx_ring_desc(ring
, i
);
849 if (!ag71xx_desc_empty(desc
))
852 if (cur_len
> split
) {
856 * TX will hang if DMA transfers <= 4 bytes,
857 * make sure next segment is more than 4 bytes long.
859 if (len
<= split
+ 4)
868 cur_len
|= DESC_MORE
;
870 /* prevent early tx attempt of this descriptor */
872 cur_len
|= DESC_EMPTY
;
874 desc
->ctrl
= cur_len
;
881 static netdev_tx_t
ag71xx_hard_start_xmit(struct sk_buff
*skb
,
882 struct net_device
*dev
)
884 struct ag71xx
*ag
= netdev_priv(dev
);
885 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
886 int ring_mask
= BIT(ring
->order
) - 1;
887 int ring_size
= BIT(ring
->order
);
888 struct ag71xx_desc
*desc
;
893 DBG("%s: packet len is too small\n", ag
->dev
->name
);
897 dma_addr
= dma_map_single(&ag
->pdev
->dev
, skb
->data
, skb
->len
,
900 i
= ring
->curr
& ring_mask
;
901 desc
= ag71xx_ring_desc(ring
, i
);
903 /* setup descriptor fields */
904 n
= ag71xx_fill_dma_desc(ring
, (u32
) dma_addr
, skb
->len
& ag
->desc_pktlen_mask
);
908 i
= (ring
->curr
+ n
- 1) & ring_mask
;
909 ring
->buf
[i
].len
= skb
->len
;
910 ring
->buf
[i
].skb
= skb
;
912 netdev_sent_queue(dev
, skb
->len
);
914 skb_tx_timestamp(skb
);
916 desc
->ctrl
&= ~DESC_EMPTY
;
919 /* flush descriptor */
923 if (ring
->desc_split
)
924 ring_min
*= AG71XX_TX_RING_DS_PER_PKT
;
926 if (ring
->curr
- ring
->dirty
>= ring_size
- ring_min
) {
927 DBG("%s: tx queue full\n", dev
->name
);
928 netif_stop_queue(dev
);
931 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
933 /* enable TX engine */
934 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
939 dma_unmap_single(&ag
->pdev
->dev
, dma_addr
, skb
->len
, DMA_TO_DEVICE
);
942 dev
->stats
.tx_dropped
++;
948 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
950 struct ag71xx
*ag
= netdev_priv(dev
);
956 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
962 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
969 if (ag
->phy_dev
== NULL
)
972 return phy_mii_ioctl(ag
->phy_dev
, ifr
, cmd
);
981 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
982 static void ag71xx_oom_timer_handler(unsigned long data
)
984 struct net_device
*dev
= (struct net_device
*) data
;
985 struct ag71xx
*ag
= netdev_priv(dev
);
987 static void ag71xx_oom_timer_handler(struct timer_list
*t
)
989 struct ag71xx
*ag
= from_timer(ag
, t
, oom_timer
);
992 napi_schedule(&ag
->napi
);
995 static void ag71xx_tx_timeout(struct net_device
*dev
)
997 struct ag71xx
*ag
= netdev_priv(dev
);
999 if (netif_msg_tx_err(ag
))
1000 pr_info("%s: tx timeout\n", ag
->dev
->name
);
1002 schedule_delayed_work(&ag
->restart_work
, 1);
1005 static void ag71xx_restart_work_func(struct work_struct
*work
)
1007 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, restart_work
.work
);
1010 ag71xx_hw_disable(ag
);
1011 ag71xx_hw_enable(ag
);
1013 __ag71xx_link_adjust(ag
, false);
1017 static bool ag71xx_check_dma_stuck(struct ag71xx
*ag
)
1019 unsigned long timestamp
;
1020 u32 rx_sm
, tx_sm
, rx_fd
;
1022 timestamp
= netdev_get_tx_queue(ag
->dev
, 0)->trans_start
;
1023 if (likely(time_before(jiffies
, timestamp
+ HZ
/10)))
1026 if (!netif_carrier_ok(ag
->dev
))
1029 rx_sm
= ag71xx_rr(ag
, AG71XX_REG_RX_SM
);
1030 if ((rx_sm
& 0x7) == 0x3 && ((rx_sm
>> 4) & 0x7) == 0x6)
1033 tx_sm
= ag71xx_rr(ag
, AG71XX_REG_TX_SM
);
1034 rx_fd
= ag71xx_rr(ag
, AG71XX_REG_FIFO_DEPTH
);
1035 if (((tx_sm
>> 4) & 0x7) == 0 && ((rx_sm
& 0x7) == 0) &&
1036 ((rx_sm
>> 4) & 0x7) == 0 && rx_fd
== 0)
1042 static int ag71xx_tx_packets(struct ag71xx
*ag
, bool flush
)
1044 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
1045 bool dma_stuck
= false;
1046 int ring_mask
= BIT(ring
->order
) - 1;
1047 int ring_size
= BIT(ring
->order
);
1049 int bytes_compl
= 0;
1052 DBG("%s: processing TX ring\n", ag
->dev
->name
);
1054 while (ring
->dirty
+ n
!= ring
->curr
) {
1055 unsigned int i
= (ring
->dirty
+ n
) & ring_mask
;
1056 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
1057 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
1059 if (!flush
&& !ag71xx_desc_empty(desc
)) {
1060 if (ag
->tx_hang_workaround
&&
1061 ag71xx_check_dma_stuck(ag
)) {
1062 schedule_delayed_work(&ag
->restart_work
, HZ
/ 2);
1069 desc
->ctrl
|= DESC_EMPTY
;
1075 dev_kfree_skb_any(skb
);
1076 ring
->buf
[i
].skb
= NULL
;
1078 bytes_compl
+= ring
->buf
[i
].len
;
1084 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
1089 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
1094 ag
->dev
->stats
.tx_bytes
+= bytes_compl
;
1095 ag
->dev
->stats
.tx_packets
+= sent
;
1097 netdev_completed_queue(ag
->dev
, sent
, bytes_compl
);
1098 if ((ring
->curr
- ring
->dirty
) < (ring_size
* 3) / 4)
1099 netif_wake_queue(ag
->dev
);
1102 cancel_delayed_work(&ag
->restart_work
);
1107 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
1109 struct net_device
*dev
= ag
->dev
;
1110 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
1111 unsigned int pktlen_mask
= ag
->desc_pktlen_mask
;
1112 unsigned int offset
= ag
->rx_buf_offset
;
1113 int ring_mask
= BIT(ring
->order
) - 1;
1114 int ring_size
= BIT(ring
->order
);
1115 struct sk_buff_head queue
;
1116 struct sk_buff
*skb
;
1119 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1120 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
1122 skb_queue_head_init(&queue
);
1124 while (done
< limit
) {
1125 unsigned int i
= ring
->curr
& ring_mask
;
1126 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
1130 if (ag71xx_desc_empty(desc
))
1133 if ((ring
->dirty
+ ring_size
) == ring
->curr
) {
1138 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
1140 pktlen
= desc
->ctrl
& pktlen_mask
;
1141 pktlen
-= ETH_FCS_LEN
;
1143 dma_unmap_single(&ag
->pdev
->dev
, ring
->buf
[i
].dma_addr
,
1144 ag
->rx_buf_size
, DMA_FROM_DEVICE
);
1146 dev
->stats
.rx_packets
++;
1147 dev
->stats
.rx_bytes
+= pktlen
;
1149 skb
= build_skb(ring
->buf
[i
].rx_buf
, ag71xx_buffer_size(ag
));
1151 skb_free_frag(ring
->buf
[i
].rx_buf
);
1155 skb_reserve(skb
, offset
);
1156 skb_put(skb
, pktlen
);
1159 dev
->stats
.rx_dropped
++;
1163 skb
->ip_summed
= CHECKSUM_NONE
;
1164 __skb_queue_tail(&queue
, skb
);
1168 ring
->buf
[i
].rx_buf
= NULL
;
1174 ag71xx_ring_rx_refill(ag
);
1176 while ((skb
= __skb_dequeue(&queue
)) != NULL
) {
1177 skb
->protocol
= eth_type_trans(skb
, dev
);
1178 netif_receive_skb(skb
);
1181 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1182 dev
->name
, ring
->curr
, ring
->dirty
, done
);
1187 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
1189 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
1190 struct net_device
*dev
= ag
->dev
;
1191 struct ag71xx_ring
*rx_ring
= &ag
->rx_ring
;
1192 int rx_ring_size
= BIT(rx_ring
->order
);
1193 unsigned long flags
;
1198 tx_done
= ag71xx_tx_packets(ag
, false);
1200 DBG("%s: processing RX ring\n", dev
->name
);
1201 rx_done
= ag71xx_rx_packets(ag
, limit
);
1203 ag71xx_debugfs_update_napi_stats(ag
, rx_done
, tx_done
);
1205 if (rx_ring
->buf
[rx_ring
->dirty
% rx_ring_size
].rx_buf
== NULL
)
1208 status
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
1209 if (unlikely(status
& RX_STATUS_OF
)) {
1210 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
1211 dev
->stats
.rx_fifo_errors
++;
1214 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
1217 if (rx_done
< limit
) {
1218 if (status
& RX_STATUS_PR
)
1221 status
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
1222 if (status
& TX_STATUS_PS
)
1225 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1226 dev
->name
, rx_done
, tx_done
, limit
);
1228 napi_complete(napi
);
1230 /* enable interrupts */
1231 spin_lock_irqsave(&ag
->lock
, flags
);
1232 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
1233 spin_unlock_irqrestore(&ag
->lock
, flags
);
1238 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1239 dev
->name
, rx_done
, tx_done
, limit
);
1243 if (netif_msg_rx_err(ag
))
1244 pr_info("%s: out of memory\n", dev
->name
);
1246 mod_timer(&ag
->oom_timer
, jiffies
+ AG71XX_OOM_REFILL
);
1247 napi_complete(napi
);
1251 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
1253 struct net_device
*dev
= dev_id
;
1254 struct ag71xx
*ag
= netdev_priv(dev
);
1257 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
1258 ag71xx_dump_intr(ag
, "raw", status
);
1260 if (unlikely(!status
))
1263 if (unlikely(status
& AG71XX_INT_ERR
)) {
1264 if (status
& AG71XX_INT_TX_BE
) {
1265 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
1266 dev_err(&dev
->dev
, "TX BUS error\n");
1268 if (status
& AG71XX_INT_RX_BE
) {
1269 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
1270 dev_err(&dev
->dev
, "RX BUS error\n");
1274 if (likely(status
& AG71XX_INT_POLL
)) {
1275 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
1276 DBG("%s: enable polling mode\n", dev
->name
);
1277 napi_schedule(&ag
->napi
);
1280 ag71xx_debugfs_update_int_stats(ag
, status
);
1285 static int ag71xx_change_mtu(struct net_device
*dev
, int new_mtu
)
1287 struct ag71xx
*ag
= netdev_priv(dev
);
1290 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
,
1291 ag71xx_max_frame_len(dev
->mtu
));
1296 static const struct net_device_ops ag71xx_netdev_ops
= {
1297 .ndo_open
= ag71xx_open
,
1298 .ndo_stop
= ag71xx_stop
,
1299 .ndo_start_xmit
= ag71xx_hard_start_xmit
,
1300 .ndo_do_ioctl
= ag71xx_do_ioctl
,
1301 .ndo_tx_timeout
= ag71xx_tx_timeout
,
1302 .ndo_change_mtu
= ag71xx_change_mtu
,
1303 .ndo_set_mac_address
= eth_mac_addr
,
1304 .ndo_validate_addr
= eth_validate_addr
,
1307 static int ag71xx_probe(struct platform_device
*pdev
)
1309 struct device_node
*np
= pdev
->dev
.of_node
;
1310 struct net_device
*dev
;
1311 struct resource
*res
;
1313 const void *mac_addr
;
1320 dev
= devm_alloc_etherdev(&pdev
->dev
, sizeof(*ag
));
1324 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1328 err
= ag71xx_setup_gmac(np
);
1332 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1334 ag
= netdev_priv(dev
);
1337 ag
->msg_enable
= netif_msg_init(ag71xx_msg_level
,
1338 AG71XX_DEFAULT_MSG_ENABLE
);
1339 spin_lock_init(&ag
->lock
);
1341 ag
->mac_reset
= devm_reset_control_get_exclusive(&pdev
->dev
, "mac");
1342 if (IS_ERR(ag
->mac_reset
)) {
1343 dev_err(&pdev
->dev
, "missing mac reset\n");
1344 return PTR_ERR(ag
->mac_reset
);
1347 ag
->mdio_reset
= devm_reset_control_get_optional_exclusive(&pdev
->dev
, "mdio");
1349 if (of_property_read_u32_array(np
, "fifo-data", ag
->fifodata
, 3)) {
1350 if (of_device_is_compatible(np
, "qca,ar9130-eth") ||
1351 of_device_is_compatible(np
, "qca,ar7100-eth")) {
1352 ag
->fifodata
[0] = 0x0fff0000;
1353 ag
->fifodata
[1] = 0x00001fff;
1355 ag
->fifodata
[0] = 0x0010ffff;
1356 ag
->fifodata
[1] = 0x015500aa;
1357 ag
->fifodata
[2] = 0x01f00140;
1359 if (of_device_is_compatible(np
, "qca,ar9130-eth"))
1360 ag
->fifodata
[2] = 0x00780fff;
1361 else if (of_device_is_compatible(np
, "qca,ar7100-eth"))
1362 ag
->fifodata
[2] = 0x008001ff;
1365 if (of_property_read_u32_array(np
, "pll-data", ag
->plldata
, 3))
1366 dev_dbg(&pdev
->dev
, "failed to read pll-data property\n");
1368 if (of_property_read_u32_array(np
, "pll-reg", ag
->pllreg
, 3))
1369 dev_dbg(&pdev
->dev
, "failed to read pll-reg property\n");
1371 ag
->pllregmap
= syscon_regmap_lookup_by_phandle(np
, "pll-handle");
1372 if (IS_ERR(ag
->pllregmap
)) {
1373 dev_dbg(&pdev
->dev
, "failed to read pll-handle property\n");
1374 ag
->pllregmap
= NULL
;
1377 ag
->mac_base
= devm_ioremap_nocache(&pdev
->dev
, res
->start
,
1378 res
->end
- res
->start
+ 1);
1382 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1384 ag
->mii_base
= devm_ioremap_nocache(&pdev
->dev
, res
->start
,
1385 res
->end
- res
->start
+ 1);
1390 dev
->irq
= platform_get_irq(pdev
, 0);
1391 err
= devm_request_irq(&pdev
->dev
, dev
->irq
, ag71xx_interrupt
,
1392 0x0, dev_name(&pdev
->dev
), dev
);
1394 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
1398 dev
->netdev_ops
= &ag71xx_netdev_ops
;
1399 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
1401 INIT_DELAYED_WORK(&ag
->restart_work
, ag71xx_restart_work_func
);
1403 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
1404 init_timer(&ag
->oom_timer
);
1405 ag
->oom_timer
.data
= (unsigned long) dev
;
1406 ag
->oom_timer
.function
= ag71xx_oom_timer_handler
;
1408 timer_setup(&ag
->oom_timer
, ag71xx_oom_timer_handler
, 0);
1411 tx_size
= AG71XX_TX_RING_SIZE_DEFAULT
;
1412 ag
->rx_ring
.order
= ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT
);
1414 if (of_device_is_compatible(np
, "qca,ar9340-eth") ||
1415 of_device_is_compatible(np
, "qca,qca9530-eth") ||
1416 of_device_is_compatible(np
, "qca,qca9550-eth") ||
1417 of_device_is_compatible(np
, "qca,qca9560-eth"))
1418 ag
->desc_pktlen_mask
= SZ_16K
- 1;
1420 ag
->desc_pktlen_mask
= SZ_4K
- 1;
1422 if (ag
->desc_pktlen_mask
== SZ_16K
- 1 &&
1423 !of_device_is_compatible(np
, "qca,qca9550-eth") &&
1424 !of_device_is_compatible(np
, "qca,qca9560-eth"))
1425 max_frame_len
= ag
->desc_pktlen_mask
;
1427 max_frame_len
= 1540;
1430 dev
->max_mtu
= max_frame_len
- ag71xx_max_frame_len(0);
1432 if (of_device_is_compatible(np
, "qca,ar7240-eth") ||
1433 of_device_is_compatible(np
, "qca,ar7241-eth") ||
1434 of_device_is_compatible(np
, "qca,ar7242-eth") ||
1435 of_device_is_compatible(np
, "qca,ar9330-eth") ||
1436 of_device_is_compatible(np
, "qca,ar9340-eth") ||
1437 of_device_is_compatible(np
, "qca,qca9530-eth") ||
1438 of_device_is_compatible(np
, "qca,qca9550-eth") ||
1439 of_device_is_compatible(np
, "qca,qca9560-eth"))
1440 ag
->tx_hang_workaround
= 1;
1442 ag
->rx_buf_offset
= NET_SKB_PAD
;
1443 if (!of_device_is_compatible(np
, "qca,ar7100-eth") &&
1444 !of_device_is_compatible(np
, "qca,ar9130-eth"))
1445 ag
->rx_buf_offset
+= NET_IP_ALIGN
;
1447 if (of_device_is_compatible(np
, "qca,ar7100-eth")) {
1448 ag
->tx_ring
.desc_split
= AG71XX_TX_RING_SPLIT
;
1449 tx_size
*= AG71XX_TX_RING_DS_PER_PKT
;
1451 ag
->tx_ring
.order
= ag71xx_ring_size_order(tx_size
);
1453 ag
->stop_desc
= dmam_alloc_coherent(&pdev
->dev
,
1454 sizeof(struct ag71xx_desc
),
1455 &ag
->stop_desc_dma
, GFP_KERNEL
);
1459 ag
->stop_desc
->data
= 0;
1460 ag
->stop_desc
->ctrl
= 0;
1461 ag
->stop_desc
->next
= (u32
) ag
->stop_desc_dma
;
1463 mac_addr
= of_get_mac_address(np
);
1465 memcpy(dev
->dev_addr
, mac_addr
, ETH_ALEN
);
1466 if (!mac_addr
|| !is_valid_ether_addr(dev
->dev_addr
)) {
1467 dev_err(&pdev
->dev
, "invalid MAC address, using random address\n");
1468 eth_random_addr(dev
->dev_addr
);
1471 ag
->phy_if_mode
= of_get_phy_mode(np
);
1472 if (ag
->phy_if_mode
< 0) {
1473 dev_err(&pdev
->dev
, "missing phy-mode property in DT\n");
1474 return ag
->phy_if_mode
;
1477 if (of_property_read_u32(np
, "qca,mac-idx", &ag
->mac_idx
))
1480 switch (ag
->mac_idx
) {
1482 ath79_mii0_ctrl_set_if(ag
);
1485 ath79_mii1_ctrl_set_if(ag
);
1491 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
1493 ag71xx_dump_regs(ag
);
1495 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, 0);
1499 ag71xx_dump_regs(ag
);
1502 * populate current node to register mdio-bus as a subdevice.
1503 * the mdio bus works independently on ar7241 and later chips
1504 * and we need to load mdio1 before gmac0, which can be done
1505 * by adding a "simple-mfd" compatible to gmac node. The
1506 * following code checks OF_POPULATED_BUS flag before populating
1507 * to avoid duplicated population.
1509 if (!of_node_check_flag(np
, OF_POPULATED_BUS
)) {
1510 err
= of_platform_populate(np
, NULL
, NULL
, &pdev
->dev
);
1515 err
= ag71xx_phy_connect(ag
);
1519 err
= ag71xx_debugfs_init(ag
);
1521 goto err_phy_disconnect
;
1523 platform_set_drvdata(pdev
, dev
);
1525 err
= register_netdev(dev
);
1527 dev_err(&pdev
->dev
, "unable to register net device\n");
1528 platform_set_drvdata(pdev
, NULL
);
1529 ag71xx_debugfs_exit(ag
);
1530 goto err_phy_disconnect
;
1533 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1534 dev
->name
, (unsigned long) ag
->mac_base
, dev
->irq
,
1535 phy_modes(ag
->phy_if_mode
));
1540 ag71xx_phy_disconnect(ag
);
1544 static int ag71xx_remove(struct platform_device
*pdev
)
1546 struct net_device
*dev
= platform_get_drvdata(pdev
);
1552 ag
= netdev_priv(dev
);
1553 ag71xx_debugfs_exit(ag
);
1554 ag71xx_phy_disconnect(ag
);
1555 unregister_netdev(dev
);
1556 platform_set_drvdata(pdev
, NULL
);
1560 static const struct of_device_id ag71xx_match
[] = {
1561 { .compatible
= "qca,ar7100-eth" },
1562 { .compatible
= "qca,ar7240-eth" },
1563 { .compatible
= "qca,ar7241-eth" },
1564 { .compatible
= "qca,ar7242-eth" },
1565 { .compatible
= "qca,ar9130-eth" },
1566 { .compatible
= "qca,ar9330-eth" },
1567 { .compatible
= "qca,ar9340-eth" },
1568 { .compatible
= "qca,qca9530-eth" },
1569 { .compatible
= "qca,qca9550-eth" },
1570 { .compatible
= "qca,qca9560-eth" },
1574 static struct platform_driver ag71xx_driver
= {
1575 .probe
= ag71xx_probe
,
1576 .remove
= ag71xx_remove
,
1578 .name
= AG71XX_DRV_NAME
,
1579 .of_match_table
= ag71xx_match
,
1583 static int __init
ag71xx_module_init(void)
1587 ret
= ag71xx_debugfs_root_init();
1591 ret
= platform_driver_register(&ag71xx_driver
);
1593 goto err_debugfs_exit
;
1598 ag71xx_debugfs_root_exit();
1603 static void __exit
ag71xx_module_exit(void)
1605 platform_driver_unregister(&ag71xx_driver
);
1606 ag71xx_debugfs_root_exit();
1609 module_init(ag71xx_module_init
);
1610 module_exit(ag71xx_module_exit
);
1612 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1613 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1614 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1615 MODULE_LICENSE("GPL v2");
1616 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);