2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
20 #define AG71XX_DEFAULT_MSG_ENABLE \
30 static int ag71xx_msg_level
= -1;
32 module_param_named(msg_level
, ag71xx_msg_level
, int, 0);
33 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
35 #define ETH_SWITCH_HEADER_LEN 2
37 static int ag71xx_tx_packets(struct ag71xx
*ag
, bool flush
);
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu
)
41 return ETH_SWITCH_HEADER_LEN
+ ETH_HLEN
+ VLAN_HLEN
+ mtu
+ ETH_FCS_LEN
;
44 static void ag71xx_dump_dma_regs(struct ag71xx
*ag
)
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
48 ag71xx_rr(ag
, AG71XX_REG_TX_CTRL
),
49 ag71xx_rr(ag
, AG71XX_REG_TX_DESC
),
50 ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
));
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
54 ag71xx_rr(ag
, AG71XX_REG_RX_CTRL
),
55 ag71xx_rr(ag
, AG71XX_REG_RX_DESC
),
56 ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
));
59 static void ag71xx_dump_regs(struct ag71xx
*ag
)
61 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
63 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
64 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
65 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
66 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
67 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
68 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
70 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
71 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
72 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
73 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
75 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
76 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
77 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
78 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
80 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
81 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
82 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
85 static inline void ag71xx_dump_intr(struct ag71xx
*ag
, char *label
, u32 intr
)
87 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
88 ag
->dev
->name
, label
, intr
,
89 (intr
& AG71XX_INT_TX_PS
) ? "TXPS " : "",
90 (intr
& AG71XX_INT_TX_UR
) ? "TXUR " : "",
91 (intr
& AG71XX_INT_TX_BE
) ? "TXBE " : "",
92 (intr
& AG71XX_INT_RX_PR
) ? "RXPR " : "",
93 (intr
& AG71XX_INT_RX_OF
) ? "RXOF " : "",
94 (intr
& AG71XX_INT_RX_BE
) ? "RXBE " : "");
97 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
99 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
100 struct net_device
*dev
= ag
->dev
;
101 int ring_mask
= BIT(ring
->order
) - 1;
102 u32 bytes_compl
= 0, pkts_compl
= 0;
104 while (ring
->curr
!= ring
->dirty
) {
105 struct ag71xx_desc
*desc
;
106 u32 i
= ring
->dirty
& ring_mask
;
108 desc
= ag71xx_ring_desc(ring
, i
);
109 if (!ag71xx_desc_empty(desc
)) {
111 dev
->stats
.tx_errors
++;
114 if (ring
->buf
[i
].skb
) {
115 bytes_compl
+= ring
->buf
[i
].len
;
117 dev_kfree_skb_any(ring
->buf
[i
].skb
);
119 ring
->buf
[i
].skb
= NULL
;
123 /* flush descriptors */
126 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
129 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
131 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
132 int ring_size
= BIT(ring
->order
);
133 int ring_mask
= ring_size
- 1;
136 for (i
= 0; i
< ring_size
; i
++) {
137 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
139 desc
->next
= (u32
) (ring
->descs_dma
+
140 AG71XX_DESC_SIZE
* ((i
+ 1) & ring_mask
));
142 desc
->ctrl
= DESC_EMPTY
;
143 ring
->buf
[i
].skb
= NULL
;
146 /* flush descriptors */
151 netdev_reset_queue(ag
->dev
);
154 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
156 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
157 int ring_size
= BIT(ring
->order
);
163 for (i
= 0; i
< ring_size
; i
++)
164 if (ring
->buf
[i
].rx_buf
) {
165 dma_unmap_single(&ag
->dev
->dev
, ring
->buf
[i
].dma_addr
,
166 ag
->rx_buf_size
, DMA_FROM_DEVICE
);
167 skb_free_frag(ring
->buf
[i
].rx_buf
);
171 static int ag71xx_buffer_size(struct ag71xx
*ag
)
173 return ag
->rx_buf_size
+
174 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
177 static bool ag71xx_fill_rx_buf(struct ag71xx
*ag
, struct ag71xx_buf
*buf
,
179 void *(*alloc
)(unsigned int size
))
181 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
182 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, buf
- &ring
->buf
[0]);
185 data
= alloc(ag71xx_buffer_size(ag
));
190 buf
->dma_addr
= dma_map_single(&ag
->dev
->dev
, data
, ag
->rx_buf_size
,
192 desc
->data
= (u32
) buf
->dma_addr
+ offset
;
196 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
198 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
199 int ring_size
= BIT(ring
->order
);
200 int ring_mask
= BIT(ring
->order
) - 1;
205 for (i
= 0; i
< ring_size
; i
++) {
206 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
208 desc
->next
= (u32
) (ring
->descs_dma
+
209 AG71XX_DESC_SIZE
* ((i
+ 1) & ring_mask
));
211 DBG("ag71xx: RX desc at %p, next is %08x\n",
215 for (i
= 0; i
< ring_size
; i
++) {
216 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
218 if (!ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], ag
->rx_buf_offset
,
219 netdev_alloc_frag
)) {
224 desc
->ctrl
= DESC_EMPTY
;
227 /* flush descriptors */
236 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
238 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
239 int ring_mask
= BIT(ring
->order
) - 1;
241 int offset
= ag
->rx_buf_offset
;
244 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
245 struct ag71xx_desc
*desc
;
248 i
= ring
->dirty
& ring_mask
;
249 desc
= ag71xx_ring_desc(ring
, i
);
251 if (!ring
->buf
[i
].rx_buf
&&
252 !ag71xx_fill_rx_buf(ag
, &ring
->buf
[i
], offset
,
256 desc
->ctrl
= DESC_EMPTY
;
260 /* flush descriptors */
263 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
268 static int ag71xx_rings_init(struct ag71xx
*ag
)
270 struct ag71xx_ring
*tx
= &ag
->tx_ring
;
271 struct ag71xx_ring
*rx
= &ag
->rx_ring
;
272 int ring_size
= BIT(tx
->order
) + BIT(rx
->order
);
273 int tx_size
= BIT(tx
->order
);
275 tx
->buf
= kzalloc(ring_size
* sizeof(*tx
->buf
), GFP_KERNEL
);
279 tx
->descs_cpu
= dma_alloc_coherent(NULL
, ring_size
* AG71XX_DESC_SIZE
,
280 &tx
->descs_dma
, GFP_ATOMIC
);
281 if (!tx
->descs_cpu
) {
287 rx
->buf
= &tx
->buf
[BIT(tx
->order
)];
288 rx
->descs_cpu
= ((void *)tx
->descs_cpu
) + tx_size
* AG71XX_DESC_SIZE
;
289 rx
->descs_dma
= tx
->descs_dma
+ tx_size
* AG71XX_DESC_SIZE
;
291 ag71xx_ring_tx_init(ag
);
292 return ag71xx_ring_rx_init(ag
);
295 static void ag71xx_rings_free(struct ag71xx
*ag
)
297 struct ag71xx_ring
*tx
= &ag
->tx_ring
;
298 struct ag71xx_ring
*rx
= &ag
->rx_ring
;
299 int ring_size
= BIT(tx
->order
) + BIT(rx
->order
);
302 dma_free_coherent(NULL
, ring_size
* AG71XX_DESC_SIZE
,
303 tx
->descs_cpu
, tx
->descs_dma
);
307 tx
->descs_cpu
= NULL
;
308 rx
->descs_cpu
= NULL
;
313 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
315 ag71xx_ring_rx_clean(ag
);
316 ag71xx_ring_tx_clean(ag
);
317 ag71xx_rings_free(ag
);
319 netdev_reset_queue(ag
->dev
);
322 static unsigned char *ag71xx_speed_str(struct ag71xx
*ag
)
336 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
340 t
= (((u32
) mac
[5]) << 24) | (((u32
) mac
[4]) << 16)
341 | (((u32
) mac
[3]) << 8) | ((u32
) mac
[2]);
343 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
345 t
= (((u32
) mac
[1]) << 24) | (((u32
) mac
[0]) << 16);
346 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
349 static void ag71xx_dma_reset(struct ag71xx
*ag
)
354 ag71xx_dump_dma_regs(ag
);
357 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
358 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
361 * give the hardware some time to really stop all rx/tx activity
362 * clearing the descriptors too early causes random memory corruption
366 /* clear descriptor addresses */
367 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->stop_desc_dma
);
368 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->stop_desc_dma
);
370 /* clear pending RX/TX interrupts */
371 for (i
= 0; i
< 256; i
++) {
372 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
373 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
376 /* clear pending errors */
377 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
| RX_STATUS_OF
);
378 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
| TX_STATUS_UR
);
380 val
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
382 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
385 val
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
387 /* mask out reserved bits */
391 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
394 ag71xx_dump_dma_regs(ag
);
397 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
398 MAC_CFG1_SRX | MAC_CFG1_STX)
400 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
402 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
403 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
404 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
405 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
406 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
409 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
410 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
411 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
412 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
413 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
414 FIFO_CFG5_17 | FIFO_CFG5_SF)
416 static void ag71xx_hw_stop(struct ag71xx
*ag
)
418 /* disable all interrupts and stop the rx/tx engine */
419 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
420 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
421 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
424 static void ag71xx_hw_setup(struct ag71xx
*ag
)
426 struct device_node
*np
= ag
->pdev
->dev
.of_node
;
427 u32 init
= MAC_CFG1_INIT
;
429 /* setup MAC configuration registers */
430 if (of_property_read_bool(np
, "flow-control"))
431 init
|= MAC_CFG1_TFC
| MAC_CFG1_RFC
;
432 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, init
);
434 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
435 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
437 /* setup max frame length to zero */
438 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, 0);
440 /* setup FIFO configuration registers */
441 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
442 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, ag
->fifodata
[0]);
443 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, ag
->fifodata
[1]);
444 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, FIFO_CFG4_INIT
);
445 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, FIFO_CFG5_INIT
);
448 static void ag71xx_hw_init(struct ag71xx
*ag
)
452 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
455 reset_control_assert(ag
->mac_reset
);
457 reset_control_deassert(ag
->mac_reset
);
462 ag71xx_dma_reset(ag
);
465 static void ag71xx_fast_reset(struct ag71xx
*ag
)
467 struct net_device
*dev
= ag
->dev
;
474 mii_reg
= ag71xx_rr(ag
, AG71XX_REG_MII_CFG
);
475 rx_ds
= ag71xx_rr(ag
, AG71XX_REG_RX_DESC
);
477 ag71xx_tx_packets(ag
, true);
479 reset_control_assert(ag
->mac_reset
);
481 reset_control_deassert(ag
->mac_reset
);
484 ag71xx_dma_reset(ag
);
486 ag
->tx_ring
.curr
= 0;
487 ag
->tx_ring
.dirty
= 0;
488 netdev_reset_queue(ag
->dev
);
490 /* setup max frame length */
491 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
,
492 ag71xx_max_frame_len(ag
->dev
->mtu
));
494 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, rx_ds
);
495 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
496 ag71xx_wr(ag
, AG71XX_REG_MII_CFG
, mii_reg
);
498 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
501 static void ag71xx_hw_start(struct ag71xx
*ag
)
503 /* start RX engine */
504 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
506 /* enable interrupts */
507 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
509 netif_wake_queue(ag
->dev
);
512 static void ath79_set_pllval(struct ag71xx
*ag
)
514 u32 pll_reg
= ag
->pllreg
[1];
522 pll_val
= ag
->plldata
[2];
525 pll_val
= ag
->plldata
[1];
528 pll_val
= ag
->plldata
[0];
535 regmap_write(ag
->pllregmap
, pll_reg
, pll_val
);
538 static void ath79_set_pll(struct ag71xx
*ag
)
540 u32 pll_cfg
= ag
->pllreg
[0];
541 u32 pll_shift
= ag
->pllreg
[2];
546 regmap_update_bits(ag
->pllregmap
, pll_cfg
, 3 << pll_shift
, 2 << pll_shift
);
549 ath79_set_pllval(ag
);
551 regmap_update_bits(ag
->pllregmap
, pll_cfg
, 3 << pll_shift
, 3 << pll_shift
);
554 regmap_update_bits(ag
->pllregmap
, pll_cfg
, 3 << pll_shift
, 0);
558 static void ath79_mii_ctrl_set_if(struct ag71xx
*ag
, unsigned int mii_if
)
562 t
= __raw_readl(ag
->mii_base
);
563 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
564 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
565 __raw_writel(t
, ag
->mii_base
);
568 static void ath79_mii0_ctrl_set_if(struct ag71xx
*ag
)
572 switch (ag
->phy_if_mode
) {
573 case PHY_INTERFACE_MODE_MII
:
574 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
576 case PHY_INTERFACE_MODE_GMII
:
577 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
579 case PHY_INTERFACE_MODE_RGMII
:
580 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
582 case PHY_INTERFACE_MODE_RMII
:
583 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
586 WARN(1, "Impossible PHY mode defined.\n");
590 ath79_mii_ctrl_set_if(ag
, mii_if
);
593 static void ath79_mii1_ctrl_set_if(struct ag71xx
*ag
)
597 switch (ag
->phy_if_mode
) {
598 case PHY_INTERFACE_MODE_RMII
:
599 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
601 case PHY_INTERFACE_MODE_RGMII
:
602 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
605 WARN(1, "Impossible PHY mode defined.\n");
609 ath79_mii_ctrl_set_if(ag
, mii_if
);
612 static void ath79_mii_ctrl_set_speed(struct ag71xx
*ag
)
614 unsigned int mii_speed
;
622 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
625 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
628 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
634 t
= __raw_readl(ag
->mii_base
);
635 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
636 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
637 __raw_writel(t
, ag
->mii_base
);
641 __ag71xx_link_adjust(struct ag71xx
*ag
, bool update
)
643 struct device_node
*np
= ag
->pdev
->dev
.of_node
;
648 if (!ag
->link
&& update
) {
650 netif_carrier_off(ag
->dev
);
651 if (netif_msg_link(ag
))
652 pr_info("%s: link down\n", ag
->dev
->name
);
656 if (!of_device_is_compatible(np
, "qca,ar9130-eth") &&
657 !of_device_is_compatible(np
, "qca,ar7100-eth"))
658 ag71xx_fast_reset(ag
);
660 cfg2
= ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
);
661 cfg2
&= ~(MAC_CFG2_IF_1000
| MAC_CFG2_IF_10_100
| MAC_CFG2_FDX
);
662 cfg2
|= (ag
->duplex
) ? MAC_CFG2_FDX
: 0;
664 ifctl
= ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
);
665 ifctl
&= ~(MAC_IFCTL_SPEED
);
667 fifo5
= ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
);
668 fifo5
&= ~FIFO_CFG5_BM
;
672 cfg2
|= MAC_CFG2_IF_1000
;
673 fifo5
|= FIFO_CFG5_BM
;
676 cfg2
|= MAC_CFG2_IF_10_100
;
677 ifctl
|= MAC_IFCTL_SPEED
;
680 cfg2
|= MAC_CFG2_IF_10_100
;
687 if (ag
->tx_ring
.desc_split
) {
688 ag
->fifodata
[2] &= 0xffff;
689 ag
->fifodata
[2] |= ((2048 - ag
->tx_ring
.desc_split
) / 4) << 16;
692 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG3
, ag
->fifodata
[2]);
695 if (of_device_is_compatible(np
, "qca,ar7100-eth") ||
696 of_device_is_compatible(np
, "qca,ar9130-eth")) {
698 ath79_mii_ctrl_set_speed(ag
);
699 } else if (of_device_is_compatible(np
, "qca,ar7242-eth") ||
700 of_device_is_compatible(np
, "qca,ar9340-eth") ||
701 of_device_is_compatible(np
, "qca,qca9550-eth") ||
702 of_device_is_compatible(np
, "qca,qca9560-eth")) {
703 ath79_set_pllval(ag
);
707 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG2
, cfg2
);
708 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, fifo5
);
709 ag71xx_wr(ag
, AG71XX_REG_MAC_IFCTL
, ifctl
);
711 if (of_device_is_compatible(np
, "qca,qca9530-eth") ||
712 of_device_is_compatible(np
, "qca,qca9560-eth")) {
714 * The rx ring buffer can stall on small packets on QCA953x and
715 * QCA956x. Disabling the inline checksum engine fixes the stall.
716 * The wr, rr functions cannot be used since this hidden register
717 * is outside of the normal ag71xx register block.
719 void __iomem
*dam
= ioremap_nocache(0xb90001bc, 0x4);
721 __raw_writel(__raw_readl(dam
) & ~BIT(27), dam
);
722 (void)__raw_readl(dam
);
729 netif_carrier_on(ag
->dev
);
730 if (update
&& netif_msg_link(ag
))
731 pr_info("%s: link up (%sMbps/%s duplex)\n",
733 ag71xx_speed_str(ag
),
734 (DUPLEX_FULL
== ag
->duplex
) ? "Full" : "Half");
736 ag71xx_dump_regs(ag
);
739 void ag71xx_link_adjust(struct ag71xx
*ag
)
741 __ag71xx_link_adjust(ag
, true);
744 static int ag71xx_hw_enable(struct ag71xx
*ag
)
748 ret
= ag71xx_rings_init(ag
);
752 napi_enable(&ag
->napi
);
753 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
754 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
755 netif_start_queue(ag
->dev
);
760 static void ag71xx_hw_disable(struct ag71xx
*ag
)
764 spin_lock_irqsave(&ag
->lock
, flags
);
766 netif_stop_queue(ag
->dev
);
769 ag71xx_dma_reset(ag
);
771 napi_disable(&ag
->napi
);
772 del_timer_sync(&ag
->oom_timer
);
774 spin_unlock_irqrestore(&ag
->lock
, flags
);
776 ag71xx_rings_cleanup(ag
);
779 static int ag71xx_open(struct net_device
*dev
)
781 struct ag71xx
*ag
= netdev_priv(dev
);
782 unsigned int max_frame_len
;
785 netif_carrier_off(dev
);
786 max_frame_len
= ag71xx_max_frame_len(dev
->mtu
);
787 ag
->rx_buf_size
= SKB_DATA_ALIGN(max_frame_len
+ NET_SKB_PAD
+ NET_IP_ALIGN
);
789 /* setup max frame length */
790 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, max_frame_len
);
791 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
793 ret
= ag71xx_hw_enable(ag
);
797 phy_start(ag
->phy_dev
);
802 ag71xx_rings_cleanup(ag
);
806 static int ag71xx_stop(struct net_device
*dev
)
808 struct ag71xx
*ag
= netdev_priv(dev
);
810 netif_carrier_off(dev
);
811 phy_stop(ag
->phy_dev
);
812 ag71xx_hw_disable(ag
);
817 static int ag71xx_fill_dma_desc(struct ag71xx_ring
*ring
, u32 addr
, int len
)
820 struct ag71xx_desc
*desc
;
821 int ring_mask
= BIT(ring
->order
) - 1;
823 int split
= ring
->desc_split
;
829 unsigned int cur_len
= len
;
831 i
= (ring
->curr
+ ndesc
) & ring_mask
;
832 desc
= ag71xx_ring_desc(ring
, i
);
834 if (!ag71xx_desc_empty(desc
))
837 if (cur_len
> split
) {
841 * TX will hang if DMA transfers <= 4 bytes,
842 * make sure next segment is more than 4 bytes long.
844 if (len
<= split
+ 4)
853 cur_len
|= DESC_MORE
;
855 /* prevent early tx attempt of this descriptor */
857 cur_len
|= DESC_EMPTY
;
859 desc
->ctrl
= cur_len
;
866 static netdev_tx_t
ag71xx_hard_start_xmit(struct sk_buff
*skb
,
867 struct net_device
*dev
)
869 struct ag71xx
*ag
= netdev_priv(dev
);
870 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
871 int ring_mask
= BIT(ring
->order
) - 1;
872 int ring_size
= BIT(ring
->order
);
873 struct ag71xx_desc
*desc
;
878 DBG("%s: packet len is too small\n", ag
->dev
->name
);
882 dma_addr
= dma_map_single(&dev
->dev
, skb
->data
, skb
->len
,
885 i
= ring
->curr
& ring_mask
;
886 desc
= ag71xx_ring_desc(ring
, i
);
888 /* setup descriptor fields */
889 n
= ag71xx_fill_dma_desc(ring
, (u32
) dma_addr
, skb
->len
& ag
->desc_pktlen_mask
);
893 i
= (ring
->curr
+ n
- 1) & ring_mask
;
894 ring
->buf
[i
].len
= skb
->len
;
895 ring
->buf
[i
].skb
= skb
;
897 netdev_sent_queue(dev
, skb
->len
);
899 skb_tx_timestamp(skb
);
901 desc
->ctrl
&= ~DESC_EMPTY
;
904 /* flush descriptor */
908 if (ring
->desc_split
)
909 ring_min
*= AG71XX_TX_RING_DS_PER_PKT
;
911 if (ring
->curr
- ring
->dirty
>= ring_size
- ring_min
) {
912 DBG("%s: tx queue full\n", dev
->name
);
913 netif_stop_queue(dev
);
916 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
918 /* enable TX engine */
919 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
924 dma_unmap_single(&dev
->dev
, dma_addr
, skb
->len
, DMA_TO_DEVICE
);
927 dev
->stats
.tx_dropped
++;
933 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
935 struct ag71xx
*ag
= netdev_priv(dev
);
940 if (ag
->phy_dev
== NULL
)
943 spin_lock_irq(&ag
->lock
);
944 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
945 spin_unlock_irq(&ag
->lock
);
950 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
956 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
963 if (ag
->phy_dev
== NULL
)
966 return phy_mii_ioctl(ag
->phy_dev
, ifr
, cmd
);
975 static void ag71xx_oom_timer_handler(unsigned long data
)
977 struct net_device
*dev
= (struct net_device
*) data
;
978 struct ag71xx
*ag
= netdev_priv(dev
);
980 napi_schedule(&ag
->napi
);
983 static void ag71xx_tx_timeout(struct net_device
*dev
)
985 struct ag71xx
*ag
= netdev_priv(dev
);
987 if (netif_msg_tx_err(ag
))
988 pr_info("%s: tx timeout\n", ag
->dev
->name
);
990 schedule_delayed_work(&ag
->restart_work
, 1);
993 static void ag71xx_restart_work_func(struct work_struct
*work
)
995 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, restart_work
.work
);
998 ag71xx_hw_disable(ag
);
999 ag71xx_hw_enable(ag
);
1001 __ag71xx_link_adjust(ag
, false);
1005 static bool ag71xx_check_dma_stuck(struct ag71xx
*ag
)
1007 unsigned long timestamp
;
1008 u32 rx_sm
, tx_sm
, rx_fd
;
1010 timestamp
= netdev_get_tx_queue(ag
->dev
, 0)->trans_start
;
1011 if (likely(time_before(jiffies
, timestamp
+ HZ
/10)))
1014 if (!netif_carrier_ok(ag
->dev
))
1017 rx_sm
= ag71xx_rr(ag
, AG71XX_REG_RX_SM
);
1018 if ((rx_sm
& 0x7) == 0x3 && ((rx_sm
>> 4) & 0x7) == 0x6)
1021 tx_sm
= ag71xx_rr(ag
, AG71XX_REG_TX_SM
);
1022 rx_fd
= ag71xx_rr(ag
, AG71XX_REG_FIFO_DEPTH
);
1023 if (((tx_sm
>> 4) & 0x7) == 0 && ((rx_sm
& 0x7) == 0) &&
1024 ((rx_sm
>> 4) & 0x7) == 0 && rx_fd
== 0)
1030 static int ag71xx_tx_packets(struct ag71xx
*ag
, bool flush
)
1032 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
1033 bool dma_stuck
= false;
1034 int ring_mask
= BIT(ring
->order
) - 1;
1035 int ring_size
= BIT(ring
->order
);
1037 int bytes_compl
= 0;
1040 DBG("%s: processing TX ring\n", ag
->dev
->name
);
1042 while (ring
->dirty
+ n
!= ring
->curr
) {
1043 unsigned int i
= (ring
->dirty
+ n
) & ring_mask
;
1044 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
1045 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
1047 if (!flush
&& !ag71xx_desc_empty(desc
)) {
1048 if (ag
->tx_hang_workaround
&&
1049 ag71xx_check_dma_stuck(ag
)) {
1050 schedule_delayed_work(&ag
->restart_work
, HZ
/ 2);
1057 desc
->ctrl
|= DESC_EMPTY
;
1063 dev_kfree_skb_any(skb
);
1064 ring
->buf
[i
].skb
= NULL
;
1066 bytes_compl
+= ring
->buf
[i
].len
;
1072 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
1077 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
1082 ag
->dev
->stats
.tx_bytes
+= bytes_compl
;
1083 ag
->dev
->stats
.tx_packets
+= sent
;
1085 netdev_completed_queue(ag
->dev
, sent
, bytes_compl
);
1086 if ((ring
->curr
- ring
->dirty
) < (ring_size
* 3) / 4)
1087 netif_wake_queue(ag
->dev
);
1090 cancel_delayed_work(&ag
->restart_work
);
1095 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
1097 struct net_device
*dev
= ag
->dev
;
1098 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
1099 unsigned int pktlen_mask
= ag
->desc_pktlen_mask
;
1100 unsigned int offset
= ag
->rx_buf_offset
;
1101 int ring_mask
= BIT(ring
->order
) - 1;
1102 int ring_size
= BIT(ring
->order
);
1103 struct sk_buff_head queue
;
1104 struct sk_buff
*skb
;
1107 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1108 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
1110 skb_queue_head_init(&queue
);
1112 while (done
< limit
) {
1113 unsigned int i
= ring
->curr
& ring_mask
;
1114 struct ag71xx_desc
*desc
= ag71xx_ring_desc(ring
, i
);
1118 if (ag71xx_desc_empty(desc
))
1121 if ((ring
->dirty
+ ring_size
) == ring
->curr
) {
1126 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
1128 pktlen
= desc
->ctrl
& pktlen_mask
;
1129 pktlen
-= ETH_FCS_LEN
;
1131 dma_unmap_single(&dev
->dev
, ring
->buf
[i
].dma_addr
,
1132 ag
->rx_buf_size
, DMA_FROM_DEVICE
);
1134 dev
->stats
.rx_packets
++;
1135 dev
->stats
.rx_bytes
+= pktlen
;
1137 skb
= build_skb(ring
->buf
[i
].rx_buf
, ag71xx_buffer_size(ag
));
1139 skb_free_frag(ring
->buf
[i
].rx_buf
);
1143 skb_reserve(skb
, offset
);
1144 skb_put(skb
, pktlen
);
1147 dev
->stats
.rx_dropped
++;
1151 skb
->ip_summed
= CHECKSUM_NONE
;
1152 __skb_queue_tail(&queue
, skb
);
1156 ring
->buf
[i
].rx_buf
= NULL
;
1162 ag71xx_ring_rx_refill(ag
);
1164 while ((skb
= __skb_dequeue(&queue
)) != NULL
) {
1165 skb
->protocol
= eth_type_trans(skb
, dev
);
1166 netif_receive_skb(skb
);
1169 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1170 dev
->name
, ring
->curr
, ring
->dirty
, done
);
1175 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
1177 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
1178 struct net_device
*dev
= ag
->dev
;
1179 struct ag71xx_ring
*rx_ring
= &ag
->rx_ring
;
1180 int rx_ring_size
= BIT(rx_ring
->order
);
1181 unsigned long flags
;
1186 tx_done
= ag71xx_tx_packets(ag
, false);
1188 DBG("%s: processing RX ring\n", dev
->name
);
1189 rx_done
= ag71xx_rx_packets(ag
, limit
);
1191 ag71xx_debugfs_update_napi_stats(ag
, rx_done
, tx_done
);
1193 if (rx_ring
->buf
[rx_ring
->dirty
% rx_ring_size
].rx_buf
== NULL
)
1196 status
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
1197 if (unlikely(status
& RX_STATUS_OF
)) {
1198 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
1199 dev
->stats
.rx_fifo_errors
++;
1202 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
1205 if (rx_done
< limit
) {
1206 if (status
& RX_STATUS_PR
)
1209 status
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
1210 if (status
& TX_STATUS_PS
)
1213 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1214 dev
->name
, rx_done
, tx_done
, limit
);
1216 napi_complete(napi
);
1218 /* enable interrupts */
1219 spin_lock_irqsave(&ag
->lock
, flags
);
1220 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
1221 spin_unlock_irqrestore(&ag
->lock
, flags
);
1226 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1227 dev
->name
, rx_done
, tx_done
, limit
);
1231 if (netif_msg_rx_err(ag
))
1232 pr_info("%s: out of memory\n", dev
->name
);
1234 mod_timer(&ag
->oom_timer
, jiffies
+ AG71XX_OOM_REFILL
);
1235 napi_complete(napi
);
1239 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
1241 struct net_device
*dev
= dev_id
;
1242 struct ag71xx
*ag
= netdev_priv(dev
);
1245 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
1246 ag71xx_dump_intr(ag
, "raw", status
);
1248 if (unlikely(!status
))
1251 if (unlikely(status
& AG71XX_INT_ERR
)) {
1252 if (status
& AG71XX_INT_TX_BE
) {
1253 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
1254 dev_err(&dev
->dev
, "TX BUS error\n");
1256 if (status
& AG71XX_INT_RX_BE
) {
1257 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
1258 dev_err(&dev
->dev
, "RX BUS error\n");
1262 if (likely(status
& AG71XX_INT_POLL
)) {
1263 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
1264 DBG("%s: enable polling mode\n", dev
->name
);
1265 napi_schedule(&ag
->napi
);
1268 ag71xx_debugfs_update_int_stats(ag
, status
);
1273 #ifdef CONFIG_NET_POLL_CONTROLLER
1275 * Polling 'interrupt' - used by things like netconsole to send skbs
1276 * without having to re-enable interrupts. It's not called while
1277 * the interrupt routine is executing.
1279 static void ag71xx_netpoll(struct net_device
*dev
)
1281 disable_irq(dev
->irq
);
1282 ag71xx_interrupt(dev
->irq
, dev
);
1283 enable_irq(dev
->irq
);
1287 static int ag71xx_change_mtu(struct net_device
*dev
, int new_mtu
)
1289 struct ag71xx
*ag
= netdev_priv(dev
);
1292 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
,
1293 ag71xx_max_frame_len(dev
->mtu
));
1298 static const struct net_device_ops ag71xx_netdev_ops
= {
1299 .ndo_open
= ag71xx_open
,
1300 .ndo_stop
= ag71xx_stop
,
1301 .ndo_start_xmit
= ag71xx_hard_start_xmit
,
1302 .ndo_do_ioctl
= ag71xx_do_ioctl
,
1303 .ndo_tx_timeout
= ag71xx_tx_timeout
,
1304 .ndo_change_mtu
= ag71xx_change_mtu
,
1305 .ndo_set_mac_address
= eth_mac_addr
,
1306 .ndo_validate_addr
= eth_validate_addr
,
1307 #ifdef CONFIG_NET_POLL_CONTROLLER
1308 .ndo_poll_controller
= ag71xx_netpoll
,
1312 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode
)
1315 case PHY_INTERFACE_MODE_MII
:
1317 case PHY_INTERFACE_MODE_GMII
:
1319 case PHY_INTERFACE_MODE_RMII
:
1321 case PHY_INTERFACE_MODE_RGMII
:
1323 case PHY_INTERFACE_MODE_SGMII
:
1332 static int ag71xx_probe(struct platform_device
*pdev
)
1334 struct device_node
*np
= pdev
->dev
.of_node
;
1335 struct device_node
*mdio_node
;
1336 struct net_device
*dev
;
1337 struct resource
*res
;
1339 const void *mac_addr
;
1346 dev
= alloc_etherdev(sizeof(*ag
));
1350 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1354 err
= ag71xx_setup_gmac(np
);
1358 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1360 ag
= netdev_priv(dev
);
1363 ag
->msg_enable
= netif_msg_init(ag71xx_msg_level
,
1364 AG71XX_DEFAULT_MSG_ENABLE
);
1365 spin_lock_init(&ag
->lock
);
1367 ag
->mac_reset
= devm_reset_control_get(&pdev
->dev
, "mac");
1368 if (IS_ERR(ag
->mac_reset
)) {
1369 dev_err(&pdev
->dev
, "missing mac reset\n");
1370 err
= PTR_ERR(ag
->mac_reset
);
1374 if (of_property_read_u32_array(np
, "fifo-data", ag
->fifodata
, 3)) {
1375 if (of_device_is_compatible(np
, "qca,ar9130-eth") ||
1376 of_device_is_compatible(np
, "qca,ar7100-eth")) {
1377 ag
->fifodata
[0] = 0x0fff0000;
1378 ag
->fifodata
[1] = 0x00001fff;
1380 ag
->fifodata
[0] = 0x0010ffff;
1381 ag
->fifodata
[1] = 0x015500aa;
1382 ag
->fifodata
[2] = 0x01f00140;
1384 if (of_device_is_compatible(np
, "qca,ar9130-eth"))
1385 ag
->fifodata
[2] = 0x00780fff;
1386 else if (of_device_is_compatible(np
, "qca,ar7100-eth"))
1387 ag
->fifodata
[2] = 0x008001ff;
1390 if (of_property_read_u32_array(np
, "pll-data", ag
->plldata
, 3))
1391 dev_dbg(&pdev
->dev
, "failed to read pll-data property\n");
1393 if (of_property_read_u32_array(np
, "pll-reg", ag
->pllreg
, 3))
1394 dev_dbg(&pdev
->dev
, "failed to read pll-reg property\n");
1396 ag
->pllregmap
= syscon_regmap_lookup_by_phandle(np
, "pll-handle");
1397 if (IS_ERR(ag
->pllregmap
)) {
1398 dev_dbg(&pdev
->dev
, "failed to read pll-handle property\n");
1399 ag
->pllregmap
= NULL
;
1402 ag
->mac_base
= devm_ioremap_nocache(&pdev
->dev
, res
->start
,
1403 res
->end
- res
->start
+ 1);
1404 if (!ag
->mac_base
) {
1408 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1410 ag
->mii_base
= devm_ioremap_nocache(&pdev
->dev
, res
->start
,
1411 res
->end
- res
->start
+ 1);
1412 if (!ag
->mii_base
) {
1418 dev
->irq
= platform_get_irq(pdev
, 0);
1419 err
= devm_request_irq(&pdev
->dev
, dev
->irq
, ag71xx_interrupt
,
1420 0x0, dev_name(&pdev
->dev
), dev
);
1422 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
1426 dev
->netdev_ops
= &ag71xx_netdev_ops
;
1427 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
1429 INIT_DELAYED_WORK(&ag
->restart_work
, ag71xx_restart_work_func
);
1431 init_timer(&ag
->oom_timer
);
1432 ag
->oom_timer
.data
= (unsigned long) dev
;
1433 ag
->oom_timer
.function
= ag71xx_oom_timer_handler
;
1435 tx_size
= AG71XX_TX_RING_SIZE_DEFAULT
;
1436 ag
->rx_ring
.order
= ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT
);
1438 if (of_device_is_compatible(np
, "qca,ar9340-eth") ||
1439 of_device_is_compatible(np
, "qca,qca9530-eth") ||
1440 of_device_is_compatible(np
, "qca,qca9550-eth") ||
1441 of_device_is_compatible(np
, "qca,qca9560-eth"))
1442 ag
->desc_pktlen_mask
= SZ_16K
- 1;
1444 ag
->desc_pktlen_mask
= SZ_4K
- 1;
1446 if (ag
->desc_pktlen_mask
== SZ_16K
- 1 &&
1447 !of_device_is_compatible(np
, "qca,qca9550-eth") &&
1448 !of_device_is_compatible(np
, "qca,qca9560-eth"))
1449 max_frame_len
= ag
->desc_pktlen_mask
;
1451 max_frame_len
= 1540;
1454 dev
->max_mtu
= max_frame_len
- ag71xx_max_frame_len(0);
1456 if (of_device_is_compatible(np
, "qca,ar7240-eth"))
1457 ag
->tx_hang_workaround
= 1;
1459 ag
->rx_buf_offset
= NET_SKB_PAD
;
1460 if (!of_device_is_compatible(np
, "qca,ar7100-eth") &&
1461 !of_device_is_compatible(np
, "qca,ar9130-eth"))
1462 ag
->rx_buf_offset
+= NET_IP_ALIGN
;
1464 if (of_device_is_compatible(np
, "qca,ar7100-eth")) {
1465 ag
->tx_ring
.desc_split
= AG71XX_TX_RING_SPLIT
;
1466 tx_size
*= AG71XX_TX_RING_DS_PER_PKT
;
1468 ag
->tx_ring
.order
= ag71xx_ring_size_order(tx_size
);
1470 ag
->stop_desc
= dmam_alloc_coherent(&pdev
->dev
,
1471 sizeof(struct ag71xx_desc
),
1472 &ag
->stop_desc_dma
, GFP_KERNEL
);
1476 ag
->stop_desc
->data
= 0;
1477 ag
->stop_desc
->ctrl
= 0;
1478 ag
->stop_desc
->next
= (u32
) ag
->stop_desc_dma
;
1480 mac_addr
= of_get_mac_address(np
);
1482 memcpy(dev
->dev_addr
, mac_addr
, ETH_ALEN
);
1483 if (!mac_addr
|| !is_valid_ether_addr(dev
->dev_addr
)) {
1484 dev_err(&pdev
->dev
, "invalid MAC address, using random address\n");
1485 eth_random_addr(dev
->dev_addr
);
1488 ag
->phy_if_mode
= of_get_phy_mode(np
);
1489 if (ag
->phy_if_mode
< 0) {
1490 dev_err(&pdev
->dev
, "missing phy-mode property in DT\n");
1491 err
= ag
->phy_if_mode
;
1495 if (of_property_read_u32(np
, "qca,mac-idx", &ag
->mac_idx
))
1498 switch (ag
->mac_idx
) {
1500 ath79_mii0_ctrl_set_if(ag
);
1503 ath79_mii1_ctrl_set_if(ag
);
1509 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
1511 ag71xx_dump_regs(ag
);
1513 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, 0);
1517 ag71xx_dump_regs(ag
);
1519 if (!of_device_is_compatible(np
, "simple-mfd")) {
1520 mdio_node
= of_get_child_by_name(np
, "mdio-bus");
1521 if (!IS_ERR(mdio_node
))
1522 of_platform_device_create(mdio_node
, NULL
, NULL
);
1525 err
= ag71xx_phy_connect(ag
);
1529 err
= ag71xx_debugfs_init(ag
);
1531 goto err_phy_disconnect
;
1533 platform_set_drvdata(pdev
, dev
);
1535 err
= register_netdev(dev
);
1537 dev_err(&pdev
->dev
, "unable to register net device\n");
1538 platform_set_drvdata(pdev
, NULL
);
1539 ag71xx_debugfs_exit(ag
);
1540 goto err_phy_disconnect
;
1543 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1544 dev
->name
, (unsigned long) ag
->mac_base
, dev
->irq
,
1545 ag71xx_get_phy_if_mode_name(ag
->phy_if_mode
));
1550 ag71xx_phy_disconnect(ag
);
1556 static int ag71xx_remove(struct platform_device
*pdev
)
1558 struct net_device
*dev
= platform_get_drvdata(pdev
);
1564 ag
= netdev_priv(dev
);
1565 ag71xx_debugfs_exit(ag
);
1566 ag71xx_phy_disconnect(ag
);
1567 unregister_netdev(dev
);
1568 free_irq(dev
->irq
, dev
);
1569 iounmap(ag
->mac_base
);
1571 platform_set_drvdata(pdev
, NULL
);
1576 static const struct of_device_id ag71xx_match
[] = {
1577 { .compatible
= "qca,ar7100-eth" },
1578 { .compatible
= "qca,ar7240-eth" },
1579 { .compatible
= "qca,ar7241-eth" },
1580 { .compatible
= "qca,ar7242-eth" },
1581 { .compatible
= "qca,ar9130-eth" },
1582 { .compatible
= "qca,ar9330-eth" },
1583 { .compatible
= "qca,ar9340-eth" },
1584 { .compatible
= "qca,qca9530-eth" },
1585 { .compatible
= "qca,qca9550-eth" },
1586 { .compatible
= "qca,qca9560-eth" },
1590 static struct platform_driver ag71xx_driver
= {
1591 .probe
= ag71xx_probe
,
1592 .remove
= ag71xx_remove
,
1594 .name
= AG71XX_DRV_NAME
,
1595 .of_match_table
= ag71xx_match
,
1599 static int __init
ag71xx_module_init(void)
1603 ret
= ag71xx_debugfs_root_init();
1607 ret
= platform_driver_register(&ag71xx_driver
);
1609 goto err_debugfs_exit
;
1614 ag71xx_debugfs_root_exit();
1619 static void __exit
ag71xx_module_exit(void)
1621 platform_driver_unregister(&ag71xx_driver
);
1622 ag71xx_debugfs_root_exit();
1625 module_init(ag71xx_module_init
);
1626 module_exit(ag71xx_module_exit
);
1628 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1629 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1630 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1631 MODULE_LICENSE("GPL v2");
1632 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);