1 From cb376159800b9b44be76949c3aee89eb06d29faa Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 6 Mar 2018 09:55:13 +0100
4 Subject: [PATCH 07/27] irqchip/irq-ath79-intc: add irq cascade driver for
7 Signed-off-by: John Crispin <john@phrozen.org>
9 drivers/irqchip/Makefile | 1 +
10 drivers/irqchip/irq-ath79-intc.c | 104 +++++++++++++++++++++++++++++++++++++++
11 2 files changed, 105 insertions(+)
12 create mode 100644 drivers/irqchip/irq-ath79-intc.c
14 --- a/drivers/irqchip/Makefile
15 +++ b/drivers/irqchip/Makefile
16 @@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
18 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
19 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
20 +obj-$(CONFIG_ATH79) += irq-ath79-intc.o
21 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
22 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
23 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
25 +++ b/drivers/irqchip/irq-ath79-intc.c
28 + * Atheros AR71xx/AR724x/AR913x specific interrupt handling
30 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
32 + * This program is free software; you can redistribute it and/or modify it
33 + * under the terms of the GNU General Public License version 2 as published
34 + * by the Free Software Foundation.
37 +#include <linux/interrupt.h>
38 +#include <linux/irqchip.h>
39 +#include <linux/of.h>
40 +#include <linux/of_irq.h>
41 +#include <linux/irqdomain.h>
43 +#include <asm/irq_cpu.h>
44 +#include <asm/mach-ath79/ath79.h>
45 +#include <asm/mach-ath79/ar71xx_regs.h>
47 +#define ATH79_MAX_INTC_CASCADE 3
50 + struct irq_chip chip;
53 + u32 irq_mask[ATH79_MAX_INTC_CASCADE];
56 +static void ath79_intc_irq_handler(struct irq_desc *desc)
58 + struct irq_domain *domain = irq_desc_get_handler_data(desc);
59 + struct ath79_intc *intc = domain->host_data;
62 + pending = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
63 + pending &= intc->pending_mask;
68 + for (i = 0; i < domain->hwirq_max; i++)
69 + if (pending & intc->irq_mask[i])
70 + generic_handle_irq(irq_find_mapping(domain, i));
72 + spurious_interrupt();
76 +static void ath79_intc_irq_unmask(struct irq_data *d)
80 +static void ath79_intc_irq_mask(struct irq_data *d)
84 +static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
86 + struct ath79_intc *intc = d->host_data;
88 + irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
93 +static const struct irq_domain_ops ath79_irq_domain_ops = {
94 + .xlate = irq_domain_xlate_onecell,
95 + .map = ath79_intc_map,
98 +static int __init qca9556_intc_of_init(
99 + struct device_node *node, struct device_node *parent)
101 + struct irq_domain *domain;
102 + struct ath79_intc *intc;
105 + cnt = of_property_count_u32_elems(node, "qcom,pending-bits");
106 + if (cnt > ATH79_MAX_INTC_CASCADE)
107 + panic("Too many INTC pending bits\n");
109 + intc = kzalloc(sizeof(*intc), GFP_KERNEL);
111 + panic("Failed to allocate INTC memory\n");
112 + intc->chip.name = "INTC";
113 + intc->chip.irq_unmask = ath79_intc_irq_unmask,
114 + intc->chip.irq_mask = ath79_intc_irq_mask,
116 + of_property_read_u32_array(node, "qcom,pending-bits", intc->irq_mask, cnt);
117 + for (i = 0; i < cnt; i++)
118 + intc->pending_mask |= intc->irq_mask[i];
120 + intc->irq = irq_of_parse_and_map(node, 0);
122 + panic("Failed to get INTC IRQ");
124 + domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
125 + irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
129 +IRQCHIP_DECLARE(qca9556_intc, "qcom,qca9556-intc",
130 + qca9556_intc_of_init);