1 From 08b9cad7da5d981d595fe6d76e9675f85e23e688 Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 6 Mar 2018 09:57:15 +0100
4 Subject: [PATCH 25/27] MIPS: ath79: drop irq.c
6 all IRQ init code will flow via OF based irq chips.
8 Signed-off-by: John Crispin <john@phrozen.org>
10 arch/mips/ath79/Makefile | 2 +-
11 arch/mips/ath79/irq.c | 285 -----------------------------------------------
12 arch/mips/ath79/setup.c | 6 +
13 3 files changed, 7 insertions(+), 286 deletions(-)
14 delete mode 100644 arch/mips/ath79/irq.c
16 diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
17 index 783369bc1c5b..bd0c9b8b1b5b 100644
18 --- a/arch/mips/ath79/Makefile
19 +++ b/arch/mips/ath79/Makefile
21 # under the terms of the GNU General Public License version 2 as published
22 # by the Free Software Foundation.
24 -obj-y := prom.o setup.o irq.o common.o clock.o
25 +obj-y := prom.o setup.o common.o clock.o
27 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
29 diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
30 deleted file mode 100644
31 index 58d17ef6f58f..000000000000
32 --- a/arch/mips/ath79/irq.c
36 - * Atheros AR71xx/AR724x/AR913x specific interrupt handling
38 - * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
39 - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
40 - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
42 - * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
44 - * This program is free software; you can redistribute it and/or modify it
45 - * under the terms of the GNU General Public License version 2 as published
46 - * by the Free Software Foundation.
49 -#include <linux/kernel.h>
50 -#include <linux/init.h>
51 -#include <linux/interrupt.h>
52 -#include <linux/irqchip.h>
53 -#include <linux/of_irq.h>
55 -#include <asm/irq_cpu.h>
56 -#include <asm/mipsregs.h>
58 -#include <asm/mach-ath79/ath79.h>
59 -#include <asm/mach-ath79/ar71xx_regs.h>
61 -#include "machtypes.h"
64 -static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
68 - status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
70 - if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
71 - ath79_ddr_wb_flush(3);
72 - generic_handle_irq(ATH79_IP2_IRQ(0));
73 - } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
74 - ath79_ddr_wb_flush(4);
75 - generic_handle_irq(ATH79_IP2_IRQ(1));
77 - spurious_interrupt();
81 -static void ar934x_ip2_irq_init(void)
85 - for (i = ATH79_IP2_IRQ_BASE;
86 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
87 - irq_set_chip_and_handler(i, &dummy_irq_chip,
90 - irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
93 -static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
97 - status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
99 - if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
100 - ath79_ddr_wb_flush(3);
101 - generic_handle_irq(ATH79_IP2_IRQ(0));
102 - } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
103 - ath79_ddr_wb_flush(4);
104 - generic_handle_irq(ATH79_IP2_IRQ(1));
106 - spurious_interrupt();
110 -static void qca953x_irq_init(void)
114 - for (i = ATH79_IP2_IRQ_BASE;
115 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
116 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
118 - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
121 -static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
125 - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
126 - status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
129 - spurious_interrupt();
133 - if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
134 - /* TODO: flush DDR? */
135 - generic_handle_irq(ATH79_IP2_IRQ(0));
138 - if (status & QCA955X_EXT_INT_WMAC_ALL) {
139 - /* TODO: flush DDR? */
140 - generic_handle_irq(ATH79_IP2_IRQ(1));
144 -static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
148 - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
149 - status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
150 - QCA955X_EXT_INT_USB1 |
151 - QCA955X_EXT_INT_USB2;
154 - spurious_interrupt();
158 - if (status & QCA955X_EXT_INT_USB1) {
159 - /* TODO: flush DDR? */
160 - generic_handle_irq(ATH79_IP3_IRQ(0));
163 - if (status & QCA955X_EXT_INT_USB2) {
164 - /* TODO: flush DDR? */
165 - generic_handle_irq(ATH79_IP3_IRQ(1));
168 - if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
169 - /* TODO: flush DDR? */
170 - generic_handle_irq(ATH79_IP3_IRQ(2));
174 -static void qca955x_irq_init(void)
178 - for (i = ATH79_IP2_IRQ_BASE;
179 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
180 - irq_set_chip_and_handler(i, &dummy_irq_chip,
183 - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
185 - for (i = ATH79_IP3_IRQ_BASE;
186 - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
187 - irq_set_chip_and_handler(i, &dummy_irq_chip,
190 - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
193 -static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
197 - status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
198 - status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
201 - spurious_interrupt();
205 - if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
206 - /* TODO: flush DDR? */
207 - generic_handle_irq(ATH79_IP2_IRQ(0));
210 - if (status & QCA956X_EXT_INT_WMAC_ALL) {
211 - /* TODO: flsuh DDR? */
212 - generic_handle_irq(ATH79_IP2_IRQ(1));
216 -static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
220 - status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
221 - status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
222 - QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
225 - spurious_interrupt();
229 - if (status & QCA956X_EXT_INT_USB1) {
230 - /* TODO: flush DDR? */
231 - generic_handle_irq(ATH79_IP3_IRQ(0));
234 - if (status & QCA956X_EXT_INT_USB2) {
235 - /* TODO: flush DDR? */
236 - generic_handle_irq(ATH79_IP3_IRQ(1));
239 - if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
240 - /* TODO: flush DDR? */
241 - generic_handle_irq(ATH79_IP3_IRQ(2));
245 -static void qca956x_enable_timer_cb(void) {
248 - misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
249 - misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
250 - ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
253 -static void qca956x_irq_init(void)
257 - for (i = ATH79_IP2_IRQ_BASE;
258 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
259 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
261 - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
263 - for (i = ATH79_IP3_IRQ_BASE;
264 - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
265 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
267 - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
269 - /* QCA956x timer init workaround has to be applied right before setting
270 - * up the clock. Else, there will be no jiffies */
271 - late_time_init = &qca956x_enable_timer_cb;
274 -void __init arch_init_irq(void)
276 - unsigned irq_wb_chan2 = -1;
277 - unsigned irq_wb_chan3 = -1;
278 - bool misc_is_ar71xx;
280 - if (mips_machtype == ATH79_MACH_GENERIC_OF) {
285 - if (soc_is_ar71xx() || soc_is_ar724x() ||
286 - soc_is_ar913x() || soc_is_ar933x()) {
289 - } else if (soc_is_ar934x() || soc_is_qca953x()) {
293 - ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
295 - if (soc_is_ar71xx() || soc_is_ar913x())
296 - misc_is_ar71xx = true;
297 - else if (soc_is_ar724x() ||
300 - soc_is_qca953x() ||
301 - soc_is_qca955x() ||
302 - soc_is_qca956x() ||
304 - misc_is_ar71xx = false;
307 - ath79_misc_irq_init(
308 - ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
309 - ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
311 - if (soc_is_ar934x())
312 - ar934x_ip2_irq_init();
313 - else if (soc_is_qca953x())
314 - qca953x_irq_init();
315 - else if (soc_is_qca955x())
316 - qca955x_irq_init();
317 - else if (soc_is_qca956x() || soc_is_tp9343())
318 - qca956x_irq_init();
320 diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
321 index 8d7ffa2e8265..7b089c07d2fa 100644
322 --- a/arch/mips/ath79/setup.c
323 +++ b/arch/mips/ath79/setup.c
325 #include <linux/clk.h>
326 #include <linux/clk-provider.h>
327 #include <linux/of_fdt.h>
328 +#include <linux/irqchip.h>
330 #include <asm/bootinfo.h>
331 #include <asm/idle.h>
332 @@ -310,6 +311,11 @@ void __init plat_time_init(void)
333 mips_hpt_frequency = cpu_clk_rate / 2;
336 +void __init arch_init_irq(void)
341 static int __init ath79_setup(void)
343 if (mips_machtype == ATH79_MACH_GENERIC_OF)