1 From 08b9cad7da5d981d595fe6d76e9675f85e23e688 Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 6 Mar 2018 09:57:15 +0100
4 Subject: [PATCH 25/27] MIPS: ath79: drop irq.c
6 all IRQ init code will flow via OF based irq chips.
8 Signed-off-by: John Crispin <john@phrozen.org>
10 arch/mips/ath79/Makefile | 2 +-
11 arch/mips/ath79/irq.c | 285 -----------------------------------------------
12 arch/mips/ath79/setup.c | 6 +
13 3 files changed, 7 insertions(+), 286 deletions(-)
14 delete mode 100644 arch/mips/ath79/irq.c
16 --- a/arch/mips/ath79/Makefile
17 +++ b/arch/mips/ath79/Makefile
19 # under the terms of the GNU General Public License version 2 as published
20 # by the Free Software Foundation.
22 -obj-y := prom.o setup.o irq.o common.o clock.o
23 +obj-y := prom.o setup.o common.o clock.o
25 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
27 --- a/arch/mips/ath79/irq.c
31 - * Atheros AR71xx/AR724x/AR913x specific interrupt handling
33 - * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
34 - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
35 - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
37 - * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
39 - * This program is free software; you can redistribute it and/or modify it
40 - * under the terms of the GNU General Public License version 2 as published
41 - * by the Free Software Foundation.
44 -#include <linux/kernel.h>
45 -#include <linux/init.h>
46 -#include <linux/interrupt.h>
47 -#include <linux/irqchip.h>
48 -#include <linux/of_irq.h>
50 -#include <asm/irq_cpu.h>
51 -#include <asm/mipsregs.h>
53 -#include <asm/mach-ath79/ath79.h>
54 -#include <asm/mach-ath79/ar71xx_regs.h>
56 -#include "machtypes.h"
59 -static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
63 - status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
65 - if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
66 - ath79_ddr_wb_flush(3);
67 - generic_handle_irq(ATH79_IP2_IRQ(0));
68 - } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
69 - ath79_ddr_wb_flush(4);
70 - generic_handle_irq(ATH79_IP2_IRQ(1));
72 - spurious_interrupt();
76 -static void ar934x_ip2_irq_init(void)
80 - for (i = ATH79_IP2_IRQ_BASE;
81 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
82 - irq_set_chip_and_handler(i, &dummy_irq_chip,
85 - irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
88 -static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
92 - status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
94 - if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
95 - ath79_ddr_wb_flush(3);
96 - generic_handle_irq(ATH79_IP2_IRQ(0));
97 - } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
98 - ath79_ddr_wb_flush(4);
99 - generic_handle_irq(ATH79_IP2_IRQ(1));
101 - spurious_interrupt();
105 -static void qca953x_irq_init(void)
109 - for (i = ATH79_IP2_IRQ_BASE;
110 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
111 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
113 - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
116 -static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
120 - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
121 - status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
124 - spurious_interrupt();
128 - if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
129 - /* TODO: flush DDR? */
130 - generic_handle_irq(ATH79_IP2_IRQ(0));
133 - if (status & QCA955X_EXT_INT_WMAC_ALL) {
134 - /* TODO: flush DDR? */
135 - generic_handle_irq(ATH79_IP2_IRQ(1));
139 -static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
143 - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
144 - status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
145 - QCA955X_EXT_INT_USB1 |
146 - QCA955X_EXT_INT_USB2;
149 - spurious_interrupt();
153 - if (status & QCA955X_EXT_INT_USB1) {
154 - /* TODO: flush DDR? */
155 - generic_handle_irq(ATH79_IP3_IRQ(0));
158 - if (status & QCA955X_EXT_INT_USB2) {
159 - /* TODO: flush DDR? */
160 - generic_handle_irq(ATH79_IP3_IRQ(1));
163 - if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
164 - /* TODO: flush DDR? */
165 - generic_handle_irq(ATH79_IP3_IRQ(2));
169 -static void qca955x_irq_init(void)
173 - for (i = ATH79_IP2_IRQ_BASE;
174 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
175 - irq_set_chip_and_handler(i, &dummy_irq_chip,
178 - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
180 - for (i = ATH79_IP3_IRQ_BASE;
181 - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
182 - irq_set_chip_and_handler(i, &dummy_irq_chip,
185 - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
188 -static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
192 - status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
193 - status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
196 - spurious_interrupt();
200 - if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
201 - /* TODO: flush DDR? */
202 - generic_handle_irq(ATH79_IP2_IRQ(0));
205 - if (status & QCA956X_EXT_INT_WMAC_ALL) {
206 - /* TODO: flsuh DDR? */
207 - generic_handle_irq(ATH79_IP2_IRQ(1));
211 -static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
215 - status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
216 - status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
217 - QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
220 - spurious_interrupt();
224 - if (status & QCA956X_EXT_INT_USB1) {
225 - /* TODO: flush DDR? */
226 - generic_handle_irq(ATH79_IP3_IRQ(0));
229 - if (status & QCA956X_EXT_INT_USB2) {
230 - /* TODO: flush DDR? */
231 - generic_handle_irq(ATH79_IP3_IRQ(1));
234 - if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
235 - /* TODO: flush DDR? */
236 - generic_handle_irq(ATH79_IP3_IRQ(2));
240 -static void qca956x_enable_timer_cb(void) {
243 - misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
244 - misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
245 - ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
248 -static void qca956x_irq_init(void)
252 - for (i = ATH79_IP2_IRQ_BASE;
253 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
254 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
256 - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
258 - for (i = ATH79_IP3_IRQ_BASE;
259 - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
260 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
262 - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
264 - /* QCA956x timer init workaround has to be applied right before setting
265 - * up the clock. Else, there will be no jiffies */
266 - late_time_init = &qca956x_enable_timer_cb;
269 -void __init arch_init_irq(void)
271 - unsigned irq_wb_chan2 = -1;
272 - unsigned irq_wb_chan3 = -1;
273 - bool misc_is_ar71xx;
275 - if (mips_machtype == ATH79_MACH_GENERIC_OF) {
280 - if (soc_is_ar71xx() || soc_is_ar724x() ||
281 - soc_is_ar913x() || soc_is_ar933x()) {
284 - } else if (soc_is_ar934x() || soc_is_qca953x()) {
288 - ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
290 - if (soc_is_ar71xx() || soc_is_ar913x())
291 - misc_is_ar71xx = true;
292 - else if (soc_is_ar724x() ||
295 - soc_is_qca953x() ||
296 - soc_is_qca955x() ||
297 - soc_is_qca956x() ||
299 - misc_is_ar71xx = false;
302 - ath79_misc_irq_init(
303 - ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
304 - ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
306 - if (soc_is_ar934x())
307 - ar934x_ip2_irq_init();
308 - else if (soc_is_qca953x())
309 - qca953x_irq_init();
310 - else if (soc_is_qca955x())
311 - qca955x_irq_init();
312 - else if (soc_is_qca956x() || soc_is_tp9343())
313 - qca956x_irq_init();
315 --- a/arch/mips/ath79/setup.c
316 +++ b/arch/mips/ath79/setup.c
318 #include <linux/clk.h>
319 #include <linux/clk-provider.h>
320 #include <linux/of_fdt.h>
321 +#include <linux/irqchip.h>
323 #include <asm/bootinfo.h>
324 #include <asm/idle.h>
325 @@ -310,6 +311,11 @@ void __init plat_time_init(void)
326 mips_hpt_frequency = cpu_clk_rate / 2;
329 +void __init arch_init_irq(void)
334 static int __init ath79_setup(void)
336 if (mips_machtype == ATH79_MACH_GENERIC_OF)