1 Index: linux-4.14.66/arch/mips/pci/pci-ar71xx.c
2 ===================================================================
3 --- linux-4.14.66.orig/arch/mips/pci/pci-ar71xx.c
4 +++ linux-4.14.66/arch/mips/pci/pci-ar71xx.c
6 struct ar71xx_pci_controller {
7 struct device_node *np;
8 void __iomem *cfg_base;
10 struct pci_controller pci_ctrl;
11 struct resource io_res;
12 struct resource mem_res;
13 - struct irq_domain *domain;
16 /* Byte lane enable bits */
17 @@ -230,104 +228,6 @@ static struct pci_ops ar71xx_pci_ops = {
18 .write = ar71xx_pci_write_config,
21 -static void ar71xx_pci_irq_handler(struct irq_desc *desc)
23 - void __iomem *base = ath79_reset_base;
24 - struct irq_chip *chip = irq_desc_get_chip(desc);
25 - struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
28 - chained_irq_enter(chip, desc);
29 - pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
30 - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
32 - if (pending & AR71XX_PCI_INT_DEV0)
33 - generic_handle_irq(irq_linear_revmap(apc->domain, 1));
35 - else if (pending & AR71XX_PCI_INT_DEV1)
36 - generic_handle_irq(irq_linear_revmap(apc->domain, 2));
38 - else if (pending & AR71XX_PCI_INT_DEV2)
39 - generic_handle_irq(irq_linear_revmap(apc->domain, 3));
41 - else if (pending & AR71XX_PCI_INT_CORE)
42 - generic_handle_irq(irq_linear_revmap(apc->domain, 4));
45 - spurious_interrupt();
46 - chained_irq_exit(chip, desc);
49 -static void ar71xx_pci_irq_unmask(struct irq_data *d)
51 - struct ar71xx_pci_controller *apc;
53 - void __iomem *base = ath79_reset_base;
56 - apc = irq_data_get_irq_chip_data(d);
57 - irq = irq_linear_revmap(apc->domain, d->irq);
59 - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
60 - __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
63 - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
66 -static void ar71xx_pci_irq_mask(struct irq_data *d)
68 - struct ar71xx_pci_controller *apc;
70 - void __iomem *base = ath79_reset_base;
73 - apc = irq_data_get_irq_chip_data(d);
74 - irq = irq_linear_revmap(apc->domain, d->irq);
76 - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
77 - __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
80 - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
83 -static struct irq_chip ar71xx_pci_irq_chip = {
84 - .name = "AR71XX PCI",
85 - .irq_mask = ar71xx_pci_irq_mask,
86 - .irq_unmask = ar71xx_pci_irq_unmask,
87 - .irq_mask_ack = ar71xx_pci_irq_mask,
90 -static int ar71xx_pci_irq_map(struct irq_domain *d,
91 - unsigned int irq, irq_hw_number_t hw)
93 - struct ar71xx_pci_controller *apc = d->host_data;
95 - irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
96 - irq_set_chip_data(irq, apc);
101 -static const struct irq_domain_ops ar71xx_pci_domain_ops = {
102 - .xlate = irq_domain_xlate_onecell,
103 - .map = ar71xx_pci_irq_map,
106 -static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
108 - void __iomem *base = ath79_reset_base;
110 - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
111 - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
113 - apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
114 - &ar71xx_pci_domain_ops, apc);
115 - irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
119 static void ar71xx_pci_reset(void)
121 ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
122 @@ -361,10 +261,6 @@ static int ar71xx_pci_probe(struct platf
123 if (IS_ERR(apc->cfg_base))
124 return PTR_ERR(apc->cfg_base);
126 - apc->irq = platform_get_irq(pdev, 0);
132 /* setup COMMAND register */
133 @@ -375,8 +271,6 @@ static int ar71xx_pci_probe(struct platf
134 /* clear bus errors */
135 ar71xx_pci_check_error(apc, 1);
137 - ar71xx_pci_irq_init(apc);
139 apc->np = pdev->dev.of_node;
140 apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
141 apc->pci_ctrl.mem_resource = &apc->mem_res;