1 From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001
2 From: Felix Fietkau <nbd@nbd.name>
3 Date: Tue, 6 Mar 2018 13:19:26 +0100
4 Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose
7 Preparation for transitioning the legacy clock setup code over
10 Signed-off-by: Felix Fietkau <nbd@nbd.name>
11 Signed-off-by: John Crispin <john@phrozen.org>
13 arch/mips/ath79/clock.c | 128 ++++++++++++++++++----------------
14 include/dt-bindings/clock/ath79-clk.h | 3 +-
15 2 files changed, 68 insertions(+), 63 deletions(-)
17 --- a/arch/mips/ath79/clock.c
18 +++ b/arch/mips/ath79/clock.c
19 @@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data
20 .clk_num = ARRAY_SIZE(clks),
23 -static struct clk *__init ath79_add_sys_clkdev(
24 - const char *id, unsigned long rate)
25 +static const char * const clk_names[ATH79_CLK_END] = {
26 + [ATH79_CLK_CPU] = "cpu",
27 + [ATH79_CLK_DDR] = "ddr",
28 + [ATH79_CLK_AHB] = "ahb",
29 + [ATH79_CLK_REF] = "ref",
32 +static const char * __init ath79_clk_name(int type)
36 + BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
37 + return clk_names[type];
40 - clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
41 +static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
44 - panic("failed to allocate %s clock structure", id);
45 + panic("failed to allocate %s clock structure", clk_names[type]);
47 - err = clk_register_clkdev(clk, id, NULL);
49 - panic("unable to register %s clock device", id);
51 + clk_register_clkdev(clk, name, NULL);
54 +static struct clk * __init ath79_set_clk(int type, unsigned long rate)
56 + const char *name = ath79_clk_name(type);
59 + clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
60 + __ath79_set_clk(type, name, clk);
64 +static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
65 + unsigned int mult, unsigned int div)
67 + const char *name = ath79_clk_name(type);
70 + clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
71 + __ath79_set_clk(type, name, clk);
75 @@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo
76 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
77 ahb_rate = cpu_rate / div;
79 - ath79_add_sys_clkdev("ref", ref_rate);
80 - clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
81 - clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
82 - clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
83 + ath79_set_clk(ATH79_CLK_REF, ref_rate);
84 + ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
85 + ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
86 + ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
88 clk_add_alias("wdt", NULL, "ahb", NULL);
89 clk_add_alias("uart", NULL, "ahb", NULL);
92 -static struct clk * __init ath79_reg_ffclk(const char *name,
93 - const char *parent_name, unsigned int mult, unsigned int div)
97 - clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
99 - panic("failed to allocate %s clock structure", name);
104 static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
107 @@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc
108 ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
109 ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
111 - clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
112 - clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
113 - clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
114 + ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
115 + ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
116 + ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
119 static void __init ar724x_clocks_init(void)
123 - ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
124 + ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
126 ar724x_clk_init(ref_clk, ath79_pll_base);
128 - /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
129 - clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
130 - clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
131 - clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
133 clk_add_alias("wdt", NULL, "ahb", NULL);
134 clk_add_alias("uart", NULL, "ahb", NULL);
136 @@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc
137 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
140 - clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
141 - ninit_mul, ref_div * out_div * cpu_div);
142 - clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
143 - ninit_mul, ref_div * out_div * ddr_div);
144 - clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
145 - ninit_mul, ref_div * out_div * ahb_div);
146 + ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
147 + ref_div * out_div * cpu_div);
148 + ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
149 + ref_div * out_div * ddr_div);
150 + ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
151 + ref_div * out_div * ahb_div);
154 static void __init ar933x_clocks_init(void)
155 @@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo
157 ref_rate = (25 * 1000 * 1000);
159 - ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
160 + ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
162 ar9330_clk_init(ref_clk, ath79_pll_base);
164 - /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
165 - clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
166 - clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
167 - clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
169 clk_add_alias("wdt", NULL, "ahb", NULL);
170 clk_add_alias("uart", NULL, "ref", NULL);
172 @@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo
174 ahb_rate = cpu_pll / (postdiv + 1);
176 - ath79_add_sys_clkdev("ref", ref_rate);
177 - clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
178 - clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
179 - clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
180 + ath79_set_clk(ATH79_CLK_REF, ref_rate);
181 + ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
182 + ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
183 + ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
185 clk_add_alias("wdt", NULL, "ref", NULL);
186 clk_add_alias("uart", NULL, "ref", NULL);
187 @@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v
189 ahb_rate = cpu_pll / (postdiv + 1);
191 - ath79_add_sys_clkdev("ref", ref_rate);
192 - ath79_add_sys_clkdev("cpu", cpu_rate);
193 - ath79_add_sys_clkdev("ddr", ddr_rate);
194 - ath79_add_sys_clkdev("ahb", ahb_rate);
195 + ath79_set_clk(ATH79_CLK_REF, ref_rate);
196 + ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
197 + ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
198 + ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
200 clk_add_alias("wdt", NULL, "ref", NULL);
201 clk_add_alias("uart", NULL, "ref", NULL);
202 @@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v
204 ahb_rate = cpu_pll / (postdiv + 1);
206 - ath79_add_sys_clkdev("ref", ref_rate);
207 - clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
208 - clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
209 - clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
210 + ath79_set_clk(ATH79_CLK_REF, ref_rate);
211 + ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
212 + ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
213 + ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
215 clk_add_alias("wdt", NULL, "ref", NULL);
216 clk_add_alias("uart", NULL, "ref", NULL);
217 @@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v
219 ahb_rate = cpu_pll / (postdiv + 1);
221 - ath79_add_sys_clkdev("ref", ref_rate);
222 - ath79_add_sys_clkdev("cpu", cpu_rate);
223 - ath79_add_sys_clkdev("ddr", ddr_rate);
224 - ath79_add_sys_clkdev("ahb", ahb_rate);
225 + ath79_set_clk(ATH79_CLK_REF, ref_rate);
226 + ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
227 + ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
228 + ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
230 clk_add_alias("wdt", NULL, "ref", NULL);
231 clk_add_alias("uart", NULL, "ref", NULL);
232 --- a/include/dt-bindings/clock/ath79-clk.h
233 +++ b/include/dt-bindings/clock/ath79-clk.h
235 #define ATH79_CLK_CPU 0
236 #define ATH79_CLK_DDR 1
237 #define ATH79_CLK_AHB 2
238 +#define ATH79_CLK_REF 3
240 -#define ATH79_CLK_END 3
241 +#define ATH79_CLK_END 4
243 #endif /* __DT_BINDINGS_ATH79_CLK_H */