2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/string.h>
20 #include <linux/kernel.h>
21 #include <linux/reboot.h>
22 #include <asm/bootinfo.h>
26 #include "../ar531x.h"
29 * Called when an interrupt is received, this function
30 * determines exactly which interrupt it was, and it
31 * invokes the appropriate handler.
33 * Implicitly, we also define interrupt priority by
34 * choosing which to dispatch first.
36 asmlinkage
void ar5312_irq_dispatch(void)
38 int pending
= read_c0_status() & read_c0_cause();
40 if (pending
& CAUSEF_IP2
)
41 do_IRQ(AR5312_IRQ_WLAN0_INTRS
);
42 else if (pending
& CAUSEF_IP3
)
43 do_IRQ(AR5312_IRQ_ENET0_INTRS
);
44 else if (pending
& CAUSEF_IP4
)
45 do_IRQ(AR5312_IRQ_ENET1_INTRS
);
46 else if (pending
& CAUSEF_IP5
)
47 do_IRQ(AR5312_IRQ_WLAN1_INTRS
);
48 else if (pending
& CAUSEF_IP6
) {
49 unsigned int ar531x_misc_intrs
= sysRegRead(AR531X_ISR
) & sysRegRead(AR531X_IMR
);
51 if (ar531x_misc_intrs
& AR531X_ISR_TIMER
) {
52 do_IRQ(AR531X_MISC_IRQ_TIMER
);
53 (void)sysRegRead(AR531X_TIMER
);
54 } else if (ar531x_misc_intrs
& AR531X_ISR_AHBPROC
)
55 do_IRQ(AR531X_MISC_IRQ_AHB_PROC
);
56 else if ((ar531x_misc_intrs
& AR531X_ISR_UART0
))
57 do_IRQ(AR531X_MISC_IRQ_UART0
);
58 else if (ar531x_misc_intrs
& AR531X_ISR_WD
)
59 do_IRQ(AR531X_MISC_IRQ_WATCHDOG
);
61 do_IRQ(AR531X_MISC_IRQ_NONE
);
62 } else if (pending
& CAUSEF_IP7
) {
63 do_IRQ(AR531X_IRQ_CPU_CLOCK
);
68 /* Enable the specified AR531X_MISC_IRQ interrupt */
70 ar5312_misc_intr_enable(unsigned int irq
)
74 imr
= sysRegRead(AR531X_IMR
);
75 imr
|= (1 << (irq
- AR531X_MISC_IRQ_BASE
- 1));
76 sysRegWrite(AR531X_IMR
, imr
);
77 sysRegRead(AR531X_IMR
); /* flush write buffer */
80 /* Disable the specified AR531X_MISC_IRQ interrupt */
82 ar5312_misc_intr_disable(unsigned int irq
)
86 imr
= sysRegRead(AR531X_IMR
);
87 imr
&= ~(1 << (irq
- AR531X_MISC_IRQ_BASE
- 1));
88 sysRegWrite(AR531X_IMR
, imr
);
89 sysRegRead(AR531X_IMR
); /* flush write buffer */
92 /* Turn on the specified AR531X_MISC_IRQ interrupt */
94 ar5312_misc_intr_startup(unsigned int irq
)
96 ar5312_misc_intr_enable(irq
);
100 /* Turn off the specified AR531X_MISC_IRQ interrupt */
102 ar5312_misc_intr_shutdown(unsigned int irq
)
104 ar5312_misc_intr_disable(irq
);
108 ar5312_misc_intr_ack(unsigned int irq
)
110 ar5312_misc_intr_disable(irq
);
114 ar5312_misc_intr_end(unsigned int irq
)
116 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
117 ar5312_misc_intr_enable(irq
);
120 static struct irq_chip ar5312_misc_intr_controller
= {
121 .typename
= "AR5312 misc",
122 .startup
= ar5312_misc_intr_startup
,
123 .shutdown
= ar5312_misc_intr_shutdown
,
124 .enable
= ar5312_misc_intr_enable
,
125 .disable
= ar5312_misc_intr_disable
,
126 .ack
= ar5312_misc_intr_ack
,
127 .end
= ar5312_misc_intr_end
,
130 static irqreturn_t
ar5312_ahb_proc_handler(int cpl
, void *dev_id
)
132 u32 proc1
= sysRegRead(AR531X_PROC1
);
133 u32 procAddr
= sysRegRead(AR531X_PROCADDR
); /* clears error state */
134 u32 dma1
= sysRegRead(AR531X_DMA1
);
135 u32 dmaAddr
= sysRegRead(AR531X_DMAADDR
); /* clears error state */
137 printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
138 procAddr
, proc1
, dmaAddr
, dma1
);
140 machine_restart("AHB error"); /* Catastrophic failure */
145 static struct irqaction ar5312_ahb_proc_interrupt
= {
146 .handler
= ar5312_ahb_proc_handler
,
147 .flags
= IRQF_DISABLED
,
148 .name
= "ar5312_ahb_proc_interrupt",
152 static struct irqaction cascade
= {
153 .handler
= no_action
,
154 .flags
= IRQF_DISABLED
,
158 void __init
ar5312_misc_intr_init(int irq_base
)
162 for (i
= irq_base
; i
< irq_base
+ AR531X_MISC_IRQ_COUNT
; i
++) {
163 irq_desc
[i
].status
= IRQ_DISABLED
;
164 irq_desc
[i
].action
= NULL
;
165 irq_desc
[i
].depth
= 1;
166 irq_desc
[i
].chip
= &ar5312_misc_intr_controller
;
168 setup_irq(AR531X_MISC_IRQ_AHB_PROC
, &ar5312_ahb_proc_interrupt
);
169 setup_irq(AR5312_IRQ_MISC_INTRS
, &cascade
);