2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/string.h>
20 #include <linux/kernel.h>
21 #include <linux/reboot.h>
22 #include <asm/bootinfo.h>
31 * Called when an interrupt is received, this function
32 * determines exactly which interrupt it was, and it
33 * invokes the appropriate handler.
35 * Implicitly, we also define interrupt priority by
36 * choosing which to dispatch first.
38 asmlinkage
void ar5312_irq_dispatch(void)
40 int pending
= read_c0_status() & read_c0_cause();
42 if (pending
& CAUSEF_IP2
)
43 do_IRQ(AR5312_IRQ_WLAN0_INTRS
);
44 else if (pending
& CAUSEF_IP3
)
45 do_IRQ(AR5312_IRQ_ENET0_INTRS
);
46 else if (pending
& CAUSEF_IP4
)
47 do_IRQ(AR5312_IRQ_ENET1_INTRS
);
48 else if (pending
& CAUSEF_IP5
)
49 do_IRQ(AR5312_IRQ_WLAN1_INTRS
);
50 else if (pending
& CAUSEF_IP6
) {
51 unsigned int ar531x_misc_intrs
= sysRegRead(AR531X_ISR
) & sysRegRead(AR531X_IMR
);
53 if (ar531x_misc_intrs
& AR531X_ISR_TIMER
) {
54 do_IRQ(AR531X_MISC_IRQ_TIMER
);
55 (void)sysRegRead(AR531X_TIMER
);
56 } else if (ar531x_misc_intrs
& AR531X_ISR_AHBPROC
)
57 do_IRQ(AR531X_MISC_IRQ_AHB_PROC
);
58 else if (ar531x_misc_intrs
& AR531X_ISR_GPIO
)
59 ar5312_gpio_irq_dispatch();
60 else if ((ar531x_misc_intrs
& AR531X_ISR_UART0
))
61 do_IRQ(AR531X_MISC_IRQ_UART0
);
62 else if (ar531x_misc_intrs
& AR531X_ISR_WD
)
63 do_IRQ(AR531X_MISC_IRQ_WATCHDOG
);
65 do_IRQ(AR531X_MISC_IRQ_NONE
);
66 } else if (pending
& CAUSEF_IP7
) {
67 do_IRQ(AR531X_IRQ_CPU_CLOCK
);
72 /* Enable the specified AR531X_MISC_IRQ interrupt */
74 ar5312_misc_intr_enable(unsigned int irq
)
78 imr
= sysRegRead(AR531X_IMR
);
79 imr
|= (1 << (irq
- AR531X_MISC_IRQ_BASE
- 1));
80 sysRegWrite(AR531X_IMR
, imr
);
81 sysRegRead(AR531X_IMR
); /* flush write buffer */
84 /* Disable the specified AR531X_MISC_IRQ interrupt */
86 ar5312_misc_intr_disable(unsigned int irq
)
90 imr
= sysRegRead(AR531X_IMR
);
91 imr
&= ~(1 << (irq
- AR531X_MISC_IRQ_BASE
- 1));
92 sysRegWrite(AR531X_IMR
, imr
);
93 sysRegRead(AR531X_IMR
); /* flush write buffer */
96 /* Turn on the specified AR531X_MISC_IRQ interrupt */
98 ar5312_misc_intr_startup(unsigned int irq
)
100 ar5312_misc_intr_enable(irq
);
104 /* Turn off the specified AR531X_MISC_IRQ interrupt */
106 ar5312_misc_intr_shutdown(unsigned int irq
)
108 ar5312_misc_intr_disable(irq
);
112 ar5312_misc_intr_ack(unsigned int irq
)
114 ar5312_misc_intr_disable(irq
);
118 ar5312_misc_intr_end(unsigned int irq
)
120 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
121 ar5312_misc_intr_enable(irq
);
124 static struct irq_chip ar5312_misc_intr_controller
= {
125 .typename
= "AR5312 misc",
126 .startup
= ar5312_misc_intr_startup
,
127 .shutdown
= ar5312_misc_intr_shutdown
,
128 .enable
= ar5312_misc_intr_enable
,
129 .disable
= ar5312_misc_intr_disable
,
130 .ack
= ar5312_misc_intr_ack
,
131 .end
= ar5312_misc_intr_end
,
134 static irqreturn_t
ar5312_ahb_proc_handler(int cpl
, void *dev_id
)
136 u32 proc1
= sysRegRead(AR531X_PROC1
);
137 u32 procAddr
= sysRegRead(AR531X_PROCADDR
); /* clears error state */
138 u32 dma1
= sysRegRead(AR531X_DMA1
);
139 u32 dmaAddr
= sysRegRead(AR531X_DMAADDR
); /* clears error state */
141 printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
142 procAddr
, proc1
, dmaAddr
, dma1
);
144 machine_restart("AHB error"); /* Catastrophic failure */
149 static struct irqaction ar5312_ahb_proc_interrupt
= {
150 .handler
= ar5312_ahb_proc_handler
,
151 .flags
= IRQF_DISABLED
,
152 .name
= "ar5312_ahb_proc_interrupt",
156 static struct irqaction cascade
= {
157 .handler
= no_action
,
158 .flags
= IRQF_DISABLED
,
162 void __init
ar5312_misc_intr_init(int irq_base
)
166 for (i
= irq_base
; i
< irq_base
+ AR531X_MISC_IRQ_COUNT
; i
++) {
167 irq_desc
[i
].status
= IRQ_DISABLED
;
168 irq_desc
[i
].action
= NULL
;
169 irq_desc
[i
].depth
= 1;
170 irq_desc
[i
].chip
= &ar5312_misc_intr_controller
;
172 setup_irq(AR531X_MISC_IRQ_AHB_PROC
, &ar5312_ahb_proc_interrupt
);
173 setup_irq(AR5312_IRQ_MISC_INTRS
, &cascade
);