2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/platform_device.h>
23 #include <linux/kernel.h>
24 #include <linux/reboot.h>
25 #include <asm/bootinfo.h>
26 #include <asm/reboot.h>
31 #include <linux/leds.h>
35 static int is_5312
= 0;
36 static struct platform_device
*ar5312_devs
[6];
38 static struct resource ar5312_eth0_res
[] = {
40 .name
= "eth0_membase",
41 .flags
= IORESOURCE_MEM
,
42 .start
= KSEG1ADDR(AR531X_ENET0
),
43 .end
= KSEG1ADDR(AR531X_ENET0
+ 0x2000),
47 .flags
= IORESOURCE_IRQ
,
48 .start
= AR5312_IRQ_ENET0_INTRS
,
49 .end
= AR5312_IRQ_ENET0_INTRS
,
52 static struct ar531x_eth ar5312_eth0_data
= {
55 .reset_base
= AR531X_RESET
,
56 .reset_mac
= AR531X_RESET_ENET0
,
57 .reset_phy
= AR531X_RESET_EPHY0
,
58 .phy_base
= KSEG1ADDR(AR531X_ENET0
),
61 static struct resource ar5312_eth1_res
[] = {
63 .name
= "eth1_membase",
64 .flags
= IORESOURCE_MEM
,
65 .start
= KSEG1ADDR(AR531X_ENET1
),
66 .end
= KSEG1ADDR(AR531X_ENET1
+ 0x2000),
70 .flags
= IORESOURCE_IRQ
,
71 .start
= AR5312_IRQ_ENET1_INTRS
,
72 .end
= AR5312_IRQ_ENET1_INTRS
,
75 static struct ar531x_eth ar5312_eth1_data
= {
78 .reset_base
= AR531X_RESET
,
79 .reset_mac
= AR531X_RESET_ENET1
,
80 .reset_phy
= AR531X_RESET_EPHY1
,
81 .phy_base
= KSEG1ADDR(AR531X_ENET1
),
84 static struct platform_device ar5312_eth
[] = {
88 .dev
.platform_data
= &ar5312_eth0_data
,
89 .resource
= ar5312_eth0_res
,
90 .num_resources
= ARRAY_SIZE(ar5312_eth0_res
)
95 .dev
.platform_data
= &ar5312_eth1_data
,
96 .resource
= ar5312_eth1_res
,
97 .num_resources
= ARRAY_SIZE(ar5312_eth1_res
)
103 * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
104 * of ENET1. Atheros calls it 'twisted' for a reason :)
106 static struct resource ar231x_eth0_res
[] = {
108 .name
= "eth0_membase",
109 .flags
= IORESOURCE_MEM
,
110 .start
= KSEG1ADDR(AR531X_ENET1
),
111 .end
= KSEG1ADDR(AR531X_ENET1
+ 0x2000),
115 .flags
= IORESOURCE_IRQ
,
116 .start
= AR5312_IRQ_ENET1_INTRS
,
117 .end
= AR5312_IRQ_ENET1_INTRS
,
120 static struct ar531x_eth ar231x_eth0_data
= {
123 .reset_base
= AR531X_RESET
,
124 .reset_mac
= AR531X_RESET_ENET1
,
125 .reset_phy
= AR531X_RESET_EPHY1
,
126 .phy_base
= KSEG1ADDR(AR531X_ENET0
),
128 static struct platform_device ar231x_eth0
= {
130 .name
= "ar531x-eth",
131 .dev
.platform_data
= &ar231x_eth0_data
,
132 .resource
= ar231x_eth0_res
,
133 .num_resources
= ARRAY_SIZE(ar231x_eth0_res
)
137 static struct platform_device ar5312_wmac
[] = {
140 .name
= "ar531x-wmac",
144 .name
= "ar531x-wmac",
148 static struct physmap_flash_data ar5312_flash_data
= {
152 static struct resource ar5312_flash_resource
= {
153 .start
= AR531X_FLASH
,
154 .end
= AR531X_FLASH
+ 0x800000 - 1,
155 .flags
= IORESOURCE_MEM
,
158 static struct platform_device ar5312_physmap_flash
= {
159 .name
= "physmap-flash",
162 .platform_data
= &ar5312_flash_data
,
165 .resource
= &ar5312_flash_resource
,
168 #ifdef CONFIG_LEDS_GPIO
169 static struct gpio_led ar5312_leds
[] = {
170 { .name
= "wlan", .gpio
= 0, .active_low
= 1, },
173 static const struct gpio_led_platform_data ar5312_led_data
= {
174 .num_leds
= ARRAY_SIZE(ar5312_leds
),
175 .leds
= (void *) ar5312_leds
,
178 static struct platform_device ar5312_gpio_leds
= {
182 .platform_data
= (void *) &ar5312_led_data
,
188 * NB: This mapping size is larger than the actual flash size,
189 * but this shouldn't be a problem here, because the flash
190 * will simply be mapped multiple times.
192 static char __init
*ar5312_flash_limit(void)
196 * Configure flash bank 0.
197 * Assume 8M window size. Flash will be aliased if it's smaller
202 (0x01 << FLASHCTL_IDCY_S
) |
203 (0x07 << FLASHCTL_WST1_S
) |
204 (0x07 << FLASHCTL_WST2_S
) |
205 (sysRegRead(AR531X_FLASHCTL0
) & FLASHCTL_MW
);
207 sysRegWrite(AR531X_FLASHCTL0
, ctl
);
209 /* Disable other flash banks */
210 sysRegWrite(AR531X_FLASHCTL1
,
211 sysRegRead(AR531X_FLASHCTL1
) & ~(FLASHCTL_E
| FLASHCTL_AC
));
213 sysRegWrite(AR531X_FLASHCTL2
,
214 sysRegRead(AR531X_FLASHCTL2
) & ~(FLASHCTL_E
| FLASHCTL_AC
));
216 return (char *) KSEG1ADDR(AR531X_FLASH
+ 0x800000);
219 static struct ar531x_config __init
*init_wmac(int unit
)
221 struct ar531x_config
*config
;
223 config
= (struct ar531x_config
*) kzalloc(sizeof(struct ar531x_config
), GFP_KERNEL
);
224 config
->board
= board_config
;
225 config
->radio
= radio_config
;
227 config
->tag
= (u_int16_t
) ((sysRegRead(AR531X_REV
) >> AR531X_REV_WMAC_MIN_S
) & AR531X_REV_CHIP
);
232 int __init
ar5312_init_devices(void)
234 struct ar531x_boarddata
*bcfg
;
242 /* Locate board/radio config data */
243 ar531x_find_config(ar5312_flash_limit());
244 bcfg
= (struct ar531x_boarddata
*) board_config
;
248 * Chip IDs and hardware detection for some Atheros
249 * models are really broken!
251 * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
252 * as indication for AR2312, which is otherwise
253 * indistinguishable from the real AR5312.
256 radio
= radio_config
+ AR531X_RADIO_MASK_OFF
;
257 if ((*((u32
*) radio
) & AR531X_RADIO0_MASK
) == 0)
258 bcfg
->config
|= BD_ISCASPER
;
262 /* AR2313 has CPU minor rev. 10 */
263 if ((current_cpu_data
.processor_id
& 0xff) == 0x0a)
264 mips_machtype
= MACH_ATHEROS_AR2313
;
266 /* AR2312 shares the same Silicon ID as AR5312 */
267 else if (bcfg
->config
& BD_ISCASPER
)
268 mips_machtype
= MACH_ATHEROS_AR2312
;
270 /* Everything else is probably AR5312 or compatible */
272 mips_machtype
= MACH_ATHEROS_AR5312
;
274 ar5312_eth0_data
.board_config
= board_config
;
275 ar5312_eth1_data
.board_config
= board_config
;
277 /* fixup flash width */
278 fctl
= sysRegRead(AR531X_FLASHCTL
) & FLASHCTL_MW
;
281 ar5312_flash_data
.width
= 2;
285 ar5312_flash_data
.width
= 1;
289 ar5312_devs
[dev
++] = &ar5312_physmap_flash
;
291 #ifdef CONFIG_LEDS_GPIO
292 ar5312_leds
[0].gpio
= bcfg
->sysLedGpio
;
293 ar5312_devs
[dev
++] = &ar5312_gpio_leds
;
296 if (!memcmp(bcfg
->enet0Mac
, "\xff\xff\xff\xff\xff\xff", 6))
297 memcpy(bcfg
->enet0Mac
, bcfg
->enet1Mac
, 6);
299 if (memcmp(bcfg
->enet0Mac
, bcfg
->enet1Mac
, 6) == 0) {
300 /* ENET0 and ENET1 have the same mac.
301 * Increment the one from ENET1 */
302 c
= bcfg
->enet1Mac
+ 5;
303 while ((c
>= (char *) bcfg
->enet1Mac
) && !(++(*c
)))
307 switch(mips_machtype
) {
308 case MACH_ATHEROS_AR5312
:
309 ar5312_eth0_data
.macaddr
= bcfg
->enet0Mac
;
310 ar5312_eth1_data
.macaddr
= bcfg
->enet1Mac
;
311 ar5312_devs
[dev
++] = &ar5312_eth
[0];
312 ar5312_devs
[dev
++] = &ar5312_eth
[1];
314 case MACH_ATHEROS_AR2312
:
315 case MACH_ATHEROS_AR2313
:
316 ar231x_eth0_data
.macaddr
= bcfg
->enet0Mac
;
317 ar5312_devs
[dev
++] = &ar231x_eth0
;
318 ar5312_flash_data
.width
= 1;
323 if (mips_machtype
== MACH_ATHEROS_AR5312
) {
324 if (*((u32
*) radio
) & AR531X_RADIO0_MASK
) {
325 ar5312_wmac
[0].dev
.platform_data
= init_wmac(0);
326 ar5312_devs
[dev
++] = &ar5312_wmac
[0];
329 if (*((u32
*) radio
) & AR531X_RADIO1_MASK
) {
330 ar5312_wmac
[1].dev
.platform_data
= init_wmac(1);
331 ar5312_devs
[dev
++] = &ar5312_wmac
[1];
335 return platform_add_devices(ar5312_devs
, dev
);
339 static void ar5312_halt(void)
344 static void ar5312_power_off(void)
350 static void ar5312_restart(char *command
)
352 /* reset the system */
353 for(;;) sysRegWrite(AR531X_RESET
, AR531X_RESET_SYSTEM
);
358 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
359 * to determine the predevisor value.
361 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE
[4] = {
369 static unsigned int __init
ar5312_cpu_frequency(void)
372 unsigned int predivide_mask
, predivide_shift
;
373 unsigned int multiplier_mask
, multiplier_shift
;
374 unsigned int clockCtl1
, preDivideSelect
, preDivisor
, multiplier
;
375 unsigned int doubler_mask
;
376 unsigned int wisoc_revision
;
378 /* Trust the bootrom's idea of cpu frequency. */
379 if ((result
= sysRegRead(AR5312_SCRATCH
)))
382 wisoc_revision
= (sysRegRead(AR531X_REV
) & AR531X_REV_MAJ
) >> AR531X_REV_MAJ_S
;
383 if (wisoc_revision
== AR531X_REV_MAJ_AR2313
) {
384 predivide_mask
= AR2313_CLOCKCTL1_PREDIVIDE_MASK
;
385 predivide_shift
= AR2313_CLOCKCTL1_PREDIVIDE_SHIFT
;
386 multiplier_mask
= AR2313_CLOCKCTL1_MULTIPLIER_MASK
;
387 multiplier_shift
= AR2313_CLOCKCTL1_MULTIPLIER_SHIFT
;
388 doubler_mask
= AR2313_CLOCKCTL1_DOUBLER_MASK
;
389 } else { /* AR5312 and AR2312 */
390 predivide_mask
= AR5312_CLOCKCTL1_PREDIVIDE_MASK
;
391 predivide_shift
= AR5312_CLOCKCTL1_PREDIVIDE_SHIFT
;
392 multiplier_mask
= AR5312_CLOCKCTL1_MULTIPLIER_MASK
;
393 multiplier_shift
= AR5312_CLOCKCTL1_MULTIPLIER_SHIFT
;
394 doubler_mask
= AR5312_CLOCKCTL1_DOUBLER_MASK
;
398 * Clocking is derived from a fixed 40MHz input clock.
400 * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
401 * sysFreq = cpuFreq / 4 (used for APB clock, serial,
402 * flash, Timer, Watchdog Timer)
404 * cntFreq = cpuFreq / 2 (use for CPU count/compare)
406 * So, for example, with a PLL multiplier of 5, we have
412 * We compute the CPU frequency, based on PLL settings.
415 clockCtl1
= sysRegRead(AR5312_CLOCKCTL1
);
416 preDivideSelect
= (clockCtl1
& predivide_mask
) >> predivide_shift
;
417 preDivisor
= CLOCKCTL1_PREDIVIDE_TABLE
[preDivideSelect
];
418 multiplier
= (clockCtl1
& multiplier_mask
) >> multiplier_shift
;
420 if (clockCtl1
& doubler_mask
) {
421 multiplier
= multiplier
<< 1;
423 return (40000000 / preDivisor
) * multiplier
;
426 static inline int ar5312_sys_frequency(void)
428 return ar5312_cpu_frequency() / 4;
431 static void __init
ar5312_time_init(void)
433 mips_hpt_frequency
= ar5312_cpu_frequency() / 2;
437 void __init
ar5312_prom_init(void)
439 u32 memsize
, memcfg
, bank0AC
, bank1AC
;
443 /* Detect memory size */
444 memcfg
= sysRegRead(AR531X_MEM_CFG1
);
445 bank0AC
= (memcfg
& MEM_CFG1_AC0
) >> MEM_CFG1_AC0_S
;
446 bank1AC
= (memcfg
& MEM_CFG1_AC1
) >> MEM_CFG1_AC1_S
;
447 memsize
= (bank0AC
? (1 << (bank0AC
+1)) : 0)
448 + (bank1AC
? (1 << (bank1AC
+1)) : 0);
450 add_memory_region(0, memsize
, BOOT_MEM_RAM
);
452 /* Initialize it to AR5312 for now. Real detection will be done
453 * in ar5312_init_devices() */
454 mips_machtype
= MACH_ATHEROS_AR5312
;
457 void __init
ar5312_plat_setup(void)
459 /* Clear any lingering AHB errors */
460 sysRegRead(AR531X_PROCADDR
);
461 sysRegRead(AR531X_DMAADDR
);
462 sysRegWrite(AR531X_WD_CTRL
, AR531X_WD_CTRL_IGNORE_EXPIRATION
);
464 board_time_init
= ar5312_time_init
;
466 _machine_restart
= ar5312_restart
;
467 _machine_halt
= ar5312_halt
;
468 pm_power_off
= ar5312_power_off
;
470 serial_setup(KSEG1ADDR(AR531X_UART0
), ar5312_sys_frequency());
473 arch_initcall(ar5312_init_devices
);