2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/string.h>
20 #include <linux/kernel.h>
21 #include <linux/reboot.h>
22 #include <linux/interrupt.h>
23 #include <linux/bitops.h>
24 #include <asm/bootinfo.h>
25 #include <asm/irq_cpu.h>
31 static u32 gpiointmask
= 0, gpiointval
= 0;
33 static inline void ar5315_gpio_irq(void)
36 sysRegWrite(AR5315_ISR
, sysRegRead(AR5315_IMR
) | ~AR5315_ISR_GPIO
);
38 /* only do one gpio interrupt at a time */
39 pend
= (sysRegRead(AR5315_GPIO_DI
) ^ gpiointval
) & gpiointmask
;
43 do_IRQ(AR531X_GPIO_IRQ_BASE
+ fls(pend
) - 1);
48 * Called when an interrupt is received, this function
49 * determines exactly which interrupt it was, and it
50 * invokes the appropriate handler.
52 * Implicitly, we also define interrupt priority by
53 * choosing which to dispatch first.
55 asmlinkage
void ar5315_irq_dispatch(void)
57 int pending
= read_c0_status() & read_c0_cause();
59 if (pending
& CAUSEF_IP3
)
60 do_IRQ(AR5315_IRQ_WLAN0_INTRS
);
61 else if (pending
& CAUSEF_IP4
)
62 do_IRQ(AR5315_IRQ_ENET0_INTRS
);
64 else if (pending
& CAUSEF_IP5
)
65 ar5315_pci_irq(AR5315_IRQ_LCBUS_PCI
);
67 else if (pending
& CAUSEF_IP2
) {
68 unsigned int ar531x_misc_intrs
= sysRegRead(AR5315_ISR
) & sysRegRead(AR5315_IMR
);
70 if (ar531x_misc_intrs
& AR5315_ISR_SPI
)
71 do_IRQ(AR531X_MISC_IRQ_SPI
);
72 else if (ar531x_misc_intrs
& AR5315_ISR_TIMER
)
73 do_IRQ(AR531X_MISC_IRQ_TIMER
);
74 else if (ar531x_misc_intrs
& AR5315_ISR_AHB
)
75 do_IRQ(AR531X_MISC_IRQ_AHB_PROC
);
76 else if (ar531x_misc_intrs
& AR5315_ISR_GPIO
)
78 else if (ar531x_misc_intrs
& AR5315_ISR_UART0
)
79 do_IRQ(AR531X_MISC_IRQ_UART0
);
80 else if (ar531x_misc_intrs
& AR5315_ISR_WD
)
81 do_IRQ(AR531X_MISC_IRQ_WATCHDOG
);
83 do_IRQ(AR531X_MISC_IRQ_NONE
);
84 } else if (pending
& CAUSEF_IP7
)
85 do_IRQ(AR531X_IRQ_CPU_CLOCK
);
89 static inline void pci_abort_irq(void)
91 sysRegWrite(AR5315_PCI_INT_STATUS
, AR5315_PCI_ABORT_INT
);
92 (void)sysRegRead(AR5315_PCI_INT_STATUS
); /* flush write to hardware */
95 static inline void pci_ack_irq(void)
97 sysRegWrite(AR5315_PCI_INT_STATUS
, AR5315_PCI_EXT_INT
);
98 (void)sysRegRead(AR5315_PCI_INT_STATUS
); /* flush write to hardware */
101 void ar5315_pci_irq(int irq
)
103 if (sysRegRead(AR5315_PCI_INT_STATUS
) == AR5315_PCI_ABORT_INT
)
112 static void ar5315_gpio_intr_enable(unsigned int irq
)
115 gpio
= irq
- AR531X_GPIO_IRQ_BASE
;
119 /* reconfigure GPIO line as input */
120 sysRegMask(AR5315_GPIO_CR
, AR5315_GPIO_CR_M(gpio
), AR5315_GPIO_CR_I(gpio
));
122 /* Enable interrupt with edge detection */
123 sysRegMask(AR5315_GPIO_INT
, AR5315_GPIO_INT_M
| AR5315_GPIO_INT_LVL_M
, gpio
| AR5315_GPIO_INT_LVL(3));
126 static void ar5315_gpio_intr_disable(unsigned int irq
)
129 gpio
= irq
- AR531X_GPIO_IRQ_BASE
;
132 gpiointmask
&= ~mask
;
134 /* Disable interrupt with edge detection */
135 sysRegMask(AR5315_GPIO_INT
, AR5315_GPIO_INT_M
| AR5315_GPIO_INT_LVL_M
, gpio
| AR5315_GPIO_INT_LVL(0));
138 /* Turn on the specified AR531X_MISC_IRQ interrupt */
139 static unsigned int ar5315_gpio_intr_startup(unsigned int irq
)
141 ar5315_gpio_intr_enable(irq
);
145 /* Turn off the specified AR531X_MISC_IRQ interrupt */
147 ar5315_gpio_intr_shutdown(unsigned int irq
)
149 ar5315_gpio_intr_disable(irq
);
153 ar5315_gpio_intr_ack(unsigned int irq
)
155 ar5315_gpio_intr_disable(irq
);
159 ar5315_gpio_intr_end(unsigned int irq
)
161 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
162 ar5315_gpio_intr_enable(irq
);
165 static struct irq_chip ar5315_gpio_intr_controller
= {
166 .typename
= "AR5315 GPIO",
167 .startup
= ar5315_gpio_intr_startup
,
168 .shutdown
= ar5315_gpio_intr_shutdown
,
169 .enable
= ar5315_gpio_intr_enable
,
170 .disable
= ar5315_gpio_intr_disable
,
171 .ack
= ar5315_gpio_intr_ack
,
172 .end
= ar5315_gpio_intr_end
,
176 /* Enable the specified AR531X_MISC_IRQ interrupt */
178 ar5315_misc_intr_enable(unsigned int irq
)
182 imr
= sysRegRead(AR5315_IMR
);
185 case AR531X_MISC_IRQ_SPI
:
186 imr
|= AR5315_ISR_SPI
;
189 case AR531X_MISC_IRQ_TIMER
:
190 imr
|= AR5315_ISR_TIMER
;
193 case AR531X_MISC_IRQ_AHB_PROC
:
194 imr
|= AR5315_ISR_AHB
;
197 case AR531X_MISC_IRQ_AHB_DMA
:
201 case AR531X_MISC_IRQ_GPIO
:
202 imr
|= AR5315_ISR_GPIO
;
205 case AR531X_MISC_IRQ_UART0
:
206 imr
|= AR5315_ISR_UART0
;
210 case AR531X_MISC_IRQ_WATCHDOG
:
211 imr
|= AR5315_ISR_WD
;
214 case AR531X_MISC_IRQ_LOCAL
:
219 sysRegWrite(AR5315_IMR
, imr
);
220 imr
=sysRegRead(AR5315_IMR
); /* flush write buffer */
223 /* Disable the specified AR531X_MISC_IRQ interrupt */
225 ar5315_misc_intr_disable(unsigned int irq
)
229 imr
= sysRegRead(AR5315_IMR
);
232 case AR531X_MISC_IRQ_SPI
:
233 imr
&= ~AR5315_ISR_SPI
;
236 case AR531X_MISC_IRQ_TIMER
:
237 imr
&= (~AR5315_ISR_TIMER
);
240 case AR531X_MISC_IRQ_AHB_PROC
:
241 imr
&= (~AR5315_ISR_AHB
);
244 case AR531X_MISC_IRQ_AHB_DMA
:
248 case AR531X_MISC_IRQ_GPIO
:
249 imr
&= ~AR5315_ISR_GPIO
;
252 case AR531X_MISC_IRQ_UART0
:
253 imr
&= (~AR5315_ISR_UART0
);
256 case AR531X_MISC_IRQ_WATCHDOG
:
257 imr
&= (~AR5315_ISR_WD
);
260 case AR531X_MISC_IRQ_LOCAL
:
265 sysRegWrite(AR5315_IMR
, imr
);
266 sysRegRead(AR5315_IMR
); /* flush write buffer */
269 /* Turn on the specified AR531X_MISC_IRQ interrupt */
271 ar5315_misc_intr_startup(unsigned int irq
)
273 ar5315_misc_intr_enable(irq
);
277 /* Turn off the specified AR531X_MISC_IRQ interrupt */
279 ar5315_misc_intr_shutdown(unsigned int irq
)
281 ar5315_misc_intr_disable(irq
);
285 ar5315_misc_intr_ack(unsigned int irq
)
287 ar5315_misc_intr_disable(irq
);
291 ar5315_misc_intr_end(unsigned int irq
)
293 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
294 ar5315_misc_intr_enable(irq
);
297 static struct irq_chip ar5315_misc_intr_controller
= {
298 .typename
= "AR5315 misc",
299 .startup
= ar5315_misc_intr_startup
,
300 .shutdown
= ar5315_misc_intr_shutdown
,
301 .enable
= ar5315_misc_intr_enable
,
302 .disable
= ar5315_misc_intr_disable
,
303 .ack
= ar5315_misc_intr_ack
,
304 .end
= ar5315_misc_intr_end
,
307 static irqreturn_t
ar5315_ahb_proc_handler(int cpl
, void *dev_id
)
309 sysRegWrite(AR5315_AHB_ERR0
,AHB_ERROR_DET
);
310 sysRegRead(AR5315_AHB_ERR1
);
312 printk("AHB fatal error\n");
313 machine_restart("AHB error"); /* Catastrophic failure */
318 static struct irqaction ar5315_ahb_proc_interrupt
= {
319 .handler
= ar5315_ahb_proc_handler
,
320 .flags
= IRQF_DISABLED
,
321 .name
= "ar5315_ahb_proc_interrupt",
325 static struct irqaction cascade
= {
326 .handler
= no_action
,
327 .flags
= IRQF_DISABLED
,
331 static void ar5315_gpio_intr_init(int irq_base
)
335 for (i
= irq_base
; i
< irq_base
+ AR531X_GPIO_IRQ_COUNT
; i
++) {
336 irq_desc
[i
].status
= IRQ_DISABLED
;
337 irq_desc
[i
].action
= NULL
;
338 irq_desc
[i
].depth
= 1;
339 irq_desc
[i
].chip
= &ar5315_gpio_intr_controller
;
341 setup_irq(AR531X_MISC_IRQ_GPIO
, &cascade
);
342 gpiointval
= sysRegRead(AR5315_GPIO_DI
);
345 void ar5315_misc_intr_init(int irq_base
)
349 for (i
= irq_base
; i
< irq_base
+ AR531X_MISC_IRQ_COUNT
; i
++) {
350 irq_desc
[i
].status
= IRQ_DISABLED
;
351 irq_desc
[i
].action
= NULL
;
352 irq_desc
[i
].depth
= 1;
353 irq_desc
[i
].chip
= &ar5315_misc_intr_controller
;
355 setup_irq(AR531X_MISC_IRQ_AHB_PROC
, &ar5315_ahb_proc_interrupt
);
356 setup_irq(AR5315_IRQ_MISC_INTRS
, &cascade
);
357 ar5315_gpio_intr_init(AR531X_GPIO_IRQ_BASE
);