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[openwrt/staging/chunkeey.git] / target / linux / atheros / patches-3.10 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
10 @@ -5,7 +5,7 @@
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
13 default y
14 - depends on PCI
15 + depends on (PCI || ATHEROS_AR231X)
16 ---help---
17 If you have a network (Ethernet) card belonging to this class, say Y
18 and read the Ethernet-HOWTO, available from
19 @@ -85,4 +85,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
21 will be called alx.
22
23 +config NET_AR231X
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATHEROS_AR231X
26 + help
27 + Support for the AR231x/531x ethernet controller
28 +
29 endif # NET_VENDOR_ATHEROS
30 --- /dev/null
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
32 @@ -0,0 +1 @@
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
34 --- /dev/null
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
36 @@ -0,0 +1,1246 @@
37 +/*
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
39 + *
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
43 + *
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
51 + *
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
55 + */
56 +
57 +#include <linux/module.h>
58 +#include <linux/version.h>
59 +#include <linux/types.h>
60 +#include <linux/errno.h>
61 +#include <linux/ioport.h>
62 +#include <linux/pci.h>
63 +#include <linux/netdevice.h>
64 +#include <linux/etherdevice.h>
65 +#include <linux/interrupt.h>
66 +#include <linux/hardirq.h>
67 +#include <linux/skbuff.h>
68 +#include <linux/init.h>
69 +#include <linux/delay.h>
70 +#include <linux/mm.h>
71 +#include <linux/highmem.h>
72 +#include <linux/sockios.h>
73 +#include <linux/pkt_sched.h>
74 +#include <linux/mii.h>
75 +#include <linux/phy.h>
76 +#include <linux/ethtool.h>
77 +#include <linux/ctype.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/io.h>
80 +#include <linux/uaccess.h>
81 +
82 +#include <net/sock.h>
83 +#include <net/ip.h>
84 +
85 +#define AR2313_MTU 1692
86 +#define AR2313_PRIOS 1
87 +#define AR2313_QUEUES (2*AR2313_PRIOS)
88 +#define AR2313_DESCR_ENTRIES 64
89 +
90 +
91 +#ifndef min
92 +#define min(a, b) (((a) < (b)) ? (a) : (b))
93 +#endif
94 +
95 +#ifndef SMP_CACHE_BYTES
96 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
97 +#endif
98 +
99 +#define AR2313_MBOX_SET_BIT 0x8
100 +
101 +#include "ar231x.h"
102 +
103 +/**
104 + * New interrupt handler strategy:
105 + *
106 + * An old interrupt handler worked using the traditional method of
107 + * replacing an skbuff with a new one when a packet arrives. However
108 + * the rx rings do not need to contain a static number of buffer
109 + * descriptors, thus it makes sense to move the memory allocation out
110 + * of the main interrupt handler and do it in a bottom half handler
111 + * and only allocate new buffers when the number of buffers in the
112 + * ring is below a certain threshold. In order to avoid starving the
113 + * NIC under heavy load it is however necessary to force allocation
114 + * when hitting a minimum threshold. The strategy for alloction is as
115 + * follows:
116 + *
117 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
118 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
119 + * the buffers in the interrupt handler
120 + * RX_RING_THRES - maximum number of buffers in the rx ring
121 + *
122 + * One advantagous side effect of this allocation approach is that the
123 + * entire rx processing can be done without holding any spin lock
124 + * since the rx rings and registers are totally independent of the tx
125 + * ring and its registers. This of course includes the kmalloc's of
126 + * new skb's. Thus start_xmit can run in parallel with rx processing
127 + * and the memory allocation on SMP systems.
128 + *
129 + * Note that running the skb reallocation in a bottom half opens up
130 + * another can of races which needs to be handled properly. In
131 + * particular it can happen that the interrupt handler tries to run
132 + * the reallocation while the bottom half is either running on another
133 + * CPU or was interrupted on the same CPU. To get around this the
134 + * driver uses bitops to prevent the reallocation routines from being
135 + * reentered.
136 + *
137 + * TX handling can also be done without holding any spin lock, wheee
138 + * this is fun! since tx_csm is only written to by the interrupt
139 + * handler.
140 + */
141 +
142 +/**
143 + * Threshold values for RX buffer allocation - the low water marks for
144 + * when to start refilling the rings are set to 75% of the ring
145 + * sizes. It seems to make sense to refill the rings entirely from the
146 + * intrrupt handler once it gets below the panic threshold, that way
147 + * we don't risk that the refilling is moved to another CPU when the
148 + * one running the interrupt handler just got the slab code hot in its
149 + * cache.
150 + */
151 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
152 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
153 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
154 +#define CRC_LEN 4
155 +#define RX_OFFSET 2
156 +
157 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
158 +#define VLAN_HDR 4
159 +#else
160 +#define VLAN_HDR 0
161 +#endif
162 +
163 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
164 + RX_OFFSET)
165 +
166 +#ifdef MODULE
167 +MODULE_LICENSE("GPL");
168 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
169 +MODULE_DESCRIPTION("AR231x Ethernet driver");
170 +#endif
171 +
172 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
173 +
174 +/* prototypes */
175 +static void ar231x_halt(struct net_device *dev);
176 +static void rx_tasklet_func(unsigned long data);
177 +static void rx_tasklet_cleanup(struct net_device *dev);
178 +static void ar231x_multicast_list(struct net_device *dev);
179 +static void ar231x_tx_timeout(struct net_device *dev);
180 +
181 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
182 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
183 + u16 value);
184 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
185 +static int ar231x_mdiobus_probe(struct net_device *dev);
186 +static void ar231x_adjust_link(struct net_device *dev);
187 +
188 +#ifndef ERR
189 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
190 +#endif
191 +
192 +#ifdef CONFIG_NET_POLL_CONTROLLER
193 +static void
194 +ar231x_netpoll(struct net_device *dev)
195 +{
196 + unsigned long flags;
197 +
198 + local_irq_save(flags);
199 + ar231x_interrupt(dev->irq, dev);
200 + local_irq_restore(flags);
201 +}
202 +#endif
203 +
204 +static const struct net_device_ops ar231x_ops = {
205 + .ndo_open = ar231x_open,
206 + .ndo_stop = ar231x_close,
207 + .ndo_start_xmit = ar231x_start_xmit,
208 + .ndo_set_rx_mode = ar231x_multicast_list,
209 + .ndo_do_ioctl = ar231x_ioctl,
210 + .ndo_change_mtu = eth_change_mtu,
211 + .ndo_validate_addr = eth_validate_addr,
212 + .ndo_set_mac_address = eth_mac_addr,
213 + .ndo_tx_timeout = ar231x_tx_timeout,
214 +#ifdef CONFIG_NET_POLL_CONTROLLER
215 + .ndo_poll_controller = ar231x_netpoll,
216 +#endif
217 +};
218 +
219 +int ar231x_probe(struct platform_device *pdev)
220 +{
221 + struct net_device *dev;
222 + struct ar231x_private *sp;
223 + struct resource *res;
224 + unsigned long ar_eth_base;
225 + char buf[64];
226 +
227 + dev = alloc_etherdev(sizeof(struct ar231x_private));
228 +
229 + if (dev == NULL) {
230 + printk(KERN_ERR
231 + "ar231x: Unable to allocate net_device structure!\n");
232 + return -ENOMEM;
233 + }
234 +
235 + platform_set_drvdata(pdev, dev);
236 +
237 + sp = netdev_priv(dev);
238 + sp->dev = dev;
239 + sp->cfg = pdev->dev.platform_data;
240 +
241 + sprintf(buf, "eth%d_membase", pdev->id);
242 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
243 + if (!res)
244 + return -ENODEV;
245 +
246 + sp->link = 0;
247 + ar_eth_base = res->start;
248 +
249 + sprintf(buf, "eth%d_irq", pdev->id);
250 + dev->irq = platform_get_irq_byname(pdev, buf);
251 +
252 + spin_lock_init(&sp->lock);
253 +
254 + dev->features |= NETIF_F_HIGHDMA;
255 + dev->netdev_ops = &ar231x_ops;
256 +
257 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
258 + tasklet_disable(&sp->rx_tasklet);
259 +
260 + sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
261 + if (!sp->eth_regs) {
262 + printk("Can't remap eth registers\n");
263 + return -ENXIO;
264 + }
265 +
266 + /**
267 + * When there's only one MAC, PHY regs are typically on ENET0,
268 + * even though the MAC might be on ENET1.
269 + * Needto remap PHY regs separately in this case
270 + */
271 + if (ar_eth_base == sp->cfg->phy_base)
272 + sp->phy_regs = sp->eth_regs;
273 + else {
274 + sp->phy_regs = ioremap_nocache(sp->cfg->phy_base,
275 + sizeof(*sp->phy_regs));
276 + if (!sp->phy_regs) {
277 + printk("Can't remap phy registers\n");
278 + return -ENXIO;
279 + }
280 + }
281 +
282 + sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
283 + sizeof(*sp->dma_regs));
284 + if (!sp->dma_regs) {
285 + printk("Can't remap DMA registers\n");
286 + return -ENXIO;
287 + }
288 + dev->base_addr = ar_eth_base + 0x1000;
289 +
290 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
291 + sp->name[sizeof(sp->name) - 1] = '\0';
292 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
293 +
294 + if (ar231x_init(dev)) {
295 + /* ar231x_init() calls ar231x_init_cleanup() on error */
296 + kfree(dev);
297 + return -ENODEV;
298 + }
299 +
300 + if (register_netdev(dev)) {
301 + printk("%s: register_netdev failed\n", __func__);
302 + return -1;
303 + }
304 +
305 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
306 + dev->irq);
307 +
308 + sp->mii_bus = mdiobus_alloc();
309 + if (sp->mii_bus == NULL)
310 + return -1;
311 +
312 + sp->mii_bus->priv = dev;
313 + sp->mii_bus->read = ar231x_mdiobus_read;
314 + sp->mii_bus->write = ar231x_mdiobus_write;
315 + sp->mii_bus->reset = ar231x_mdiobus_reset;
316 + sp->mii_bus->name = "ar231x_eth_mii";
317 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
318 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
319 + *sp->mii_bus->irq = PHY_POLL;
320 +
321 + mdiobus_register(sp->mii_bus);
322 +
323 + if (ar231x_mdiobus_probe(dev) != 0) {
324 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
325 + rx_tasklet_cleanup(dev);
326 + ar231x_init_cleanup(dev);
327 + unregister_netdev(dev);
328 + kfree(dev);
329 + return -ENODEV;
330 + }
331 +
332 + /* start link poll timer */
333 + ar231x_setup_timer(dev);
334 +
335 + return 0;
336 +}
337 +
338 +
339 +static void ar231x_multicast_list(struct net_device *dev)
340 +{
341 + struct ar231x_private *sp = netdev_priv(dev);
342 + unsigned int filter;
343 +
344 + filter = sp->eth_regs->mac_control;
345 +
346 + if (dev->flags & IFF_PROMISC)
347 + filter |= MAC_CONTROL_PR;
348 + else
349 + filter &= ~MAC_CONTROL_PR;
350 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
351 + filter |= MAC_CONTROL_PM;
352 + else
353 + filter &= ~MAC_CONTROL_PM;
354 +
355 + sp->eth_regs->mac_control = filter;
356 +}
357 +
358 +static void rx_tasklet_cleanup(struct net_device *dev)
359 +{
360 + struct ar231x_private *sp = netdev_priv(dev);
361 +
362 + /**
363 + * Tasklet may be scheduled. Need to get it removed from the list
364 + * since we're about to free the struct.
365 + */
366 +
367 + sp->unloading = 1;
368 + tasklet_enable(&sp->rx_tasklet);
369 + tasklet_kill(&sp->rx_tasklet);
370 +}
371 +
372 +static int ar231x_remove(struct platform_device *pdev)
373 +{
374 + struct net_device *dev = platform_get_drvdata(pdev);
375 + struct ar231x_private *sp = netdev_priv(dev);
376 + rx_tasklet_cleanup(dev);
377 + ar231x_init_cleanup(dev);
378 + unregister_netdev(dev);
379 + mdiobus_unregister(sp->mii_bus);
380 + mdiobus_free(sp->mii_bus);
381 + kfree(dev);
382 + return 0;
383 +}
384 +
385 +
386 +/**
387 + * Restart the AR2313 ethernet controller.
388 + */
389 +static int ar231x_restart(struct net_device *dev)
390 +{
391 + /* disable interrupts */
392 + disable_irq(dev->irq);
393 +
394 + /* stop mac */
395 + ar231x_halt(dev);
396 +
397 + /* initialize */
398 + ar231x_init(dev);
399 +
400 + /* enable interrupts */
401 + enable_irq(dev->irq);
402 +
403 + return 0;
404 +}
405 +
406 +static struct platform_driver ar231x_driver = {
407 + .driver.name = "ar231x-eth",
408 + .probe = ar231x_probe,
409 + .remove = ar231x_remove,
410 +};
411 +
412 +module_platform_driver(ar231x_driver);
413 +
414 +static void ar231x_free_descriptors(struct net_device *dev)
415 +{
416 + struct ar231x_private *sp = netdev_priv(dev);
417 + if (sp->rx_ring != NULL) {
418 + kfree((void *)KSEG0ADDR(sp->rx_ring));
419 + sp->rx_ring = NULL;
420 + sp->tx_ring = NULL;
421 + }
422 +}
423 +
424 +
425 +static int ar231x_allocate_descriptors(struct net_device *dev)
426 +{
427 + struct ar231x_private *sp = netdev_priv(dev);
428 + int size;
429 + int j;
430 + ar231x_descr_t *space;
431 +
432 + if (sp->rx_ring != NULL) {
433 + printk("%s: already done.\n", __func__);
434 + return 0;
435 + }
436 +
437 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
438 + space = kmalloc(size, GFP_KERNEL);
439 + if (space == NULL)
440 + return 1;
441 +
442 + /* invalidate caches */
443 + dma_cache_inv((unsigned int) space, size);
444 +
445 + /* now convert pointer to KSEG1 */
446 + space = (ar231x_descr_t *)KSEG1ADDR(space);
447 +
448 + memset((void *)space, 0, size);
449 +
450 + sp->rx_ring = space;
451 + space += AR2313_DESCR_ENTRIES;
452 +
453 + sp->tx_ring = space;
454 + space += AR2313_DESCR_ENTRIES;
455 +
456 + /* Initialize the transmit Descriptors */
457 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
458 + ar231x_descr_t *td = &sp->tx_ring[j];
459 + td->status = 0;
460 + td->devcs = DMA_TX1_CHAINED;
461 + td->addr = 0;
462 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
463 + }
464 +
465 + return 0;
466 +}
467 +
468 +
469 +/**
470 + * Generic cleanup handling data allocated during init. Used when the
471 + * module is unloaded or if an error occurs during initialization
472 + */
473 +static void ar231x_init_cleanup(struct net_device *dev)
474 +{
475 + struct ar231x_private *sp = netdev_priv(dev);
476 + struct sk_buff *skb;
477 + int j;
478 +
479 + ar231x_free_descriptors(dev);
480 +
481 + if (sp->eth_regs)
482 + iounmap((void *)sp->eth_regs);
483 + if (sp->dma_regs)
484 + iounmap((void *)sp->dma_regs);
485 +
486 + if (sp->rx_skb) {
487 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
488 + skb = sp->rx_skb[j];
489 + if (skb) {
490 + sp->rx_skb[j] = NULL;
491 + dev_kfree_skb(skb);
492 + }
493 + }
494 + kfree(sp->rx_skb);
495 + sp->rx_skb = NULL;
496 + }
497 +
498 + if (sp->tx_skb) {
499 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
500 + skb = sp->tx_skb[j];
501 + if (skb) {
502 + sp->tx_skb[j] = NULL;
503 + dev_kfree_skb(skb);
504 + }
505 + }
506 + kfree(sp->tx_skb);
507 + sp->tx_skb = NULL;
508 + }
509 +}
510 +
511 +static int ar231x_setup_timer(struct net_device *dev)
512 +{
513 + struct ar231x_private *sp = netdev_priv(dev);
514 +
515 + init_timer(&sp->link_timer);
516 +
517 + sp->link_timer.function = ar231x_link_timer_fn;
518 + sp->link_timer.data = (int) dev;
519 + sp->link_timer.expires = jiffies + HZ;
520 +
521 + add_timer(&sp->link_timer);
522 + return 0;
523 +}
524 +
525 +static void ar231x_link_timer_fn(unsigned long data)
526 +{
527 + struct net_device *dev = (struct net_device *)data;
528 + struct ar231x_private *sp = netdev_priv(dev);
529 +
530 + /**
531 + * See if the link status changed.
532 + * This was needed to make sure we set the PHY to the
533 + * autonegotiated value of half or full duplex.
534 + */
535 + ar231x_check_link(dev);
536 +
537 + /**
538 + * Loop faster when we don't have link.
539 + * This was needed to speed up the AP bootstrap time.
540 + */
541 + if (sp->link == 0)
542 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
543 + else
544 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
545 +}
546 +
547 +static void ar231x_check_link(struct net_device *dev)
548 +{
549 + struct ar231x_private *sp = netdev_priv(dev);
550 + u16 phy_data;
551 +
552 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
553 + if (sp->phy_data != phy_data) {
554 + if (phy_data & BMSR_LSTATUS) {
555 + /**
556 + * Link is present, ready link partner ability to
557 + * deterine duplexity.
558 + */
559 + int duplex = 0;
560 + u16 reg;
561 +
562 + sp->link = 1;
563 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
564 + MII_BMCR);
565 + if (reg & BMCR_ANENABLE) {
566 + /* auto neg enabled */
567 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
568 + MII_LPA);
569 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
570 + 1 : 0;
571 + } else {
572 + /* no auto neg, just read duplex config */
573 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
574 + }
575 +
576 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
577 + dev->name, (duplex) ? "full" : "half");
578 +
579 + if (duplex) {
580 + /* full duplex */
581 + sp->eth_regs->mac_control =
582 + (sp->eth_regs->mac_control |
583 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
584 + } else {
585 + /* half duplex */
586 + sp->eth_regs->mac_control =
587 + (sp->eth_regs->mac_control |
588 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
589 + }
590 + } else {
591 + /* no link */
592 + sp->link = 0;
593 + }
594 + sp->phy_data = phy_data;
595 + }
596 +}
597 +
598 +static int ar231x_reset_reg(struct net_device *dev)
599 +{
600 + struct ar231x_private *sp = netdev_priv(dev);
601 + unsigned int ethsal, ethsah;
602 + unsigned int flags;
603 +
604 + sp->cfg->reset_set(sp->cfg->reset_mac);
605 + mdelay(10);
606 + sp->cfg->reset_clear(sp->cfg->reset_mac);
607 + mdelay(10);
608 + sp->cfg->reset_set(sp->cfg->reset_phy);
609 + mdelay(10);
610 + sp->cfg->reset_clear(sp->cfg->reset_phy);
611 + mdelay(10);
612 +
613 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
614 + mdelay(10);
615 + sp->dma_regs->bus_mode =
616 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
617 +
618 + /* enable interrupts */
619 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
620 + DMA_STATUS_RI | DMA_STATUS_TI |
621 + DMA_STATUS_FBE;
622 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
623 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
624 + sp->dma_regs->control =
625 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
626 +
627 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
628 + sp->eth_regs->vlan_tag = (0x8100);
629 +
630 + /* Enable Ethernet Interface */
631 + flags = (MAC_CONTROL_TE | /* transmit enable */
632 + MAC_CONTROL_PM | /* pass mcast */
633 + MAC_CONTROL_F | /* full duplex */
634 + MAC_CONTROL_HBD); /* heart beat disabled */
635 +
636 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
637 + flags |= MAC_CONTROL_PR;
638 + }
639 + sp->eth_regs->mac_control = flags;
640 +
641 + /* Set all Ethernet station address registers to their initial values */
642 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
643 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
644 +
645 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
646 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
647 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
648 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
649 +
650 + sp->eth_regs->mac_addr[0] = ethsah;
651 + sp->eth_regs->mac_addr[1] = ethsal;
652 +
653 + mdelay(10);
654 +
655 + return 0;
656 +}
657 +
658 +
659 +static int ar231x_init(struct net_device *dev)
660 +{
661 + struct ar231x_private *sp = netdev_priv(dev);
662 + int ecode = 0;
663 +
664 + /* Allocate descriptors */
665 + if (ar231x_allocate_descriptors(dev)) {
666 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
667 + dev->name, __func__);
668 + ecode = -EAGAIN;
669 + goto init_error;
670 + }
671 +
672 + /* Get the memory for the skb rings */
673 + if (sp->rx_skb == NULL) {
674 + sp->rx_skb =
675 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
676 + GFP_KERNEL);
677 + if (!(sp->rx_skb)) {
678 + printk("%s: %s: rx_skb kmalloc failed\n",
679 + dev->name, __func__);
680 + ecode = -EAGAIN;
681 + goto init_error;
682 + }
683 + }
684 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
685 +
686 + if (sp->tx_skb == NULL) {
687 + sp->tx_skb =
688 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
689 + GFP_KERNEL);
690 + if (!(sp->tx_skb)) {
691 + printk("%s: %s: tx_skb kmalloc failed\n",
692 + dev->name, __func__);
693 + ecode = -EAGAIN;
694 + goto init_error;
695 + }
696 + }
697 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
698 +
699 + /**
700 + * Set tx_csm before we start receiving interrupts, otherwise
701 + * the interrupt handler might think it is supposed to process
702 + * tx ints before we are up and running, which may cause a null
703 + * pointer access in the int handler.
704 + */
705 + sp->rx_skbprd = 0;
706 + sp->cur_rx = 0;
707 + sp->tx_prd = 0;
708 + sp->tx_csm = 0;
709 +
710 + /* Zero the stats before starting the interface */
711 + memset(&dev->stats, 0, sizeof(dev->stats));
712 +
713 + /**
714 + * We load the ring here as there seem to be no way to tell the
715 + * firmware to wipe the ring without re-initializing it.
716 + */
717 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
718 +
719 + /* Init hardware */
720 + ar231x_reset_reg(dev);
721 +
722 + /* Get the IRQ */
723 + ecode =
724 + request_irq(dev->irq, &ar231x_interrupt,
725 + IRQF_DISABLED,
726 + dev->name, dev);
727 + if (ecode) {
728 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
729 + dev->name, __func__, dev->irq);
730 + goto init_error;
731 + }
732 +
733 +
734 + tasklet_enable(&sp->rx_tasklet);
735 +
736 + return 0;
737 +
738 +init_error:
739 + ar231x_init_cleanup(dev);
740 + return ecode;
741 +}
742 +
743 +/**
744 + * Load the rx ring.
745 + *
746 + * Loading rings is safe without holding the spin lock since this is
747 + * done only before the device is enabled, thus no interrupts are
748 + * generated and by the interrupt handler/tasklet handler.
749 + */
750 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
751 +{
752 + struct ar231x_private *sp = netdev_priv(dev);
753 + short i, idx;
754 +
755 + idx = sp->rx_skbprd;
756 +
757 + for (i = 0; i < nr_bufs; i++) {
758 + struct sk_buff *skb;
759 + ar231x_descr_t *rd;
760 +
761 + if (sp->rx_skb[idx])
762 + break;
763 +
764 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
765 + if (!skb) {
766 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
767 + __func__);
768 + break;
769 + }
770 +
771 + /* Make sure IP header starts on a fresh cache line */
772 + skb->dev = dev;
773 + sp->rx_skb[idx] = skb;
774 +
775 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
776 +
777 + /* initialize dma descriptor */
778 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
779 + DMA_RX1_CHAINED);
780 + rd->addr = virt_to_phys(skb->data);
781 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
782 + rd->status = DMA_RX_OWN;
783 +
784 + idx = DSC_NEXT(idx);
785 + }
786 +
787 + if (i)
788 + sp->rx_skbprd = idx;
789 +
790 + return;
791 +}
792 +
793 +#define AR2313_MAX_PKTS_PER_CALL 64
794 +
795 +static int ar231x_rx_int(struct net_device *dev)
796 +{
797 + struct ar231x_private *sp = netdev_priv(dev);
798 + struct sk_buff *skb, *skb_new;
799 + ar231x_descr_t *rxdesc;
800 + unsigned int status;
801 + u32 idx;
802 + int pkts = 0;
803 + int rval;
804 +
805 + idx = sp->cur_rx;
806 +
807 + /* process at most the entire ring and then wait for another int */
808 + while (1) {
809 + rxdesc = &sp->rx_ring[idx];
810 + status = rxdesc->status;
811 +
812 + if (status & DMA_RX_OWN) {
813 + /* SiByte owns descriptor or descr not yet filled in */
814 + rval = 0;
815 + break;
816 + }
817 +
818 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
819 + rval = 1;
820 + break;
821 + }
822 +
823 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
824 + dev->stats.rx_errors++;
825 + dev->stats.rx_dropped++;
826 +
827 + /* add statistics counters */
828 + if (status & DMA_RX_ERR_CRC)
829 + dev->stats.rx_crc_errors++;
830 + if (status & DMA_RX_ERR_COL)
831 + dev->stats.rx_over_errors++;
832 + if (status & DMA_RX_ERR_LENGTH)
833 + dev->stats.rx_length_errors++;
834 + if (status & DMA_RX_ERR_RUNT)
835 + dev->stats.rx_over_errors++;
836 + if (status & DMA_RX_ERR_DESC)
837 + dev->stats.rx_over_errors++;
838 +
839 + } else {
840 + /* alloc new buffer. */
841 + skb_new = netdev_alloc_skb_ip_align(dev,
842 + AR2313_BUFSIZE);
843 + if (skb_new != NULL) {
844 + skb = sp->rx_skb[idx];
845 + /* set skb */
846 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
847 + 0x3fff) - CRC_LEN);
848 +
849 + dev->stats.rx_bytes += skb->len;
850 + skb->protocol = eth_type_trans(skb, dev);
851 + /* pass the packet to upper layers */
852 + netif_rx(skb);
853 +
854 + skb_new->dev = dev;
855 + /* reset descriptor's curr_addr */
856 + rxdesc->addr = virt_to_phys(skb_new->data);
857 +
858 + dev->stats.rx_packets++;
859 + sp->rx_skb[idx] = skb_new;
860 + } else {
861 + dev->stats.rx_dropped++;
862 + }
863 + }
864 +
865 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
866 + DMA_RX1_CHAINED);
867 + rxdesc->status = DMA_RX_OWN;
868 +
869 + idx = DSC_NEXT(idx);
870 + }
871 +
872 + sp->cur_rx = idx;
873 +
874 + return rval;
875 +}
876 +
877 +
878 +static void ar231x_tx_int(struct net_device *dev)
879 +{
880 + struct ar231x_private *sp = netdev_priv(dev);
881 + u32 idx;
882 + struct sk_buff *skb;
883 + ar231x_descr_t *txdesc;
884 + unsigned int status = 0;
885 +
886 + idx = sp->tx_csm;
887 +
888 + while (idx != sp->tx_prd) {
889 + txdesc = &sp->tx_ring[idx];
890 + status = txdesc->status;
891 +
892 + if (status & DMA_TX_OWN) {
893 + /* ar231x dma still owns descr */
894 + break;
895 + }
896 + /* done with this descriptor */
897 + dma_unmap_single(NULL, txdesc->addr,
898 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
899 + DMA_TO_DEVICE);
900 + txdesc->status = 0;
901 +
902 + if (status & DMA_TX_ERROR) {
903 + dev->stats.tx_errors++;
904 + dev->stats.tx_dropped++;
905 + if (status & DMA_TX_ERR_UNDER)
906 + dev->stats.tx_fifo_errors++;
907 + if (status & DMA_TX_ERR_HB)
908 + dev->stats.tx_heartbeat_errors++;
909 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
910 + dev->stats.tx_carrier_errors++;
911 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
912 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
913 + dev->stats.tx_aborted_errors++;
914 + } else {
915 + /* transmit OK */
916 + dev->stats.tx_packets++;
917 + }
918 +
919 + skb = sp->tx_skb[idx];
920 + sp->tx_skb[idx] = NULL;
921 + idx = DSC_NEXT(idx);
922 + dev->stats.tx_bytes += skb->len;
923 + dev_kfree_skb_irq(skb);
924 + }
925 +
926 + sp->tx_csm = idx;
927 +
928 + return;
929 +}
930 +
931 +
932 +static void rx_tasklet_func(unsigned long data)
933 +{
934 + struct net_device *dev = (struct net_device *)data;
935 + struct ar231x_private *sp = netdev_priv(dev);
936 +
937 + if (sp->unloading)
938 + return;
939 +
940 + if (ar231x_rx_int(dev)) {
941 + tasklet_hi_schedule(&sp->rx_tasklet);
942 + } else {
943 + unsigned long flags;
944 + spin_lock_irqsave(&sp->lock, flags);
945 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
946 + spin_unlock_irqrestore(&sp->lock, flags);
947 + }
948 +}
949 +
950 +static void rx_schedule(struct net_device *dev)
951 +{
952 + struct ar231x_private *sp = netdev_priv(dev);
953 +
954 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
955 +
956 + tasklet_hi_schedule(&sp->rx_tasklet);
957 +}
958 +
959 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
960 +{
961 + struct net_device *dev = (struct net_device *)dev_id;
962 + struct ar231x_private *sp = netdev_priv(dev);
963 + unsigned int status, enabled;
964 +
965 + /* clear interrupt */
966 + /* Don't clear RI bit if currently disabled */
967 + status = sp->dma_regs->status;
968 + enabled = sp->dma_regs->intr_ena;
969 + sp->dma_regs->status = status & enabled;
970 +
971 + if (status & DMA_STATUS_NIS) {
972 + /* normal status */
973 + /**
974 + * Don't schedule rx processing if interrupt
975 + * is already disabled.
976 + */
977 + if (status & enabled & DMA_STATUS_RI) {
978 + /* receive interrupt */
979 + rx_schedule(dev);
980 + }
981 + if (status & DMA_STATUS_TI) {
982 + /* transmit interrupt */
983 + ar231x_tx_int(dev);
984 + }
985 + }
986 +
987 + /* abnormal status */
988 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
989 + ar231x_restart(dev);
990 +
991 + return IRQ_HANDLED;
992 +}
993 +
994 +
995 +static int ar231x_open(struct net_device *dev)
996 +{
997 + struct ar231x_private *sp = netdev_priv(dev);
998 + unsigned int ethsal, ethsah;
999 +
1000 + /* reset the hardware, in case the MAC address changed */
1001 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1002 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
1003 +
1004 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1005 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1006 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1007 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
1008 +
1009 + sp->eth_regs->mac_addr[0] = ethsah;
1010 + sp->eth_regs->mac_addr[1] = ethsal;
1011 +
1012 + mdelay(10);
1013 +
1014 + dev->mtu = 1500;
1015 + netif_start_queue(dev);
1016 +
1017 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1018 +
1019 + return 0;
1020 +}
1021 +
1022 +static void ar231x_tx_timeout(struct net_device *dev)
1023 +{
1024 + struct ar231x_private *sp = netdev_priv(dev);
1025 + unsigned long flags;
1026 +
1027 + spin_lock_irqsave(&sp->lock, flags);
1028 + ar231x_restart(dev);
1029 + spin_unlock_irqrestore(&sp->lock, flags);
1030 +}
1031 +
1032 +static void ar231x_halt(struct net_device *dev)
1033 +{
1034 + struct ar231x_private *sp = netdev_priv(dev);
1035 + int j;
1036 +
1037 + tasklet_disable(&sp->rx_tasklet);
1038 +
1039 + /* kill the MAC */
1040 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1041 + MAC_CONTROL_TE); /* disable Transmits */
1042 + /* stop dma */
1043 + sp->dma_regs->control = 0;
1044 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1045 +
1046 + /* place phy and MAC in reset */
1047 + sp->cfg->reset_set(sp->cfg->reset_mac);
1048 + sp->cfg->reset_set(sp->cfg->reset_phy);
1049 +
1050 + /* free buffers on tx ring */
1051 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1052 + struct sk_buff *skb;
1053 + ar231x_descr_t *txdesc;
1054 +
1055 + txdesc = &sp->tx_ring[j];
1056 + txdesc->descr = 0;
1057 +
1058 + skb = sp->tx_skb[j];
1059 + if (skb) {
1060 + dev_kfree_skb(skb);
1061 + sp->tx_skb[j] = NULL;
1062 + }
1063 + }
1064 +}
1065 +
1066 +/**
1067 + * close should do nothing. Here's why. It's called when
1068 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1069 + * the irq is gone forever ! When bond0 is made 'up' again,
1070 + * the ar231x_open () does not call request_irq (). Worse,
1071 + * the call to ar231x_halt() generates a WDOG reset due to
1072 + * the write to reset register and the box reboots.
1073 + * Commenting this out is good since it allows the
1074 + * system to resume when bond0 is made up again.
1075 + */
1076 +static int ar231x_close(struct net_device *dev)
1077 +{
1078 +#if 0
1079 + /* Disable interrupts */
1080 + disable_irq(dev->irq);
1081 +
1082 + /**
1083 + * Without (or before) releasing irq and stopping hardware, this
1084 + * is an absolute non-sense, by the way. It will be reset instantly
1085 + * by the first irq.
1086 + */
1087 + netif_stop_queue(dev);
1088 +
1089 + /* stop the MAC and DMA engines */
1090 + ar231x_halt(dev);
1091 +
1092 + /* release the interrupt */
1093 + free_irq(dev->irq, dev);
1094 +
1095 +#endif
1096 + return 0;
1097 +}
1098 +
1099 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1100 +{
1101 + struct ar231x_private *sp = netdev_priv(dev);
1102 + ar231x_descr_t *td;
1103 + u32 idx;
1104 +
1105 + idx = sp->tx_prd;
1106 + td = &sp->tx_ring[idx];
1107 +
1108 + if (td->status & DMA_TX_OWN) {
1109 + /* free skbuf and lie to the caller that we sent it out */
1110 + dev->stats.tx_dropped++;
1111 + dev_kfree_skb(skb);
1112 +
1113 + /* restart transmitter in case locked */
1114 + sp->dma_regs->xmt_poll = 0;
1115 + return 0;
1116 + }
1117 +
1118 + /* Setup the transmit descriptor. */
1119 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1120 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1121 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1122 + td->status = DMA_TX_OWN;
1123 +
1124 + /* kick transmitter last */
1125 + sp->dma_regs->xmt_poll = 0;
1126 +
1127 + sp->tx_skb[idx] = skb;
1128 + idx = DSC_NEXT(idx);
1129 + sp->tx_prd = idx;
1130 +
1131 + return 0;
1132 +}
1133 +
1134 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1135 +{
1136 + struct ar231x_private *sp = netdev_priv(dev);
1137 + int ret;
1138 +
1139 + switch (cmd) {
1140 + case SIOCETHTOOL:
1141 + spin_lock_irq(&sp->lock);
1142 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *)ifr->ifr_data);
1143 + spin_unlock_irq(&sp->lock);
1144 + return ret;
1145 +
1146 + case SIOCSIFHWADDR:
1147 + if (copy_from_user
1148 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1149 + return -EFAULT;
1150 + return 0;
1151 +
1152 + case SIOCGIFHWADDR:
1153 + if (copy_to_user
1154 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1155 + return -EFAULT;
1156 + return 0;
1157 +
1158 + case SIOCGMIIPHY:
1159 + case SIOCGMIIREG:
1160 + case SIOCSMIIREG:
1161 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1162 +
1163 + default:
1164 + break;
1165 + }
1166 +
1167 + return -EOPNOTSUPP;
1168 +}
1169 +
1170 +static void ar231x_adjust_link(struct net_device *dev)
1171 +{
1172 + struct ar231x_private *sp = netdev_priv(dev);
1173 + unsigned int mc;
1174 +
1175 + if (!sp->phy_dev->link)
1176 + return;
1177 +
1178 + if (sp->phy_dev->duplex != sp->oldduplex) {
1179 + mc = readl(&sp->eth_regs->mac_control);
1180 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1181 + if (sp->phy_dev->duplex)
1182 + mc |= MAC_CONTROL_F;
1183 + else
1184 + mc |= MAC_CONTROL_DRO;
1185 + writel(mc, &sp->eth_regs->mac_control);
1186 + sp->oldduplex = sp->phy_dev->duplex;
1187 + }
1188 +}
1189 +
1190 +#define MII_ADDR(phy, reg) \
1191 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1192 +
1193 +static int
1194 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1195 +{
1196 + struct net_device *const dev = bus->priv;
1197 + struct ar231x_private *sp = netdev_priv(dev);
1198 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1199 +
1200 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1201 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1202 + ;
1203 + return ethernet->mii_data >> MII_DATA_SHIFT;
1204 +}
1205 +
1206 +static int
1207 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1208 +{
1209 + struct net_device *const dev = bus->priv;
1210 + struct ar231x_private *sp = netdev_priv(dev);
1211 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1212 +
1213 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1214 + ;
1215 + ethernet->mii_data = value << MII_DATA_SHIFT;
1216 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1217 +
1218 + return 0;
1219 +}
1220 +
1221 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1222 +{
1223 + struct net_device *const dev = bus->priv;
1224 +
1225 + ar231x_reset_reg(dev);
1226 +
1227 + return 0;
1228 +}
1229 +
1230 +static int ar231x_mdiobus_probe(struct net_device *dev)
1231 +{
1232 + struct ar231x_private *const sp = netdev_priv(dev);
1233 + struct phy_device *phydev = NULL;
1234 + int phy_addr;
1235 +
1236 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1237 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1238 + if (sp->mii_bus->phy_map[phy_addr]) {
1239 + phydev = sp->mii_bus->phy_map[phy_addr];
1240 + sp->phy = phy_addr;
1241 + break; /* break out with first one found */
1242 + }
1243 +
1244 + if (!phydev) {
1245 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1246 + return -1;
1247 + }
1248 +
1249 + /* now we are supposed to have a proper phydev, to attach to... */
1250 + BUG_ON(!phydev);
1251 + BUG_ON(phydev->attached_dev);
1252 +
1253 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
1254 + PHY_INTERFACE_MODE_MII);
1255 +
1256 + if (IS_ERR(phydev)) {
1257 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1258 + return PTR_ERR(phydev);
1259 + }
1260 +
1261 + /* mask with MAC supported features */
1262 + phydev->supported &= (SUPPORTED_10baseT_Half
1263 + | SUPPORTED_10baseT_Full
1264 + | SUPPORTED_100baseT_Half
1265 + | SUPPORTED_100baseT_Full
1266 + | SUPPORTED_Autoneg
1267 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1268 + | SUPPORTED_MII
1269 + | SUPPORTED_TP);
1270 +
1271 + phydev->advertising = phydev->supported;
1272 +
1273 + sp->oldduplex = -1;
1274 + sp->phy_dev = phydev;
1275 +
1276 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1277 + "(mii_bus:phy_addr=%s)\n",
1278 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1279 +
1280 + return 0;
1281 +}
1282 +
1283 --- /dev/null
1284 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1285 @@ -0,0 +1,287 @@
1286 +/*
1287 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1288 + *
1289 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1290 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1291 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1292 + *
1293 + * Thanks to Atheros for providing hardware and documentation
1294 + * enabling me to write this driver.
1295 + *
1296 + * This program is free software; you can redistribute it and/or modify
1297 + * it under the terms of the GNU General Public License as published by
1298 + * the Free Software Foundation; either version 2 of the License, or
1299 + * (at your option) any later version.
1300 + */
1301 +
1302 +#ifndef _AR2313_H_
1303 +#define _AR2313_H_
1304 +
1305 +#include <linux/interrupt.h>
1306 +#include <generated/autoconf.h>
1307 +#include <linux/bitops.h>
1308 +#include <ar231x_platform.h>
1309 +
1310 +/* probe link timer - 5 secs */
1311 +#define LINK_TIMER (5*HZ)
1312 +
1313 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1314 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1315 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1316 +
1317 +#define AR2313_TX_TIMEOUT (HZ/4)
1318 +
1319 +/* Rings */
1320 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1321 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1322 +
1323 +#define AR2313_MBGET 2
1324 +#define AR2313_MBSET 3
1325 +#define AR2313_PCI_RECONFIG 4
1326 +#define AR2313_PCI_DUMP 5
1327 +#define AR2313_TEST_PANIC 6
1328 +#define AR2313_TEST_NULLPTR 7
1329 +#define AR2313_READ_DATA 8
1330 +#define AR2313_WRITE_DATA 9
1331 +#define AR2313_GET_VERSION 10
1332 +#define AR2313_TEST_HANG 11
1333 +#define AR2313_SYNC 12
1334 +
1335 +#define DMA_RX_ERR_CRC BIT(1)
1336 +#define DMA_RX_ERR_DRIB BIT(2)
1337 +#define DMA_RX_ERR_MII BIT(3)
1338 +#define DMA_RX_EV2 BIT(5)
1339 +#define DMA_RX_ERR_COL BIT(6)
1340 +#define DMA_RX_LONG BIT(7)
1341 +#define DMA_RX_LS BIT(8) /* last descriptor */
1342 +#define DMA_RX_FS BIT(9) /* first descriptor */
1343 +#define DMA_RX_MF BIT(10) /* multicast frame */
1344 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1345 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1346 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1347 +#define DMA_RX_ERROR BIT(15) /* error summary */
1348 +#define DMA_RX_LEN_MASK 0x3fff0000
1349 +#define DMA_RX_LEN_SHIFT 16
1350 +#define DMA_RX_FILT BIT(30)
1351 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1352 +
1353 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1354 +#define DMA_RX1_BSIZE_SHIFT 0
1355 +#define DMA_RX1_CHAINED BIT(24)
1356 +#define DMA_RX1_RER BIT(25)
1357 +
1358 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1359 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1360 +#define DMA_TX_COL_MASK 0x78
1361 +#define DMA_TX_COL_SHIFT 3
1362 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1363 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1364 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1365 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1366 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1367 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1368 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1369 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1370 +
1371 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1372 +#define DMA_TX1_BSIZE_SHIFT 0
1373 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1374 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1375 +#define DMA_TX1_FS BIT(29) /* first segment */
1376 +#define DMA_TX1_LS BIT(30) /* last segment */
1377 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1378 +
1379 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1380 +
1381 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1382 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1383 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1384 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1385 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1386 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1387 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1388 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1389 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1390 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1391 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1392 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1393 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1394 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1395 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1396 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1397 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1398 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1399 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1400 +
1401 +#define MII_ADDR_BUSY BIT(0)
1402 +#define MII_ADDR_WRITE BIT(1)
1403 +#define MII_ADDR_REG_SHIFT 6
1404 +#define MII_ADDR_PHY_SHIFT 11
1405 +#define MII_DATA_SHIFT 0
1406 +
1407 +#define FLOW_CONTROL_FCE BIT(1)
1408 +
1409 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1410 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1411 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1412 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1413 +
1414 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1415 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1416 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1417 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1418 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1419 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1420 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1421 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1422 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1423 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1424 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1425 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1426 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1427 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1428 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1429 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1430 +
1431 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1432 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1433 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1434 +
1435 +
1436 +typedef struct {
1437 + volatile unsigned int status; /* OWN, Device control and status. */
1438 + volatile unsigned int devcs; /* pkt Control bits + Length */
1439 + volatile unsigned int addr; /* Current Address. */
1440 + volatile unsigned int descr; /* Next descriptor in chain. */
1441 +} ar231x_descr_t;
1442 +
1443 +
1444 +
1445 +/**
1446 + * New Combo structure for Both Eth0 AND eth1
1447 + */
1448 +typedef struct {
1449 + volatile unsigned int mac_control; /* 0x00 */
1450 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1451 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1452 + volatile unsigned int mii_addr; /* 0x14 */
1453 + volatile unsigned int mii_data; /* 0x18 */
1454 + volatile unsigned int flow_control; /* 0x1c */
1455 + volatile unsigned int vlan_tag; /* 0x20 */
1456 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1457 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1458 +
1459 +} ETHERNET_STRUCT;
1460 +
1461 +/********************************************************************
1462 + * Interrupt controller
1463 + ********************************************************************/
1464 +
1465 +typedef struct {
1466 + volatile unsigned int wdog_control; /* 0x08 */
1467 + volatile unsigned int wdog_timer; /* 0x0c */
1468 + volatile unsigned int misc_status; /* 0x10 */
1469 + volatile unsigned int misc_mask; /* 0x14 */
1470 + volatile unsigned int global_status; /* 0x18 */
1471 + volatile unsigned int reserved; /* 0x1c */
1472 + volatile unsigned int reset_control; /* 0x20 */
1473 +} INTERRUPT;
1474 +
1475 +/********************************************************************
1476 + * DMA controller
1477 + ********************************************************************/
1478 +typedef struct {
1479 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1480 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1481 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1482 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1483 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1484 + volatile unsigned int status; /* 0x14 (CSR5) */
1485 + volatile unsigned int control; /* 0x18 (CSR6) */
1486 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1487 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1488 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1489 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1490 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1491 +} DMA;
1492 +
1493 +/**
1494 + * Struct private for the Sibyte.
1495 + *
1496 + * Elements are grouped so variables used by the tx handling goes
1497 + * together, and will go into the same cache lines etc. in order to
1498 + * avoid cache line contention between the rx and tx handling on SMP.
1499 + *
1500 + * Frequently accessed variables are put at the beginning of the
1501 + * struct to help the compiler generate better/shorter code.
1502 + */
1503 +struct ar231x_private {
1504 + struct net_device *dev;
1505 + int version;
1506 + u32 mb[2];
1507 +
1508 + volatile ETHERNET_STRUCT *phy_regs;
1509 + volatile ETHERNET_STRUCT *eth_regs;
1510 + volatile DMA *dma_regs;
1511 + struct ar231x_eth *cfg;
1512 +
1513 + spinlock_t lock; /* Serialise access to device */
1514 +
1515 + /* RX and TX descriptors, must be adjacent */
1516 + ar231x_descr_t *rx_ring;
1517 + ar231x_descr_t *tx_ring;
1518 +
1519 +
1520 + struct sk_buff **rx_skb;
1521 + struct sk_buff **tx_skb;
1522 +
1523 + /* RX elements */
1524 + u32 rx_skbprd;
1525 + u32 cur_rx;
1526 +
1527 + /* TX elements */
1528 + u32 tx_prd;
1529 + u32 tx_csm;
1530 +
1531 + /* Misc elements */
1532 + char name[48];
1533 + struct {
1534 + u32 address;
1535 + u32 length;
1536 + char *mapping;
1537 + } desc;
1538 +
1539 +
1540 + struct timer_list link_timer;
1541 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1542 + unsigned short mac;
1543 + unsigned short link; /* 0 - link down, 1 - link up */
1544 + u16 phy_data;
1545 +
1546 + struct tasklet_struct rx_tasklet;
1547 + int unloading;
1548 +
1549 + struct phy_device *phy_dev;
1550 + struct mii_bus *mii_bus;
1551 + int oldduplex;
1552 +};
1553 +
1554 +
1555 +/* Prototypes */
1556 +static int ar231x_init(struct net_device *dev);
1557 +#ifdef TX_TIMEOUT
1558 +static void ar231x_tx_timeout(struct net_device *dev);
1559 +#endif
1560 +static int ar231x_restart(struct net_device *dev);
1561 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1562 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1563 +static int ar231x_open(struct net_device *dev);
1564 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1565 +static int ar231x_close(struct net_device *dev);
1566 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1567 + int cmd);
1568 +static void ar231x_init_cleanup(struct net_device *dev);
1569 +static int ar231x_setup_timer(struct net_device *dev);
1570 +static void ar231x_link_timer_fn(unsigned long data);
1571 +static void ar231x_check_link(struct net_device *dev);
1572 +#endif /* _AR2313_H_ */
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