target/linux/atheros/patches-3.14/105-ar2315_pci.patch

   1 --- a/arch/mips/ar231x/Makefile
   2 +++ b/arch/mips/ar231x/Makefile
   3 @@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
   4
   5  obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
   6  obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
   7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
   8 --- /dev/null
   9 +++ b/arch/mips/ar231x/pci.c
  10 @@ -0,0 +1,336 @@
  11 +/*
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License
  14 + * as published by the Free Software Foundation; either version 2
  15 + * of the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
  24 + */
  25 +
  26 +/**
  27 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  28 + * and interrupt. PCI interface supports MMIO access method, but does not
  29 + * seem to support I/O ports.
  30 + *
  31 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  32 + * a memory read/write command on the PCI bus. 30 LSBs of address on
  33 + * the bus are taken from memory read/write request and 2 MSBs are
  34 + * determined by PCI unit configuration.
  35 + *
  36 + * To work with the configuration space instead of memory is necessary set
  37 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  38 + *
  39 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  40 + * controller BARs are programmend as if an external device is programmed.
  41 + * Which means that during configuration, IDSEL pin of the chip should be
  42 + * asserted.
  43 + *
  44 + * We know (and support) only one board that uses the PCI interface -
  45 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  46 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  47 + * and IDSEL pin of AR125 is connected to AD[16] line.
  48 + */
  49 +
  50 +#include <linux/types.h>
  51 +#include <linux/pci.h>
  52 +#include <linux/kernel.h>
  53 +#include <linux/init.h>
  54 +#include <linux/mm.h>
  55 +#include <linux/delay.h>
  56 +#include <linux/irq.h>
  57 +#include <linux/io.h>
  58 +#include <asm/paccess.h>
  59 +#include <ar231x_platform.h>
  60 +#include <ar231x.h>
  61 +#include <ar2315_regs.h>
  62 +#include "devices.h"
  63 +
  64 +#define AR2315_MEM_BASE    0x80800000UL
  65 +#define AR2315_MEM_SIZE    0x00ffffffUL
  66 +#define AR2315_IO_SIZE     0x00007fffUL
  67 +
  68 +#define AR2315_PCI_HOST_SLOT   3
  69 +#define AR2315_PCI_HOST_DEVID  ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
  70 +
  71 +static unsigned long configspace;
  72 +
  73 +static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
  74 +                                bool write)
  75 +{
  76 +       int func = PCI_FUNC(devfn);
  77 +       int dev = PCI_SLOT(devfn);
  78 +       u32 value = 0;
  79 +       int err = 0;
  80 +       u32 addr;
  81 +
  82 +       /* Select Configuration access */
  83 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
  84 +       mb();
  85 +
  86 +       addr = (u32)configspace + (1 << (13 + dev)) + (func << 8) + where;
  87 +       if (size == 1)
  88 +               addr ^= 0x3;
  89 +       else if (size == 2)
  90 +               addr ^= 0x2;
  91 +
  92 +       if (write) {
  93 +               value = *ptr;
  94 +               if (size == 1)
  95 +                       err = put_dbe(value, (u8 *)addr);
  96 +               else if (size == 2)
  97 +                       err = put_dbe(value, (u16 *)addr);
  98 +               else if (size == 4)
  99 +                       err = put_dbe(value, (u32 *)addr);
 100 +       } else {
 101 +               if (size == 1)
 102 +                       err = get_dbe(value, (u8 *)addr);
 103 +               else if (size == 2)
 104 +                       err = get_dbe(value, (u16 *)addr);
 105 +               else if (size == 4)
 106 +                       err = get_dbe(value, (u32 *)addr);
 107 +               if (err)
 108 +                       *ptr = 0xffffffff;
 109 +               else
 110 +                       *ptr = value;
 111 +       }
 112 +
 113 +       /* Select Memory access */
 114 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
 115 +
 116 +       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 117 +}
 118 +
 119 +static inline int ar2315_pci_local_cfg_rd(unsigned devfn, int where, u32 *val)
 120 +{
 121 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), val, false);
 122 +}
 123 +
 124 +static inline int ar2315_pci_local_cfg_wr(unsigned devfn, int where, u32 val)
 125 +{
 126 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), &val, true);
 127 +}
 128 +
 129 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
 130 +                              int where, int size, u32 *value)
 131 +{
 132 +       if ((PCI_SLOT(devfn) != 0) || (PCI_FUNC(devfn) > 2))
 133 +               return PCIBIOS_DEVICE_NOT_FOUND;
 134 +
 135 +       return ar2315_pci_cfg_access(devfn, where, size, value, 0);
 136 +}
 137 +
 138 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
 139 +                               int where, int size, u32 value)
 140 +{
 141 +       if ((PCI_SLOT(devfn) != 0) || (PCI_FUNC(devfn) > 2))
 142 +               return PCIBIOS_DEVICE_NOT_FOUND;
 143 +
 144 +       return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
 145 +}
 146 +
 147 +static struct pci_ops ar2315_pci_ops = {
 148 +       .read   = ar2315_pci_cfg_read,
 149 +       .write  = ar2315_pci_cfg_write,
 150 +};
 151 +
 152 +static struct resource ar2315_mem_resource = {
 153 +       .name   = "ar2315-pci-mem",
 154 +       .start  = AR2315_MEM_BASE,
 155 +       .end    = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE - 1 +
 156 +                 0x4000000,
 157 +       .flags  = IORESOURCE_MEM,
 158 +};
 159 +
 160 +static struct resource ar2315_io_resource = {
 161 +       .name   = "ar2315-pci-io",
 162 +       .start  = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE,
 163 +       .end    = AR2315_MEM_BASE + AR2315_MEM_SIZE - 1,
 164 +       .flags  = IORESOURCE_IO,
 165 +};
 166 +
 167 +static struct pci_controller ar2315_pci_controller = {
 168 +       .pci_ops        = &ar2315_pci_ops,
 169 +       .mem_resource   = &ar2315_mem_resource,
 170 +       .io_resource    = &ar2315_io_resource,
 171 +       .mem_offset     = 0x00000000UL,
 172 +       .io_offset      = 0x00000000UL,
 173 +};
 174 +
 175 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 176 +{
 177 +       return AR2315_PCI_IRQ_EXT;
 178 +}
 179 +
 180 +int pcibios_plat_dev_init(struct pci_dev *dev)
 181 +{
 182 +       return 0;
 183 +}
 184 +
 185 +static int ar2315_pci_host_setup(void)
 186 +{
 187 +       unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
 188 +       int res;
 189 +       u32 id;
 190 +
 191 +       res = ar2315_pci_local_cfg_rd(devfn, PCI_VENDOR_ID, &id);
 192 +       if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
 193 +               return -ENODEV;
 194 +
 195 +       /* Program MBARs */
 196 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
 197 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
 198 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
 199 +
 200 +       /* Run */
 201 +       ar2315_pci_local_cfg_wr(devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
 202 +                               PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 203 +                               PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 204 +                               PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 205 +
 206 +       return 0;
 207 +}
 208 +
 209 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
 210 +{
 211 +       u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
 212 +                     ar231x_read_reg(AR2315_PCI_IMR);
 213 +
 214 +       if (pending & AR2315_PCI_INT_EXT)
 215 +               generic_handle_irq(AR2315_PCI_IRQ_EXT);
 216 +       else if (pending & AR2315_PCI_INT_ABORT)
 217 +               generic_handle_irq(AR2315_PCI_IRQ_ABORT);
 218 +       else
 219 +               spurious_interrupt();
 220 +}
 221 +
 222 +static void ar2315_pci_irq_mask(struct irq_data *d)
 223 +{
 224 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 225 +
 226 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 227 +}
 228 +
 229 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
 230 +{
 231 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 232 +
 233 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 234 +       ar231x_write_reg(AR2315_PCI_ISR, m);
 235 +}
 236 +
 237 +static void ar2315_pci_irq_unmask(struct irq_data *d)
 238 +{
 239 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 240 +
 241 +       ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
 242 +}
 243 +
 244 +static struct irq_chip ar2315_pci_irq_chip = {
 245 +       .name = "AR2315-PCI",
 246 +       .irq_mask = ar2315_pci_irq_mask,
 247 +       .irq_mask_ack = ar2315_pci_irq_mask_ack,
 248 +       .irq_unmask = ar2315_pci_irq_unmask,
 249 +};
 250 +
 251 +static void ar2315_pci_irq_init(void)
 252 +{
 253 +       int i;
 254 +
 255 +       ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
 256 +       ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
 257 +                        AR2315_PCI_INT_EXT), 0);
 258 +
 259 +       for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
 260 +               int irq = AR2315_PCI_IRQ_BASE + i;
 261 +
 262 +               irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
 263 +                                        handle_level_irq);
 264 +       }
 265 +
 266 +       irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
 267 +
 268 +       /* Clear any pending Abort or external Interrupts
 269 +        * and enable interrupt processing */
 270 +       ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
 271 +                        AR2315_PCI_INT_EXT));
 272 +       ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
 273 +}
 274 +
 275 +static int __init
 276 +ar2315_pci_init(void)
 277 +{
 278 +       u32 reg;
 279 +       int res;
 280 +
 281 +       if (ar231x_devtype != DEV_TYPE_AR2315)
 282 +               return -ENODEV;
 283 +
 284 +       /* Remap PCI config space */
 285 +       configspace = (unsigned long)ioremap_nocache(AR2315_PCIEXT,
 286 +                                                    1 * 1024 * 1024);
 287 +       ar2315_pci_controller.io_map_base =
 288 +                       (unsigned long)ioremap_nocache(AR2315_MEM_BASE +
 289 +                       AR2315_MEM_SIZE, AR2315_IO_SIZE);
 290 +       set_io_port_base(ar2315_pci_controller.io_map_base); /* PCI I/O space*/
 291 +
 292 +       /* Reset PCI DMA logic */
 293 +       reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 294 +       msleep(20);
 295 +       reg &= ~AR2315_RESET_PCIDMA;
 296 +       ar231x_write_reg(AR2315_RESET, reg);
 297 +       msleep(20);
 298 +
 299 +       ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
 300 +                       AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
 301 +
 302 +       ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 303 +                        (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
 304 +       ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 305 +       ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
 306 +                       AR2315_IF_PCI | AR2315_IF_PCI_HOST |
 307 +                       AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
 308 +                                             AR2315_IF_PCI_CLK_SHIFT));
 309 +
 310 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 311 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 312 +                       AR2315_PCIRST_LOW);
 313 +       msleep(100);
 314 +
 315 +       /* Bring the PCI out of reset */
 316 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 317 +                       AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 318 +
 319 +       ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
 320 +                        0x1E | /* 1GB uncached */
 321 +                        (1 << 5) | /* Enable uncached */
 322 +                        (0x2 << 30) /* Base: 0x80000000 */);
 323 +       ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
 324 +
 325 +       msleep(500);
 326 +
 327 +       /* dirty hack - anyone with a datasheet that knows the memory map ? */
 328 +       ioport_resource.start = 0x10000000;
 329 +       ioport_resource.end = 0xffffffff;
 330 +
 331 +       res = ar2315_pci_host_setup();
 332 +       if (res)
 333 +               goto error;
 334 +
 335 +       ar2315_pci_irq_init();
 336 +
 337 +       register_pci_controller(&ar2315_pci_controller);
 338 +
 339 +       return 0;
 340 +
 341 +error:
 342 +       iounmap((void __iomem *)configspace);
 343 +       return res;
 344 +}
 345 +
 346 +arch_initcall(ar2315_pci_init);
 347 --- a/arch/mips/ar231x/Kconfig
 348 +++ b/arch/mips/ar231x/Kconfig
 349 @@ -7,3 +7,10 @@ config ATHEROS_AR2315
 350         bool "Atheros 2315+ support"
 351         depends on ATHEROS_AR231X
 352         default y
 353 +
 354 +config ATHEROS_AR2315_PCI
 355 +       bool "PCI support"
 356 +       depends on ATHEROS_AR2315
 357 +       select HW_HAS_PCI
 358 +       select PCI
 359 +       default y
 360 --- a/arch/mips/ar231x/ar2315.c
 361 +++ b/arch/mips/ar231x/ar2315.c
 362 @@ -104,6 +104,10 @@ ar2315_irq_dispatch(void)
 363                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 364         else if (pending & CAUSEF_IP4)
 365                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 366 +#ifdef CONFIG_ATHEROS_AR2315_PCI
 367 +       else if (pending & CAUSEF_IP5)
 368 +               do_IRQ(AR2315_IRQ_LCBUS_PCI);
 369 +#endif
 370         else if (pending & CAUSEF_IP2)
 371                 do_IRQ(AR2315_IRQ_MISC_INTRS);
 372         else if (pending & CAUSEF_IP7)