1 --- a/arch/mips/ar231x/Makefile
2 +++ b/arch/mips/ar231x/Makefile
3 @@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
5 obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
6 obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
9 +++ b/arch/mips/ar231x/pci.c
12 + * This program is free software; you can redistribute it and/or
13 + * modify it under the terms of the GNU General Public License
14 + * as published by the Free Software Foundation; either version 2
15 + * of the License, or (at your option) any later version.
17 + * This program is distributed in the hope that it will be useful,
18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 + * GNU General Public License for more details.
22 + * You should have received a copy of the GNU General Public License
23 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
26 +#include <linux/types.h>
27 +#include <linux/pci.h>
28 +#include <linux/kernel.h>
29 +#include <linux/init.h>
30 +#include <linux/mm.h>
31 +#include <linux/delay.h>
32 +#include <linux/irq.h>
33 +#include <linux/io.h>
34 +#include <asm/paccess.h>
35 +#include <ar231x_platform.h>
37 +#include <ar2315_regs.h>
40 +#define AR2315_MEM_BASE 0x80800000UL
41 +#define AR2315_MEM_SIZE 0x00ffffffUL
42 +#define AR2315_IO_SIZE 0x00007fffUL
44 +static unsigned long configspace;
46 +static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
48 + int func = PCI_FUNC(devfn);
49 + int dev = PCI_SLOT(devfn);
54 + if (((dev != 0) && (dev != 3)) || (func > 2))
55 + return PCIBIOS_DEVICE_NOT_FOUND;
57 + /* Select Configuration access */
58 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
61 + addr = (u32)configspace + (1 << (13 + dev)) + (func << 8) + where;
70 + err = put_dbe(value, (u8 *)addr);
72 + err = put_dbe(value, (u16 *)addr);
74 + err = put_dbe(value, (u32 *)addr);
77 + err = get_dbe(value, (u8 *)addr);
79 + err = get_dbe(value, (u16 *)addr);
81 + err = get_dbe(value, (u32 *)addr);
88 + /* Select Memory access */
89 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
91 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
94 +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
95 + int size, u32 *value)
97 + return config_access(devfn, where, size, value, 0);
100 +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
101 + int size, u32 value)
103 + return config_access(devfn, where, size, &value, 1);
106 +static struct pci_ops ar231x_pci_ops = {
107 + .read = ar231x_pci_read,
108 + .write = ar231x_pci_write,
111 +static struct resource ar231x_mem_resource = {
112 + .name = "AR2315 PCI MEM",
113 + .start = AR2315_MEM_BASE,
114 + .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE - 1 +
116 + .flags = IORESOURCE_MEM,
119 +static struct resource ar231x_io_resource = {
120 + .name = "AR2315 PCI I/O",
121 + .start = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE,
122 + .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - 1,
123 + .flags = IORESOURCE_IO,
126 +static struct pci_controller ar231x_pci_controller = {
127 + .pci_ops = &ar231x_pci_ops,
128 + .mem_resource = &ar231x_mem_resource,
129 + .io_resource = &ar231x_io_resource,
130 + .mem_offset = 0x00000000UL,
131 + .io_offset = 0x00000000UL,
134 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
136 + return AR2315_IRQ_LCBUS_PCI;
139 +int pcibios_plat_dev_init(struct pci_dev *dev)
141 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
142 + pci_write_config_word(dev, 0x40, 0);
144 + /* Clear any pending Abort or external Interrupts
145 + * and enable interrupt processing */
146 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
147 + ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT |
148 + AR2315_PCI_EXT_INT));
149 + ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT |
150 + AR2315_PCI_EXT_INT));
151 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
157 +ar2315_pci_fixup(struct pci_dev *dev)
159 + unsigned int devfn = dev->devfn;
161 + if (dev->bus->number != 0)
164 + /* Only fix up the PCI host settings */
165 + if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
169 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
170 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
171 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
172 + pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
173 + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
174 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
175 + PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
177 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
180 +ar2315_pci_init(void)
184 + if (ar231x_devtype != DEV_TYPE_AR2315)
187 + /* Remap PCI config space */
188 + configspace = (unsigned long)ioremap_nocache(AR2315_PCIEXT,
190 + ar231x_pci_controller.io_map_base =
191 + (unsigned long)ioremap_nocache(AR2315_MEM_BASE +
192 + AR2315_MEM_SIZE, AR2315_IO_SIZE);
193 + set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
195 + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
198 + reg &= ~AR2315_RESET_PCIDMA;
199 + ar231x_write_reg(AR2315_RESET, reg);
202 + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
203 + AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
205 + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
206 + (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
207 + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
208 + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
209 + AR2315_IF_PCI | AR2315_IF_PCI_HOST |
210 + AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
211 + AR2315_IF_PCI_CLK_SHIFT));
213 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
214 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
215 + AR2315_PCIRST_LOW);
218 + /* Bring the PCI out of reset */
219 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
220 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
222 + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
223 + 0x1E | /* 1GB uncached */
224 + (1 << 5) | /* Enable uncached */
225 + (0x2 << 30) /* Base: 0x80000000 */);
226 + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
230 + /* dirty hack - anyone with a datasheet that knows the memory map ? */
231 + ioport_resource.start = 0x10000000;
232 + ioport_resource.end = 0xffffffff;
234 + register_pci_controller(&ar231x_pci_controller);
239 +arch_initcall(ar2315_pci_init);
240 --- a/arch/mips/ar231x/Kconfig
241 +++ b/arch/mips/ar231x/Kconfig
242 @@ -7,3 +7,10 @@ config ATHEROS_AR2315
243 bool "Atheros 2315+ support"
244 depends on ATHEROS_AR231X
247 +config ATHEROS_AR2315_PCI
249 + depends on ATHEROS_AR2315
253 --- a/arch/mips/ar231x/ar2315.c
254 +++ b/arch/mips/ar231x/ar2315.c
255 @@ -87,6 +87,28 @@ static void ar2315_misc_irq_handler(unsi
256 do_IRQ(AR2315_MISC_IRQ_NONE);
259 +#ifdef CONFIG_ATHEROS_AR2315_PCI
260 +static inline void pci_abort_irq(void)
262 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
265 +static inline void pci_ack_irq(void)
267 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
270 +static void ar2315_pci_irq(int irq)
272 + if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
279 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
282 * Called when an interrupt is received, this function
283 * determines exactly which interrupt it was, and it
284 @@ -104,6 +126,10 @@ ar2315_irq_dispatch(void)
285 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
286 else if (pending & CAUSEF_IP4)
287 do_IRQ(AR2315_IRQ_ENET0_INTRS);
288 +#ifdef CONFIG_ATHEROS_AR2315_PCI
289 + else if (pending & CAUSEF_IP5)
290 + ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
292 else if (pending & CAUSEF_IP2)
293 do_IRQ(AR2315_IRQ_MISC_INTRS);
294 else if (pending & CAUSEF_IP7)