target/linux/atheros/patches-3.14/105-ar2315_pci.patch

   1 --- a/arch/mips/ar231x/Makefile
   2 +++ b/arch/mips/ar231x/Makefile
   3 @@ -14,3 +14,5 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
   4
   5  obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
   6  obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
   7 +obj-$(CONFIG_PCI_AR2315) += pci.o
   8 +
   9 --- /dev/null
  10 +++ b/arch/mips/ar231x/pci.c
  11 @@ -0,0 +1,340 @@
  12 +/*
  13 + * This program is free software; you can redistribute it and/or
  14 + * modify it under the terms of the GNU General Public License
  15 + * as published by the Free Software Foundation; either version 2
  16 + * of the License, or (at your option) any later version.
  17 + *
  18 + * This program is distributed in the hope that it will be useful,
  19 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 + * GNU General Public License for more details.
  22 + *
  23 + * You should have received a copy of the GNU General Public License
  24 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
  25 + */
  26 +
  27 +/**
  28 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  29 + * and interrupt. PCI interface supports MMIO access method, but does not
  30 + * seem to support I/O ports.
  31 + *
  32 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  33 + * a memory read/write command on the PCI bus. 30 LSBs of address on
  34 + * the bus are taken from memory read/write request and 2 MSBs are
  35 + * determined by PCI unit configuration.
  36 + *
  37 + * To work with the configuration space instead of memory is necessary set
  38 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  39 + *
  40 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  41 + * controller BARs are programmend as if an external device is programmed.
  42 + * Which means that during configuration, IDSEL pin of the chip should be
  43 + * asserted.
  44 + *
  45 + * We know (and support) only one board that uses the PCI interface -
  46 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  47 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  48 + * and IDSEL pin of AR125 is connected to AD[16] line.
  49 + */
  50 +
  51 +#include <linux/types.h>
  52 +#include <linux/pci.h>
  53 +#include <linux/kernel.h>
  54 +#include <linux/init.h>
  55 +#include <linux/mm.h>
  56 +#include <linux/delay.h>
  57 +#include <linux/irq.h>
  58 +#include <linux/io.h>
  59 +#include <asm/paccess.h>
  60 +#include <ar231x_platform.h>
  61 +#include <ar231x.h>
  62 +#include <ar2315_regs.h>
  63 +#include "devices.h"
  64 +
  65 +/* Arbitrary size of memory region to access the configuration space */
  66 +#define AR2315_PCI_CFG_SIZE    0x00100000
  67 +
  68 +#define AR2315_PCI_HOST_SLOT   3
  69 +#define AR2315_PCI_HOST_DEVID  ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
  70 +
  71 +static void __iomem *ar2315_pci_cfg_mem;
  72 +
  73 +static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
  74 +                                bool write)
  75 +{
  76 +       int func = PCI_FUNC(devfn);
  77 +       int dev = PCI_SLOT(devfn);
  78 +       u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
  79 +       u32 mask = 0xffffffff >> 8 * (4 - size);
  80 +       u32 sh = (where & 3) * 8;
  81 +       u32 value, isr;
  82 +
  83 +       /* Prevent access past the remapped area */
  84 +       if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
  85 +               return PCIBIOS_DEVICE_NOT_FOUND;
  86 +
  87 +       /* Clear pending errors */
  88 +       ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
  89 +       /* Select Configuration access */
  90 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
  91 +
  92 +       mb();   /* PCI must see space change before we begin */
  93 +
  94 +       value = __raw_readl(ar2315_pci_cfg_mem + addr);
  95 +
  96 +       isr = ar231x_read_reg(AR2315_PCI_ISR);
  97 +       if (isr & AR2315_PCI_INT_ABORT)
  98 +               goto exit_err;
  99 +
 100 +       if (write) {
 101 +               value = (value & ~(mask << sh)) | *ptr << sh;
 102 +               __raw_writel(value, ar2315_pci_cfg_mem + addr);
 103 +               isr = ar231x_read_reg(AR2315_PCI_ISR);
 104 +               if (isr & AR2315_PCI_INT_ABORT)
 105 +                       goto exit_err;
 106 +       } else {
 107 +               *ptr = (value >> sh) & mask;
 108 +       }
 109 +
 110 +       goto exit;
 111 +
 112 +exit_err:
 113 +       ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 114 +       if (!write)
 115 +               *ptr = 0xffffffff;
 116 +
 117 +exit:
 118 +       /* Select Memory access */
 119 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
 120 +
 121 +       return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
 122 +                                           PCIBIOS_SUCCESSFUL;
 123 +}
 124 +
 125 +static inline int ar2315_pci_local_cfg_rd(unsigned devfn, int where, u32 *val)
 126 +{
 127 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), val, false);
 128 +}
 129 +
 130 +static inline int ar2315_pci_local_cfg_wr(unsigned devfn, int where, u32 val)
 131 +{
 132 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), &val, true);
 133 +}
 134 +
 135 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
 136 +                              int where, int size, u32 *value)
 137 +{
 138 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 139 +               return PCIBIOS_DEVICE_NOT_FOUND;
 140 +
 141 +       return ar2315_pci_cfg_access(devfn, where, size, value, 0);
 142 +}
 143 +
 144 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
 145 +                               int where, int size, u32 value)
 146 +{
 147 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 148 +               return PCIBIOS_DEVICE_NOT_FOUND;
 149 +
 150 +       return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
 151 +}
 152 +
 153 +static struct pci_ops ar2315_pci_ops = {
 154 +       .read   = ar2315_pci_cfg_read,
 155 +       .write  = ar2315_pci_cfg_write,
 156 +};
 157 +
 158 +static struct resource ar2315_mem_resource = {
 159 +       .name   = "ar2315-pci-mem",
 160 +       .start  = AR2315_PCIEXT,
 161 +       .end    = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1,
 162 +       .flags  = IORESOURCE_MEM,
 163 +};
 164 +
 165 +/* PCI controller does not support I/O ports */
 166 +static struct resource ar2315_io_resource = {
 167 +       .name   = "ar2315-pci-io",
 168 +       .start  = 0,
 169 +       .end    = 0,
 170 +       .flags  = IORESOURCE_IO,
 171 +};
 172 +
 173 +static struct pci_controller ar2315_pci_controller = {
 174 +       .pci_ops        = &ar2315_pci_ops,
 175 +       .mem_resource   = &ar2315_mem_resource,
 176 +       .io_resource    = &ar2315_io_resource,
 177 +       .mem_offset     = 0x00000000UL,
 178 +       .io_offset      = 0x00000000UL,
 179 +};
 180 +
 181 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 182 +{
 183 +       return AR2315_PCI_IRQ_EXT;
 184 +}
 185 +
 186 +int pcibios_plat_dev_init(struct pci_dev *dev)
 187 +{
 188 +       return 0;
 189 +}
 190 +
 191 +static int ar2315_pci_host_setup(void)
 192 +{
 193 +       unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
 194 +       int res;
 195 +       u32 id;
 196 +
 197 +       res = ar2315_pci_local_cfg_rd(devfn, PCI_VENDOR_ID, &id);
 198 +       if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
 199 +               return -ENODEV;
 200 +
 201 +       /* Program MBARs */
 202 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_0,
 203 +                               AR2315_PCI_HOST_MBAR0);
 204 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_1,
 205 +                               AR2315_PCI_HOST_MBAR1);
 206 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_2,
 207 +                               AR2315_PCI_HOST_MBAR2);
 208 +
 209 +       /* Run */
 210 +       ar2315_pci_local_cfg_wr(devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
 211 +                               PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 212 +                               PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 213 +                               PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 214 +
 215 +       return 0;
 216 +}
 217 +
 218 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
 219 +{
 220 +       u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
 221 +                     ar231x_read_reg(AR2315_PCI_IMR);
 222 +
 223 +       if (pending & AR2315_PCI_INT_EXT)
 224 +               generic_handle_irq(AR2315_PCI_IRQ_EXT);
 225 +       else if (pending & AR2315_PCI_INT_ABORT)
 226 +               generic_handle_irq(AR2315_PCI_IRQ_ABORT);
 227 +       else
 228 +               spurious_interrupt();
 229 +}
 230 +
 231 +static void ar2315_pci_irq_mask(struct irq_data *d)
 232 +{
 233 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 234 +
 235 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 236 +}
 237 +
 238 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
 239 +{
 240 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 241 +
 242 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 243 +       ar231x_write_reg(AR2315_PCI_ISR, m);
 244 +}
 245 +
 246 +static void ar2315_pci_irq_unmask(struct irq_data *d)
 247 +{
 248 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 249 +
 250 +       ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
 251 +}
 252 +
 253 +static struct irq_chip ar2315_pci_irq_chip = {
 254 +       .name = "AR2315-PCI",
 255 +       .irq_mask = ar2315_pci_irq_mask,
 256 +       .irq_mask_ack = ar2315_pci_irq_mask_ack,
 257 +       .irq_unmask = ar2315_pci_irq_unmask,
 258 +};
 259 +
 260 +static void ar2315_pci_irq_init(void)
 261 +{
 262 +       int i;
 263 +
 264 +       ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
 265 +       ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
 266 +                        AR2315_PCI_INT_EXT), 0);
 267 +
 268 +       for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
 269 +               int irq = AR2315_PCI_IRQ_BASE + i;
 270 +
 271 +               irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
 272 +                                        handle_level_irq);
 273 +       }
 274 +
 275 +       irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
 276 +
 277 +       /* Clear any pending Abort or external Interrupts
 278 +        * and enable interrupt processing */
 279 +       ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
 280 +                        AR2315_PCI_INT_EXT));
 281 +       ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
 282 +}
 283 +
 284 +static int __init
 285 +ar2315_pci_init(void)
 286 +{
 287 +       u32 reg;
 288 +       int res;
 289 +
 290 +       if (ar231x_devtype != DEV_TYPE_AR2315)
 291 +               return -ENODEV;
 292 +
 293 +       /* Remap PCI config space */
 294 +       ar2315_pci_cfg_mem = ioremap_nocache(AR2315_PCIEXT,
 295 +                                            AR2315_PCI_CFG_SIZE);
 296 +       if (!ar2315_pci_cfg_mem) {
 297 +               pr_err("ar2315-pci: failed to remap PCI config space\n");
 298 +               return -ENOMEM;
 299 +       }
 300 +
 301 +       /* Reset PCI DMA logic */
 302 +       reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 303 +       msleep(20);
 304 +       reg &= ~AR2315_RESET_PCIDMA;
 305 +       ar231x_write_reg(AR2315_RESET, reg);
 306 +       msleep(20);
 307 +
 308 +       ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
 309 +                       AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
 310 +
 311 +       ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 312 +                        (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
 313 +       ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 314 +       ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
 315 +                       AR2315_IF_PCI | AR2315_IF_PCI_HOST |
 316 +                       AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
 317 +                                             AR2315_IF_PCI_CLK_SHIFT));
 318 +
 319 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 320 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 321 +                       AR2315_PCIRST_LOW);
 322 +       msleep(100);
 323 +
 324 +       /* Bring the PCI out of reset */
 325 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 326 +                       AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 327 +
 328 +       ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
 329 +                        0x1E | /* 1GB uncached */
 330 +                        (1 << 5) | /* Enable uncached */
 331 +                        (0x2 << 30) /* Base: 0x80000000 */);
 332 +       ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
 333 +
 334 +       msleep(500);
 335 +
 336 +       res = ar2315_pci_host_setup();
 337 +       if (res)
 338 +               goto error;
 339 +
 340 +       ar2315_pci_irq_init();
 341 +
 342 +       register_pci_controller(&ar2315_pci_controller);
 343 +
 344 +       return 0;
 345 +
 346 +error:
 347 +       iounmap(ar2315_pci_cfg_mem);
 348 +       return res;
 349 +}
 350 +
 351 +arch_initcall(ar2315_pci_init);
 352 --- a/arch/mips/ar231x/Kconfig
 353 +++ b/arch/mips/ar231x/Kconfig
 354 @@ -7,3 +7,10 @@ config ATHEROS_AR2315
 355         bool "Atheros 2315+ support"
 356         depends on ATHEROS_AR231X
 357         default y
 358 +
 359 +config PCI_AR2315
 360 +       bool "AR2315 PCI controller support"
 361 +       depends on ATHEROS_AR2315
 362 +       select HW_HAS_PCI
 363 +       select PCI
 364 +       default y
 365 --- a/arch/mips/ar231x/ar2315.c
 366 +++ b/arch/mips/ar231x/ar2315.c
 367 @@ -104,6 +104,10 @@ ar2315_irq_dispatch(void)
 368                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 369         else if (pending & CAUSEF_IP4)
 370                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 371 +#ifdef CONFIG_PCI_AR2315
 372 +       else if (pending & CAUSEF_IP5)
 373 +               do_IRQ(AR2315_IRQ_LCBUS_PCI);
 374 +#endif
 375         else if (pending & CAUSEF_IP2)
 376                 do_IRQ(AR2315_IRQ_MISC_INTRS);
 377         else if (pending & CAUSEF_IP7)