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atheros: v3.18: rework early initialization
[openwrt/openwrt.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,234 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ath25_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == ATH25_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ath25_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ath25_board.radio = addr + 0x10000;
140 +
141 + if (ath25_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ath25_find_config(u8 *flash_limit)
191 +{
192 + struct ath25_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ath25_board.config = NULL;
202 + ath25_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ath25_board.config = (struct ath25_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ath25_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ath25_board.radio)
241 + rcfg = (u8 *)ath25_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ath25_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ath25_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ath25_halt;
275 + pm_power_off = ath25_halt;
276 +
277 + if (is_ar5312())
278 + ar5312_plat_mem_setup();
279 + else
280 + ar2315_plat_mem_setup();
281 +
282 + /* Disable data watchpoints */
283 + write_c0_watchlo0(0);
284 +}
285 +
286 +asmlinkage void plat_irq_dispatch(void)
287 +{
288 + ath25_irq_dispatch();
289 +}
290 +
291 +void __init plat_time_init(void)
292 +{
293 + if (is_ar5312())
294 + ar5312_plat_time_init();
295 + else
296 + ar2315_plat_time_init();
297 +}
298 +
299 +unsigned int __cpuinit get_c0_compare_int(void)
300 +{
301 + return CP0_LEGACY_COMPARE_IRQ;
302 +}
303 +
304 +void __init arch_init_irq(void)
305 +{
306 + clear_c0_status(ST0_IM);
307 + mips_cpu_irq_init();
308 +
309 + /* Initialize interrupt controllers */
310 + if (is_ar5312())
311 + ar5312_arch_init_irq();
312 + else
313 + ar2315_arch_init_irq();
314 +}
315 --- /dev/null
316 +++ b/arch/mips/ath25/prom.c
317 @@ -0,0 +1,26 @@
318 +/*
319 + * This file is subject to the terms and conditions of the GNU General Public
320 + * License. See the file "COPYING" in the main directory of this archive
321 + * for more details.
322 + *
323 + * Copyright MontaVista Software Inc
324 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
325 + * Copyright (C) 2006 FON Technology, SL.
326 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
327 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
328 + */
329 +
330 +/*
331 + * Prom setup file for ar231x
332 + */
333 +
334 +#include <linux/init.h>
335 +#include <asm/bootinfo.h>
336 +
337 +void __init prom_init(void)
338 +{
339 +}
340 +
341 +void __init prom_free_prom_memory(void)
342 +{
343 +}
344 --- /dev/null
345 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
346 @@ -0,0 +1,84 @@
347 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
348 +#define __ASM_MACH_ATH25_PLATFORM_H
349 +
350 +#include <linux/etherdevice.h>
351 +
352 +/*
353 + * This is board-specific data that is stored in a "fixed" location in flash.
354 + * It is shared across operating systems, so it should not be changed lightly.
355 + * The main reason we need it is in order to extract the ethernet MAC
356 + * address(es).
357 + */
358 +struct ath25_boarddata {
359 + u32 magic; /* board data is valid */
360 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
361 + u16 cksum; /* checksum (starting with BD_REV 2) */
362 + u16 rev; /* revision of this struct */
363 +#define BD_REV 4
364 + char board_name[64]; /* Name of board */
365 + u16 major; /* Board major number */
366 + u16 minor; /* Board minor number */
367 + u32 flags; /* Board configuration */
368 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
369 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
370 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
371 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
372 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
373 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
374 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
375 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
376 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
377 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
378 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
379 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
380 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
381 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
382 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
383 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
384 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
385 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
386 + u16 reset_config_gpio; /* Reset factory GPIO pin */
387 + u16 sys_led_gpio; /* System LED GPIO pin */
388 +
389 + u32 cpu_freq; /* CPU core frequency in Hz */
390 + u32 sys_freq; /* System frequency in Hz */
391 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
392 +
393 + u8 wlan0_mac[ETH_ALEN];
394 + u8 enet0_mac[ETH_ALEN];
395 + u8 enet1_mac[ETH_ALEN];
396 +
397 + u16 pci_id; /* Pseudo PCIID for common code */
398 + u16 mem_cap; /* cap bank1 in MB */
399 +
400 + /* version 3 */
401 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
402 +};
403 +
404 +#define BOARD_CONFIG_BUFSZ 0x1000
405 +
406 +/*
407 + * Platform device information for the Wireless MAC
408 + */
409 +struct ar231x_board_config {
410 + u16 devid;
411 +
412 + /* board config data */
413 + struct ath25_boarddata *config;
414 +
415 + /* radio calibration data */
416 + const char *radio;
417 +};
418 +
419 +/*
420 + * Platform device information for the Ethernet MAC
421 + */
422 +struct ar231x_eth {
423 + void (*reset_set)(u32);
424 + void (*reset_clear)(u32);
425 + u32 reset_mac;
426 + u32 reset_phy;
427 + char *macaddr;
428 +};
429 +
430 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
431 --- /dev/null
432 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
433 @@ -0,0 +1,64 @@
434 +/*
435 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
436 + *
437 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
438 + *
439 + * This file was derived from: include/asm-mips/cpu-features.h
440 + * Copyright (C) 2003, 2004 Ralf Baechle
441 + * Copyright (C) 2004 Maciej W. Rozycki
442 + *
443 + * This program is free software; you can redistribute it and/or modify it
444 + * under the terms of the GNU General Public License version 2 as published
445 + * by the Free Software Foundation.
446 + *
447 + */
448 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
449 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
450 +
451 +/*
452 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
453 + */
454 +#define cpu_has_tlb 1
455 +#define cpu_has_4kex 1
456 +#define cpu_has_3k_cache 0
457 +#define cpu_has_4k_cache 1
458 +#define cpu_has_tx39_cache 0
459 +#define cpu_has_sb1_cache 0
460 +#define cpu_has_fpu 0
461 +#define cpu_has_32fpr 0
462 +#define cpu_has_counter 1
463 +#define cpu_has_ejtag 1
464 +
465 +#if !defined(CONFIG_SOC_AR5312)
466 +# define cpu_has_llsc 1
467 +#else
468 +/*
469 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
470 + * ll/sc instructions.
471 + */
472 +# define cpu_has_llsc 0
473 +#endif
474 +
475 +#define cpu_has_mips16 0
476 +#define cpu_has_mdmx 0
477 +#define cpu_has_mips3d 0
478 +#define cpu_has_smartmips 0
479 +
480 +#define cpu_has_mips32r1 1
481 +
482 +#if !defined(CONFIG_SOC_AR5312)
483 +# define cpu_has_mips32r2 1
484 +#endif
485 +
486 +#define cpu_has_mips64r1 0
487 +#define cpu_has_mips64r2 0
488 +
489 +#define cpu_has_dsp 0
490 +#define cpu_has_mipsmt 0
491 +
492 +#define cpu_has_64bits 0
493 +#define cpu_has_64bit_zero_reg 0
494 +#define cpu_has_64bit_gp_regs 0
495 +#define cpu_has_64bit_addresses 0
496 +
497 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
498 --- /dev/null
499 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
500 @@ -0,0 +1,76 @@
501 +/*
502 + * This file is subject to the terms and conditions of the GNU General Public
503 + * License. See the file "COPYING" in the main directory of this archive
504 + * for more details.
505 + *
506 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
507 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
508 + *
509 + */
510 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
511 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
512 +
513 +#include <linux/device.h>
514 +#include <ar2315_regs.h>
515 +
516 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
517 +{
518 +#ifdef CONFIG_PCI
519 + extern struct bus_type pci_bus_type;
520 +
521 + if (dev && dev->bus == &pci_bus_type)
522 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
523 +#endif
524 + return 0;
525 +}
526 +
527 +static inline dma_addr_t
528 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
529 +{
530 + return virt_to_phys(addr) + ath25_dev_offset(dev);
531 +}
532 +
533 +static inline dma_addr_t
534 +plat_map_dma_mem_page(struct device *dev, struct page *page)
535 +{
536 + return page_to_phys(page) + ath25_dev_offset(dev);
537 +}
538 +
539 +static inline unsigned long
540 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
541 +{
542 + return dma_addr - ath25_dev_offset(dev);
543 +}
544 +
545 +static inline void
546 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
547 + enum dma_data_direction direction)
548 +{
549 +}
550 +
551 +static inline int plat_dma_supported(struct device *dev, u64 mask)
552 +{
553 + return 1;
554 +}
555 +
556 +static inline void plat_extra_sync_for_device(struct device *dev)
557 +{
558 +}
559 +
560 +static inline int plat_dma_mapping_error(struct device *dev,
561 + dma_addr_t dma_addr)
562 +{
563 + return 0;
564 +}
565 +
566 +static inline int plat_device_is_coherent(struct device *dev)
567 +{
568 +#ifdef CONFIG_DMA_COHERENT
569 + return 1;
570 +#endif
571 +#ifdef CONFIG_DMA_NONCOHERENT
572 + return 0;
573 +#endif
574 +}
575 +
576 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
577 --- /dev/null
578 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
579 @@ -0,0 +1,16 @@
580 +#ifndef __ASM_MACH_ATH25_GPIO_H
581 +#define __ASM_MACH_ATH25_GPIO_H
582 +
583 +#include <asm-generic/gpio.h>
584 +
585 +#define gpio_get_value __gpio_get_value
586 +#define gpio_set_value __gpio_set_value
587 +#define gpio_cansleep __gpio_cansleep
588 +#define gpio_to_irq __gpio_to_irq
589 +
590 +static inline int irq_to_gpio(unsigned irq)
591 +{
592 + return -EINVAL;
593 +}
594 +
595 +#endif /* __ASM_MACH_ATH25_GPIO_H */
596 --- /dev/null
597 +++ b/arch/mips/include/asm/mach-ath25/war.h
598 @@ -0,0 +1,25 @@
599 +/*
600 + * This file is subject to the terms and conditions of the GNU General Public
601 + * License. See the file "COPYING" in the main directory of this archive
602 + * for more details.
603 + *
604 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
605 + */
606 +#ifndef __ASM_MACH_ATH25_WAR_H
607 +#define __ASM_MACH_ATH25_WAR_H
608 +
609 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
610 +#define R4600_V1_HIT_CACHEOP_WAR 0
611 +#define R4600_V2_HIT_CACHEOP_WAR 0
612 +#define R5432_CP0_INTERRUPT_WAR 0
613 +#define BCM1250_M3_WAR 0
614 +#define SIBYTE_1956_WAR 0
615 +#define MIPS4K_ICACHE_REFILL_WAR 0
616 +#define MIPS_CACHE_SYNC_WAR 0
617 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
618 +#define RM9000_CDEX_SMP_WAR 0
619 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
620 +#define R10000_LLSC_WAR 0
621 +#define MIPS34K_MISSED_ITLB_WAR 0
622 +
623 +#endif /* __ASM_MACH_ATH25_WAR_H */
624 --- /dev/null
625 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
626 @@ -0,0 +1,608 @@
627 +/*
628 + * Register definitions for AR2315+
629 + *
630 + * This file is subject to the terms and conditions of the GNU General Public
631 + * License. See the file "COPYING" in the main directory of this archive
632 + * for more details.
633 + *
634 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
635 + * Copyright (C) 2006 FON Technology, SL.
636 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
637 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
638 + */
639 +
640 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
641 +#define __ASM_MACH_ATH25_AR2315_REGS_H
642 +
643 +/*
644 + * IRQs
645 + */
646 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
647 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
648 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
649 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
650 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
651 +
652 +/*
653 + * Miscellaneous interrupts, which share IP2.
654 + */
655 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
656 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
657 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
658 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
659 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
660 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
661 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
662 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
663 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
664 +#define AR2315_MISC_IRQ_COUNT 9
665 +
666 +/*
667 + * PCI interrupts, which share IP5
668 + * Keep ordered according to AR2315_PCI_INT_XXX bits
669 + */
670 +#define AR2315_PCI_IRQ_BASE 0x50
671 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
672 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
673 +#define AR2315_PCI_IRQ_COUNT 2
674 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
675 +
676 +/*
677 + * Address map
678 + */
679 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
680 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
681 +#define AR2315_PCI 0x10100000 /* PCI MMR */
682 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
683 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
684 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
685 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
686 +#define AR2315_UART0 0x11100000 /* UART MMR */
687 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
688 +#define AR2315_PCIEXT 0x80000000 /* pci external */
689 +#define AR2315_PCIEXT_SZ 0x40000000
690 +
691 +/* MII registers offset inside Ethernet MMR region */
692 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
693 +
694 +/*
695 + * Cold reset register
696 + */
697 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
698 +
699 +#define AR2315_RESET_COLD_AHB 0x00000001
700 +#define AR2315_RESET_COLD_APB 0x00000002
701 +#define AR2315_RESET_COLD_CPU 0x00000004
702 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
703 +#define AR2315_RESET_SYSTEM \
704 + (RESET_COLD_CPU |\
705 + RESET_COLD_APB |\
706 + RESET_COLD_AHB) /* full system */
707 +#define AR2317_RESET_SYSTEM 0x00000010
708 +
709 +/*
710 + * Reset register
711 + */
712 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
713 +
714 +/* warm reset WLAN0 MAC */
715 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
716 +/* warm reset WLAN0 BaseBand */
717 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
718 +/* warm reset MPEG-TS */
719 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
720 +/* warm reset PCI ahb/dma */
721 +#define AR2315_RESET_PCIDMA 0x00000008
722 +/* warm reset memory controller */
723 +#define AR2315_RESET_MEMCTL 0x00000010
724 +/* warm reset local bus */
725 +#define AR2315_RESET_LOCAL 0x00000020
726 +/* warm reset I2C bus */
727 +#define AR2315_RESET_I2C_RSVD 0x00000040
728 +/* warm reset SPI interface */
729 +#define AR2315_RESET_SPI 0x00000080
730 +/* warm reset UART0 */
731 +#define AR2315_RESET_UART0 0x00000100
732 +/* warm reset IR interface */
733 +#define AR2315_RESET_IR_RSVD 0x00000200
734 +/* cold reset ENET0 phy */
735 +#define AR2315_RESET_EPHY0 0x00000400
736 +/* cold reset ENET0 mac */
737 +#define AR2315_RESET_ENET0 0x00000800
738 +
739 +/*
740 + * AHB master arbitration control
741 + */
742 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
743 +
744 +/* CPU, default */
745 +#define AR2315_ARB_CPU 0x00000001
746 +/* WLAN */
747 +#define AR2315_ARB_WLAN 0x00000002
748 +/* MPEG-TS */
749 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
750 +/* LOCAL */
751 +#define AR2315_ARB_LOCAL 0x00000008
752 +/* PCI */
753 +#define AR2315_ARB_PCI 0x00000010
754 +/* Ethernet */
755 +#define AR2315_ARB_ETHERNET 0x00000020
756 +/* retry policy, debug only */
757 +#define AR2315_ARB_RETRY 0x00000100
758 +
759 +/*
760 + * Config Register
761 + */
762 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
763 +
764 +/* EC - AHB bridge endianess */
765 +#define AR2315_CONFIG_AHB 0x00000001
766 +/* WLAN byteswap */
767 +#define AR2315_CONFIG_WLAN 0x00000002
768 +/* MPEG-TS byteswap */
769 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
770 +/* PCI byteswap */
771 +#define AR2315_CONFIG_PCI 0x00000008
772 +/* Memory controller endianess */
773 +#define AR2315_CONFIG_MEMCTL 0x00000010
774 +/* Local bus byteswap */
775 +#define AR2315_CONFIG_LOCAL 0x00000020
776 +/* Ethernet byteswap */
777 +#define AR2315_CONFIG_ETHERNET 0x00000040
778 +
779 +/* CPU write buffer merge */
780 +#define AR2315_CONFIG_MERGE 0x00000200
781 +/* CPU big endian */
782 +#define AR2315_CONFIG_CPU 0x00000400
783 +#define AR2315_CONFIG_PCIAHB 0x00000800
784 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
785 +/* SPI byteswap */
786 +#define AR2315_CONFIG_SPI 0x00008000
787 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
788 +#define AR2315_CONFIG_CPU_PCI 0x00020000
789 +#define AR2315_CONFIG_CPU_MMR 0x00040000
790 +#define AR2315_CONFIG_BIG 0x00000400
791 +
792 +/*
793 + * NMI control
794 + */
795 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
796 +
797 +#define AR2315_NMI_EN 1
798 +
799 +/*
800 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
801 + */
802 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
803 +
804 +#define AR2315_REV_MAJ 0x00f0
805 +#define AR2315_REV_MAJ_S 4
806 +#define AR2315_REV_MIN 0x000f
807 +#define AR2315_REV_MIN_S 0
808 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
809 +
810 +/*
811 + * Interface Enable
812 + */
813 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
814 +
815 +#define AR2315_IF_MASK 0x00000007
816 +#define AR2315_IF_DISABLED 0
817 +#define AR2315_IF_PCI 1
818 +#define AR2315_IF_TS_LOCAL 2
819 +/* only for emulation with separate pins */
820 +#define AR2315_IF_ALL 3
821 +#define AR2315_IF_LOCAL_HOST 0x00000008
822 +#define AR2315_IF_PCI_HOST 0x00000010
823 +#define AR2315_IF_PCI_INTR 0x00000020
824 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
825 +#define AR2315_IF_PCI_CLK_INPUT 0
826 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
827 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
828 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
829 +#define AR2315_IF_PCI_CLK_SHIFT 16
830 +
831 +/*
832 + * APB Interrupt control
833 + */
834 +
835 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
836 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
837 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
838 +
839 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
840 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
841 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
842 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
843 +#define AR2315_ISR_APB 0x0010 /* APB error */
844 +#define AR2315_ISR_TIMER 0x0020 /* timer */
845 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
846 +#define AR2315_ISR_WD 0x0080 /* watchdog */
847 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
848 +
849 +#define AR2315_GISR_MISC 0x0001
850 +#define AR2315_GISR_WLAN0 0x0002
851 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
852 +#define AR2315_GISR_LOCALPCI 0x0008
853 +#define AR2315_GISR_WMACPOLL 0x0010
854 +#define AR2315_GISR_TIMER 0x0020
855 +#define AR2315_GISR_ETHERNET 0x0040
856 +
857 +/*
858 + * Interrupt routing from IO to the processor IP bits
859 + * Define our inter mask and level
860 + */
861 +#define AR2315_INTR_MISCIO SR_IBIT3
862 +#define AR2315_INTR_WLAN0 SR_IBIT4
863 +#define AR2315_INTR_ENET0 SR_IBIT5
864 +#define AR2315_INTR_LOCALPCI SR_IBIT6
865 +#define AR2315_INTR_WMACPOLL SR_IBIT7
866 +#define AR2315_INTR_COMPARE SR_IBIT8
867 +
868 +/*
869 + * Timers
870 + */
871 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
872 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
873 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
874 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
875 +
876 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
877 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
878 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
879 +
880 +/*
881 + * CPU Performance Counters
882 + */
883 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
884 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
885 +
886 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
887 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
888 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
889 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
890 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
891 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
892 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
893 +
894 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
895 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
896 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
897 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
898 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
899 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
900 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
901 +
902 +/*
903 + * AHB Error Reporting.
904 + */
905 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
906 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
907 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
908 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
909 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
910 +
911 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
912 + /* write 1 to clear all bits in ERR0 */
913 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
914 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
915 +
916 +#define AR2315_PROCERR_HMAST 0x0000000f
917 +#define AR2315_PROCERR_HMAST_DFLT 0
918 +#define AR2315_PROCERR_HMAST_WMAC 1
919 +#define AR2315_PROCERR_HMAST_ENET 2
920 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
921 +#define AR2315_PROCERR_HMAST_LOCAL 4
922 +#define AR2315_PROCERR_HMAST_CPU 5
923 +#define AR2315_PROCERR_HMAST_PCITGT 6
924 +
925 +#define AR2315_PROCERR_HMAST_S 0
926 +#define AR2315_PROCERR_HWRITE 0x00000010
927 +#define AR2315_PROCERR_HSIZE 0x00000060
928 +#define AR2315_PROCERR_HSIZE_S 5
929 +#define AR2315_PROCERR_HTRANS 0x00000180
930 +#define AR2315_PROCERR_HTRANS_S 7
931 +#define AR2315_PROCERR_HBURST 0x00000e00
932 +#define AR2315_PROCERR_HBURST_S 9
933 +
934 +/*
935 + * Clock Control
936 + */
937 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
938 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
939 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
940 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
941 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
942 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
943 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
944 +
945 +/* PLLc Control fields */
946 +#define PLLC_REF_DIV_M 0x00000003
947 +#define PLLC_REF_DIV_S 0
948 +#define PLLC_FDBACK_DIV_M 0x0000007C
949 +#define PLLC_FDBACK_DIV_S 2
950 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
951 +#define PLLC_ADD_FDBACK_DIV_S 7
952 +#define PLLC_CLKC_DIV_M 0x0001c000
953 +#define PLLC_CLKC_DIV_S 14
954 +#define PLLC_CLKM_DIV_M 0x00700000
955 +#define PLLC_CLKM_DIV_S 20
956 +
957 +/* CPU CLK Control fields */
958 +#define CPUCLK_CLK_SEL_M 0x00000003
959 +#define CPUCLK_CLK_SEL_S 0
960 +#define CPUCLK_CLK_DIV_M 0x0000000c
961 +#define CPUCLK_CLK_DIV_S 2
962 +
963 +/* AMBA CLK Control fields */
964 +#define AMBACLK_CLK_SEL_M 0x00000003
965 +#define AMBACLK_CLK_SEL_S 0
966 +#define AMBACLK_CLK_DIV_M 0x0000000c
967 +#define AMBACLK_CLK_DIV_S 2
968 +
969 +/* GPIO MMR base address */
970 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
971 +
972 +#define AR2315_RESET_GPIO 5
973 +
974 +/*
975 + * PCI Clock Control
976 + */
977 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
978 +
979 +#define AR2315_PCICLK_INPUT_M 0x3
980 +#define AR2315_PCICLK_INPUT_S 0
981 +
982 +#define AR2315_PCICLK_PLLC_CLKM 0
983 +#define AR2315_PCICLK_PLLC_CLKM1 1
984 +#define AR2315_PCICLK_PLLC_CLKC 2
985 +#define AR2315_PCICLK_REF_CLK 3
986 +
987 +#define AR2315_PCICLK_DIV_M 0xc
988 +#define AR2315_PCICLK_DIV_S 2
989 +
990 +#define AR2315_PCICLK_IN_FREQ 0
991 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
992 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
993 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
994 +
995 +/*
996 + * Observation Control Register
997 + */
998 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
999 +#define OCR_GPIO0_IRIN 0x0040
1000 +#define OCR_GPIO1_IROUT 0x0080
1001 +#define OCR_GPIO3_RXCLR 0x0200
1002 +
1003 +/*
1004 + * General Clock Control
1005 + */
1006 +
1007 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1008 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1009 +#define MISCCLK_PROCREFCLK 0x00000002
1010 +
1011 +/*
1012 + * SDRAM Controller
1013 + * - No read or write buffers are included.
1014 + */
1015 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1016 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1017 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1018 +
1019 +#define SDRAM_DATA_WIDTH_M 0x00006000
1020 +#define SDRAM_DATA_WIDTH_S 13
1021 +
1022 +#define SDRAM_COL_WIDTH_M 0x00001E00
1023 +#define SDRAM_COL_WIDTH_S 9
1024 +
1025 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1026 +#define SDRAM_ROW_WIDTH_S 5
1027 +
1028 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1029 +#define SDRAM_BANKADDR_BITS_S 3
1030 +
1031 +/*
1032 + * PCI Bus Interface Registers
1033 + */
1034 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1035 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1036 +
1037 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1038 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1039 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1040 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1041 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1042 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1043 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1044 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1045 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1046 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1047 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1048 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1049 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1050 + * disable */
1051 +
1052 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1053 +
1054 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1055 +
1056 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1057 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1058 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1059 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1060 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1061 +
1062 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1063 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1064 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1065 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1066 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1067 +
1068 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1069 +
1070 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1071 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1072 +
1073 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1074 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1075 +
1076 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1077 +
1078 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1079 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1080 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1081 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1082 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1083 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1084 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1085 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1086 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1087 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1088 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1089 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1090 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1091 +
1092 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1093 +
1094 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1095 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1096 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1097 +
1098 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1099 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1100 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1101 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1102 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1103 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1104 +
1105 +/*
1106 + * Local Bus Interface Registers
1107 + */
1108 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1109 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1110 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1111 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1112 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1113 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1114 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1115 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1116 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1117 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1118 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1119 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1120 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1121 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1122 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1123 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1124 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1125 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1126 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1127 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1128 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1129 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1130 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1131 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1132 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1133 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1134 +
1135 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1136 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1137 +
1138 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1139 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1140 +
1141 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1142 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1143 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1144 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1145 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1146 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1147 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1148 +#define AR2315_LBM_TIMEOUT_SHFT 7
1149 +#define AR2315_LBM_PORTMUX 0x07000000
1150 +
1151 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1152 +
1153 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1154 +#define AR2315_LB_TXEN_0 0x01
1155 +#define AR2315_LB_TXEN_1 0x02
1156 +#define AR2315_LB_TXEN_2 0x04
1157 +#define AR2315_LB_TXEN_3 0x08
1158 +
1159 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1160 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1161 +
1162 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1163 +#define AR2315_LB_RXEN 0x01
1164 +
1165 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1166 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1167 +
1168 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1169 +#define AR2315_INT_TX_DESC 0x0001
1170 +#define AR2315_INT_TX_OK 0x0002
1171 +#define AR2315_INT_TX_ERR 0x0004
1172 +#define AR2315_INT_TX_EOF 0x0008
1173 +#define AR2315_INT_RX_DESC 0x0010
1174 +#define AR2315_INT_RX_OK 0x0020
1175 +#define AR2315_INT_RX_ERR 0x0040
1176 +#define AR2315_INT_RX_EOF 0x0080
1177 +#define AR2315_INT_TX_TRUNC 0x0100
1178 +#define AR2315_INT_TX_STARVE 0x0200
1179 +#define AR2315_INT_LB_TIMEOUT 0x0400
1180 +#define AR2315_INT_LB_ERR 0x0800
1181 +#define AR2315_INT_MBOX_WR 0x1000
1182 +#define AR2315_INT_MBOX_RD 0x2000
1183 +
1184 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1185 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1186 +
1187 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1188 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1189 +
1190 +/*
1191 + * IR Interface Registers
1192 + */
1193 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1194 +
1195 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1196 +
1197 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1198 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1199 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1200 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1201 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1202 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1203 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1204 +
1205 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1206 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1207 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1208 +
1209 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1210 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1211 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1212 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1213 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1214 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1215 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1216 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1217 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1218 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1219 +
1220 +/*
1221 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1222 + * of PCI host controller to enable DMA. The same value should be used as the
1223 + * offset to calculate the physical address of DMA buffer for PCI devices.
1224 + */
1225 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1226 +
1227 +/* ??? access BAR */
1228 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1229 +/* RAM access BAR */
1230 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1231 +/* ??? access BAR */
1232 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1233 +
1234 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1235 --- /dev/null
1236 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1237 @@ -0,0 +1,235 @@
1238 +/*
1239 + * This file is subject to the terms and conditions of the GNU General Public
1240 + * License. See the file "COPYING" in the main directory of this archive
1241 + * for more details.
1242 + *
1243 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1244 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1245 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1246 + */
1247 +
1248 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1249 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1250 +
1251 +#include <asm/addrspace.h>
1252 +
1253 +/*
1254 + * IRQs
1255 + */
1256 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1257 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1258 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1259 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1260 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1261 +
1262 +/*
1263 + * Miscellaneous interrupts, which share IP6.
1264 + */
1265 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1266 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1267 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1268 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1269 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1270 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1271 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1272 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1273 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1274 +#define AR5312_MISC_IRQ_COUNT 9
1275 +
1276 +/*
1277 + * Address Map
1278 + */
1279 +#define AR5312_WLAN0 0x18000000
1280 +#define AR5312_WLAN1 0x18500000
1281 +#define AR5312_ENET0 0x18100000
1282 +#define AR5312_ENET1 0x18200000
1283 +#define AR5312_SDRAMCTL 0x18300000
1284 +#define AR5312_FLASHCTL 0x18400000
1285 +#define AR5312_APBBASE 0x1c000000
1286 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1287 +#define AR5312_FLASH 0x1e000000
1288 +
1289 +/*
1290 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1291 + * should be considered available. The AR5312 supports 2 enet MACS,
1292 + * even though many reference boards only actually use 1 of them
1293 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1294 + * The AR2312 supports 1 enet MAC.
1295 + */
1296 +#define AR5312_NUM_ENET_MAC 2
1297 +
1298 +/*
1299 + * Need these defines to determine true number of ethernet MACs
1300 + */
1301 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1302 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1303 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1304 +
1305 +/* MII registers offset inside Ethernet MMR region */
1306 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1307 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1308 +
1309 +/*
1310 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1311 + * should be considered available.
1312 + */
1313 +#define AR5312_NUM_WMAC 2
1314 +
1315 +/* Reset/Timer Block Address Map */
1316 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1317 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1318 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1319 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1320 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1321 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1322 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1323 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1324 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1325 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1326 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1327 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1328 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1329 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1330 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1331 +
1332 +/* AR5312_WD_CTRL register bit field definitions */
1333 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1334 +#define AR5312_WD_CTRL_NMI 0x0001
1335 +#define AR5312_WD_CTRL_RESET 0x0002
1336 +
1337 +/* AR5312_ISR register bit field definitions */
1338 +#define AR5312_ISR_TIMER 0x0001
1339 +#define AR5312_ISR_AHBPROC 0x0002
1340 +#define AR5312_ISR_AHBDMA 0x0004
1341 +#define AR5312_ISR_GPIO 0x0008
1342 +#define AR5312_ISR_UART0 0x0010
1343 +#define AR5312_ISR_UART0DMA 0x0020
1344 +#define AR5312_ISR_WD 0x0040
1345 +#define AR5312_ISR_LOCAL 0x0080
1346 +
1347 +/* AR5312_RESET register bit field definitions */
1348 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1349 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1350 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1351 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1352 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1353 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1354 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1355 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1356 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1357 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1358 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1359 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1360 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1361 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1362 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1363 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1364 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1365 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1366 +
1367 +#define AR5312_RESET_WMAC0_BITS \
1368 + (AR5312_RESET_WLAN0 |\
1369 + AR5312_RESET_WARM_WLAN0_MAC |\
1370 + AR5312_RESET_WARM_WLAN0_BB)
1371 +
1372 +#define AR5312_RESET_WMAC1_BITS \
1373 + (AR5312_RESET_WLAN1 |\
1374 + AR5312_RESET_WARM_WLAN1_MAC |\
1375 + AR5312_RESET_WARM_WLAN1_BB)
1376 +
1377 +/* AR5312_CLOCKCTL1 register bit field definitions */
1378 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1379 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1380 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1381 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1382 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1383 +
1384 +/* Valid for AR5312 and AR2312 */
1385 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1386 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1387 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1388 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1389 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1390 +
1391 +/* Valid for AR2313 */
1392 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1393 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1394 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1395 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1396 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1397 +
1398 +/* AR5312_ENABLE register bit field definitions */
1399 +#define AR5312_ENABLE_WLAN0 0x0001
1400 +#define AR5312_ENABLE_ENET0 0x0002
1401 +#define AR5312_ENABLE_ENET1 0x0004
1402 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1403 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1404 +#define AR5312_ENABLE_WLAN1 \
1405 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1406 + AR5312_ENABLE_WLAN1_DMA)
1407 +
1408 +/* AR5312_REV register bit field definitions */
1409 +#define AR5312_REV_WMAC_MAJ 0xf000
1410 +#define AR5312_REV_WMAC_MAJ_S 12
1411 +#define AR5312_REV_WMAC_MIN 0x0f00
1412 +#define AR5312_REV_WMAC_MIN_S 8
1413 +#define AR5312_REV_MAJ 0x00f0
1414 +#define AR5312_REV_MAJ_S 4
1415 +#define AR5312_REV_MIN 0x000f
1416 +#define AR5312_REV_MIN_S 0
1417 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1418 +
1419 +/* Major revision numbers, bits 7..4 of Revision ID register */
1420 +#define AR5312_REV_MAJ_AR5312 0x4
1421 +#define AR5312_REV_MAJ_AR2313 0x5
1422 +
1423 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1424 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1425 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1426 +
1427 +/* AR5312_FLASHCTL register bit field definitions */
1428 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1429 +#define FLASHCTL_IDCY_S 0
1430 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1431 +#define FLASHCTL_WST1_S 5
1432 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1433 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1434 +#define FLASHCTL_WST2_S 11
1435 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1436 +#define FLASHCTL_AC_S 16
1437 +#define FLASHCTL_AC_128K 0x00000000
1438 +#define FLASHCTL_AC_256K 0x00010000
1439 +#define FLASHCTL_AC_512K 0x00020000
1440 +#define FLASHCTL_AC_1M 0x00030000
1441 +#define FLASHCTL_AC_2M 0x00040000
1442 +#define FLASHCTL_AC_4M 0x00050000
1443 +#define FLASHCTL_AC_8M 0x00060000
1444 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1445 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1446 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1447 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1448 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1449 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1450 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1451 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1452 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1453 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1454 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1455 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1456 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1457 +
1458 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1459 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1460 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1461 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1462 +
1463 +/* ARM SDRAM Controller -- just enough to determine memory size */
1464 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1465 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1466 +#define MEM_CFG1_AC0_S 8
1467 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1468 +#define MEM_CFG1_AC1_S 12
1469 +
1470 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1471 +
1472 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1473 --- /dev/null
1474 +++ b/arch/mips/ath25/ar5312.c
1475 @@ -0,0 +1,449 @@
1476 +/*
1477 + * This file is subject to the terms and conditions of the GNU General Public
1478 + * License. See the file "COPYING" in the main directory of this archive
1479 + * for more details.
1480 + *
1481 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1482 + * Copyright (C) 2006 FON Technology, SL.
1483 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1484 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1485 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1486 + */
1487 +
1488 +/*
1489 + * Platform devices for Atheros SoCs
1490 + */
1491 +
1492 +#include <generated/autoconf.h>
1493 +#include <linux/init.h>
1494 +#include <linux/module.h>
1495 +#include <linux/types.h>
1496 +#include <linux/string.h>
1497 +#include <linux/mtd/physmap.h>
1498 +#include <linux/platform_device.h>
1499 +#include <linux/kernel.h>
1500 +#include <linux/reboot.h>
1501 +#include <linux/leds.h>
1502 +#include <linux/gpio.h>
1503 +#include <asm/bootinfo.h>
1504 +#include <asm/reboot.h>
1505 +#include <asm/time.h>
1506 +#include <linux/irq.h>
1507 +#include <linux/io.h>
1508 +
1509 +#include <ath25_platform.h>
1510 +#include <ar5312_regs.h>
1511 +#include <ar231x.h>
1512 +#include "devices.h"
1513 +#include "ar5312.h"
1514 +
1515 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1516 +{
1517 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1518 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1519 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1520 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1521 +
1522 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1523 + proc_addr, proc1, dma_addr, dma1);
1524 +
1525 + machine_restart("AHB error"); /* Catastrophic failure */
1526 + return IRQ_HANDLED;
1527 +}
1528 +
1529 +static struct irqaction ar5312_ahb_err_interrupt = {
1530 + .handler = ar5312_ahb_err_handler,
1531 + .name = "ar5312-ahb-error",
1532 +};
1533 +
1534 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1535 +{
1536 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1537 + ar231x_read_reg(AR5312_IMR);
1538 +
1539 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1540 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1541 + (void)ar231x_read_reg(AR5312_TIMER);
1542 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1543 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1544 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1545 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1546 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1547 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1548 + else
1549 + spurious_interrupt();
1550 +}
1551 +
1552 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1553 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1554 +{
1555 + unsigned int imr;
1556 +
1557 + imr = ar231x_read_reg(AR5312_IMR);
1558 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1559 + ar231x_write_reg(AR5312_IMR, imr);
1560 +}
1561 +
1562 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1563 +static void ar5312_misc_irq_mask(struct irq_data *d)
1564 +{
1565 + unsigned int imr;
1566 +
1567 + imr = ar231x_read_reg(AR5312_IMR);
1568 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1569 + ar231x_write_reg(AR5312_IMR, imr);
1570 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1571 +}
1572 +
1573 +static struct irq_chip ar5312_misc_irq_chip = {
1574 + .name = "ar5312-misc",
1575 + .irq_unmask = ar5312_misc_irq_unmask,
1576 + .irq_mask = ar5312_misc_irq_mask,
1577 +};
1578 +
1579 +static void ar5312_irq_dispatch(void)
1580 +{
1581 + int pending = read_c0_status() & read_c0_cause();
1582 +
1583 + if (pending & CAUSEF_IP2)
1584 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1585 + else if (pending & CAUSEF_IP3)
1586 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1587 + else if (pending & CAUSEF_IP4)
1588 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1589 + else if (pending & CAUSEF_IP5)
1590 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1591 + else if (pending & CAUSEF_IP6)
1592 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1593 + else if (pending & CAUSEF_IP7)
1594 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1595 + else
1596 + spurious_interrupt();
1597 +}
1598 +
1599 +void __init ar5312_arch_init_irq(void)
1600 +{
1601 + int i;
1602 +
1603 + ath25_irq_dispatch = ar5312_irq_dispatch;
1604 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1605 + int irq = AR231X_MISC_IRQ_BASE + i;
1606 +
1607 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1608 + handle_level_irq);
1609 + }
1610 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
1611 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1612 +}
1613 +
1614 +static void ar5312_device_reset_set(u32 mask)
1615 +{
1616 + u32 val;
1617 +
1618 + val = ar231x_read_reg(AR5312_RESET);
1619 + ar231x_write_reg(AR5312_RESET, val | mask);
1620 +}
1621 +
1622 +static void ar5312_device_reset_clear(u32 mask)
1623 +{
1624 + u32 val;
1625 +
1626 + val = ar231x_read_reg(AR5312_RESET);
1627 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1628 +}
1629 +
1630 +static struct physmap_flash_data ar5312_flash_data = {
1631 + .width = 2,
1632 +};
1633 +
1634 +static struct resource ar5312_flash_resource = {
1635 + .start = AR5312_FLASH,
1636 + .end = AR5312_FLASH + 0x800000 - 1,
1637 + .flags = IORESOURCE_MEM,
1638 +};
1639 +
1640 +static struct ar231x_eth ar5312_eth0_data = {
1641 + .reset_set = ar5312_device_reset_set,
1642 + .reset_clear = ar5312_device_reset_clear,
1643 + .reset_mac = AR5312_RESET_ENET0,
1644 + .reset_phy = AR5312_RESET_EPHY0,
1645 +};
1646 +
1647 +static struct ar231x_eth ar5312_eth1_data = {
1648 + .reset_set = ar5312_device_reset_set,
1649 + .reset_clear = ar5312_device_reset_clear,
1650 + .reset_mac = AR5312_RESET_ENET1,
1651 + .reset_phy = AR5312_RESET_EPHY1,
1652 +};
1653 +
1654 +static struct platform_device ar5312_physmap_flash = {
1655 + .name = "physmap-flash",
1656 + .id = 0,
1657 + .dev.platform_data = &ar5312_flash_data,
1658 + .resource = &ar5312_flash_resource,
1659 + .num_resources = 1,
1660 +};
1661 +
1662 +#ifdef CONFIG_LEDS_GPIO
1663 +static struct gpio_led ar5312_leds[] = {
1664 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1665 +};
1666 +
1667 +static const struct gpio_led_platform_data ar5312_led_data = {
1668 + .num_leds = ARRAY_SIZE(ar5312_leds),
1669 + .leds = (void *)ar5312_leds,
1670 +};
1671 +
1672 +static struct platform_device ar5312_gpio_leds = {
1673 + .name = "leds-gpio",
1674 + .id = -1,
1675 + .dev.platform_data = (void *)&ar5312_led_data,
1676 +};
1677 +#endif
1678 +
1679 +/*
1680 + * NB: This mapping size is larger than the actual flash size,
1681 + * but this shouldn't be a problem here, because the flash
1682 + * will simply be mapped multiple times.
1683 + */
1684 +static char __init *ar5312_flash_limit(void)
1685 +{
1686 + u32 ctl;
1687 + /*
1688 + * Configure flash bank 0.
1689 + * Assume 8M window size. Flash will be aliased if it's smaller
1690 + */
1691 + ctl = FLASHCTL_E |
1692 + FLASHCTL_AC_8M |
1693 + FLASHCTL_RBLE |
1694 + (0x01 << FLASHCTL_IDCY_S) |
1695 + (0x07 << FLASHCTL_WST1_S) |
1696 + (0x07 << FLASHCTL_WST2_S) |
1697 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1698 +
1699 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1700 +
1701 + /* Disable other flash banks */
1702 + ar231x_write_reg(AR5312_FLASHCTL1,
1703 + ar231x_read_reg(AR5312_FLASHCTL1) &
1704 + ~(FLASHCTL_E | FLASHCTL_AC));
1705 +
1706 + ar231x_write_reg(AR5312_FLASHCTL2,
1707 + ar231x_read_reg(AR5312_FLASHCTL2) &
1708 + ~(FLASHCTL_E | FLASHCTL_AC));
1709 +
1710 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1711 +}
1712 +
1713 +void __init ar5312_init_devices(void)
1714 +{
1715 + struct ath25_boarddata *config;
1716 + u32 fctl = 0;
1717 + u8 *c;
1718 +
1719 + /* Locate board/radio config data */
1720 + ath25_find_config(ar5312_flash_limit());
1721 + config = ath25_board.config;
1722 +
1723 + /* AR2313 has CPU minor rev. 10 */
1724 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1725 + ath25_soc = ATH25_SOC_AR2313;
1726 +
1727 + /* AR2312 shares the same Silicon ID as AR5312 */
1728 + else if (config->flags & BD_ISCASPER)
1729 + ath25_soc = ATH25_SOC_AR2312;
1730 +
1731 + /* Everything else is probably AR5312 or compatible */
1732 + else
1733 + ath25_soc = ATH25_SOC_AR5312;
1734 +
1735 + /* fixup flash width */
1736 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1737 + switch (fctl) {
1738 + case FLASHCTL_MW16:
1739 + ar5312_flash_data.width = 2;
1740 + break;
1741 + case FLASHCTL_MW8:
1742 + default:
1743 + ar5312_flash_data.width = 1;
1744 + break;
1745 + }
1746 +
1747 + platform_device_register(&ar5312_physmap_flash);
1748 +
1749 +#ifdef CONFIG_LEDS_GPIO
1750 + ar5312_leds[0].gpio = config->sys_led_gpio;
1751 + platform_device_register(&ar5312_gpio_leds);
1752 +#endif
1753 +
1754 + /* Fix up MAC addresses if necessary */
1755 + if (is_broadcast_ether_addr(config->enet0_mac))
1756 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1757 +
1758 + /* If ENET0 and ENET1 have the same mac address,
1759 + * increment the one from ENET1 */
1760 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1761 + c = config->enet1_mac + 5;
1762 + while ((c >= config->enet1_mac) && !(++(*c)))
1763 + c--;
1764 + }
1765 +
1766 + switch (ath25_soc) {
1767 + case ATH25_SOC_AR5312:
1768 + ar5312_eth0_data.macaddr = config->enet0_mac;
1769 + ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1770 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1771 + &ar5312_eth0_data);
1772 +
1773 + ar5312_eth1_data.macaddr = config->enet1_mac;
1774 + ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1775 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1776 + &ar5312_eth1_data);
1777 +
1778 + if (!ath25_board.radio)
1779 + return;
1780 +
1781 + if (!(config->flags & BD_WLAN0))
1782 + break;
1783 +
1784 + ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1785 + break;
1786 + /*
1787 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1788 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1789 + */
1790 + case ATH25_SOC_AR2312:
1791 + case ATH25_SOC_AR2313:
1792 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1793 + ar5312_eth1_data.macaddr = config->enet0_mac;
1794 + ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1795 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1796 + &ar5312_eth1_data);
1797 +
1798 + if (!ath25_board.radio)
1799 + return;
1800 + break;
1801 + default:
1802 + break;
1803 + }
1804 +
1805 + if (config->flags & BD_WLAN1)
1806 + ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1807 +}
1808 +
1809 +static void ar5312_restart(char *command)
1810 +{
1811 + /* reset the system */
1812 + local_irq_disable();
1813 + while (1)
1814 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1815 +}
1816 +
1817 +/*
1818 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1819 + * to determine the predevisor value.
1820 + */
1821 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1822 +
1823 +static unsigned __init ar5312_cpu_frequency(void)
1824 +{
1825 + unsigned int scratch;
1826 + unsigned int predivide_mask, predivide_shift;
1827 + unsigned int multiplier_mask, multiplier_shift;
1828 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1829 + unsigned int doubler_mask;
1830 + u16 devid;
1831 +
1832 + /* Trust the bootrom's idea of cpu frequency. */
1833 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1834 + if (scratch)
1835 + return scratch;
1836 +
1837 + devid = ar231x_read_reg(AR5312_REV);
1838 + devid &= AR5312_REV_MAJ;
1839 + devid >>= AR5312_REV_MAJ_S;
1840 + if (devid == AR5312_REV_MAJ_AR2313) {
1841 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1842 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1843 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1844 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1845 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1846 + } else { /* AR5312 and AR2312 */
1847 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1848 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1849 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1850 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1851 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1852 + }
1853 +
1854 + /*
1855 + * Clocking is derived from a fixed 40MHz input clock.
1856 + *
1857 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1858 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1859 + * flash, Timer, Watchdog Timer)
1860 + *
1861 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1862 + *
1863 + * So, for example, with a PLL multiplier of 5, we have
1864 + *
1865 + * cpu_freq = 200MHz
1866 + * sys_freq = 50MHz
1867 + * cnt_freq = 100MHz
1868 + *
1869 + * We compute the CPU frequency, based on PLL settings.
1870 + */
1871 +
1872 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1873 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1874 + predivisor = clockctl1_predivide_table[predivide_select];
1875 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1876 +
1877 + if (clock_ctl1 & doubler_mask)
1878 + multiplier = multiplier << 1;
1879 +
1880 + return (40000000 / predivisor) * multiplier;
1881 +}
1882 +
1883 +static inline unsigned ar5312_sys_frequency(void)
1884 +{
1885 + return ar5312_cpu_frequency() / 4;
1886 +}
1887 +
1888 +void __init ar5312_plat_time_init(void)
1889 +{
1890 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1891 +}
1892 +
1893 +void __init ar5312_plat_mem_setup(void)
1894 +{
1895 + u32 memsize, memcfg, bank0AC, bank1AC;
1896 + u32 devid;
1897 +
1898 + /* Detect memory size */
1899 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1900 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1901 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1902 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1903 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1904 + memsize <<= 20;
1905 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1906 +
1907 + devid = ar231x_read_reg(AR5312_REV);
1908 + devid >>= AR5312_REV_WMAC_MIN_S;
1909 + devid &= AR5312_REV_CHIP;
1910 + ath25_board.devid = (u16)devid;
1911 +
1912 + /* Clear any lingering AHB errors */
1913 + ar231x_read_reg(AR5312_PROCADDR);
1914 + ar231x_read_reg(AR5312_DMAADDR);
1915 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1916 +
1917 + _machine_restart = ar5312_restart;
1918 +}
1919 +
1920 +void __init ar5312_arch_init(void)
1921 +{
1922 + ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1923 + ar5312_sys_frequency());
1924 +}
1925 --- /dev/null
1926 +++ b/arch/mips/ath25/ar2315.c
1927 @@ -0,0 +1,401 @@
1928 +/*
1929 + * This file is subject to the terms and conditions of the GNU General Public
1930 + * License. See the file "COPYING" in the main directory of this archive
1931 + * for more details.
1932 + *
1933 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1934 + * Copyright (C) 2006 FON Technology, SL.
1935 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1936 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1937 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1938 + */
1939 +
1940 +/*
1941 + * Platform devices for Atheros SoCs
1942 + */
1943 +
1944 +#include <generated/autoconf.h>
1945 +#include <linux/init.h>
1946 +#include <linux/module.h>
1947 +#include <linux/types.h>
1948 +#include <linux/string.h>
1949 +#include <linux/platform_device.h>
1950 +#include <linux/kernel.h>
1951 +#include <linux/reboot.h>
1952 +#include <linux/delay.h>
1953 +#include <linux/leds.h>
1954 +#include <linux/gpio.h>
1955 +#include <asm/bootinfo.h>
1956 +#include <asm/reboot.h>
1957 +#include <asm/time.h>
1958 +#include <linux/irq.h>
1959 +#include <linux/io.h>
1960 +
1961 +#include <ath25_platform.h>
1962 +#include <ar2315_regs.h>
1963 +#include <ar231x.h>
1964 +#include "devices.h"
1965 +#include "ar2315.h"
1966 +
1967 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1968 +{
1969 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
1970 + ar231x_read_reg(AR2315_AHB_ERR1);
1971 +
1972 + pr_emerg("AHB fatal error\n");
1973 + machine_restart("AHB error"); /* Catastrophic failure */
1974 +
1975 + return IRQ_HANDLED;
1976 +}
1977 +
1978 +static struct irqaction ar2315_ahb_err_interrupt = {
1979 + .handler = ar2315_ahb_err_handler,
1980 + .name = "ar2315-ahb-error",
1981 +};
1982 +
1983 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1984 +{
1985 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
1986 + ar231x_read_reg(AR2315_IMR);
1987 +
1988 + if (misc_intr & AR2315_ISR_SPI)
1989 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
1990 + else if (misc_intr & AR2315_ISR_TIMER)
1991 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
1992 + else if (misc_intr & AR2315_ISR_AHB)
1993 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
1994 + else if (misc_intr & AR2315_ISR_GPIO) {
1995 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
1996 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
1997 + } else if (misc_intr & AR2315_ISR_UART0)
1998 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
1999 + else if (misc_intr & AR2315_ISR_WD) {
2000 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2001 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
2002 + } else
2003 + spurious_interrupt();
2004 +}
2005 +
2006 +static void ar2315_misc_irq_unmask(struct irq_data *d)
2007 +{
2008 + unsigned int imr;
2009 +
2010 + imr = ar231x_read_reg(AR2315_IMR);
2011 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
2012 + ar231x_write_reg(AR2315_IMR, imr);
2013 +}
2014 +
2015 +static void ar2315_misc_irq_mask(struct irq_data *d)
2016 +{
2017 + unsigned int imr;
2018 +
2019 + imr = ar231x_read_reg(AR2315_IMR);
2020 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
2021 + ar231x_write_reg(AR2315_IMR, imr);
2022 +}
2023 +
2024 +static struct irq_chip ar2315_misc_irq_chip = {
2025 + .name = "ar2315-misc",
2026 + .irq_unmask = ar2315_misc_irq_unmask,
2027 + .irq_mask = ar2315_misc_irq_mask,
2028 +};
2029 +
2030 +/*
2031 + * Called when an interrupt is received, this function
2032 + * determines exactly which interrupt it was, and it
2033 + * invokes the appropriate handler.
2034 + *
2035 + * Implicitly, we also define interrupt priority by
2036 + * choosing which to dispatch first.
2037 + */
2038 +static void ar2315_irq_dispatch(void)
2039 +{
2040 + int pending = read_c0_status() & read_c0_cause();
2041 +
2042 + if (pending & CAUSEF_IP3)
2043 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2044 + else if (pending & CAUSEF_IP4)
2045 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2046 + else if (pending & CAUSEF_IP2)
2047 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2048 + else if (pending & CAUSEF_IP7)
2049 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2050 + else
2051 + spurious_interrupt();
2052 +}
2053 +
2054 +void __init ar2315_arch_init_irq(void)
2055 +{
2056 + int i;
2057 +
2058 + ath25_irq_dispatch = ar2315_irq_dispatch;
2059 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2060 + int irq = AR231X_MISC_IRQ_BASE + i;
2061 +
2062 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2063 + handle_level_irq);
2064 + }
2065 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
2066 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2067 +}
2068 +
2069 +static void ar2315_device_reset_set(u32 mask)
2070 +{
2071 + u32 val;
2072 +
2073 + val = ar231x_read_reg(AR2315_RESET);
2074 + ar231x_write_reg(AR2315_RESET, val | mask);
2075 +}
2076 +
2077 +static void ar2315_device_reset_clear(u32 mask)
2078 +{
2079 + u32 val;
2080 +
2081 + val = ar231x_read_reg(AR2315_RESET);
2082 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2083 +}
2084 +
2085 +static struct ar231x_eth ar2315_eth_data = {
2086 + .reset_set = ar2315_device_reset_set,
2087 + .reset_clear = ar2315_device_reset_clear,
2088 + .reset_mac = AR2315_RESET_ENET0,
2089 + .reset_phy = AR2315_RESET_EPHY0,
2090 +};
2091 +
2092 +static struct resource ar2315_spiflash_res[] = {
2093 + {
2094 + .name = "spiflash_read",
2095 + .flags = IORESOURCE_MEM,
2096 + .start = AR2315_SPI_READ,
2097 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2098 + },
2099 + {
2100 + .name = "spiflash_mmr",
2101 + .flags = IORESOURCE_MEM,
2102 + .start = AR2315_SPI_MMR,
2103 + .end = AR2315_SPI_MMR + 12 - 1,
2104 + },
2105 +};
2106 +
2107 +static struct platform_device ar2315_spiflash = {
2108 + .id = 0,
2109 + .name = "ar2315-spiflash",
2110 + .resource = ar2315_spiflash_res,
2111 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2112 +};
2113 +
2114 +static struct resource ar2315_wdt_res[] = {
2115 + {
2116 + .flags = IORESOURCE_MEM,
2117 + .start = AR2315_WD,
2118 + .end = AR2315_WD + 8 - 1,
2119 + },
2120 + {
2121 + .flags = IORESOURCE_IRQ,
2122 + .start = AR2315_MISC_IRQ_WATCHDOG,
2123 + .end = AR2315_MISC_IRQ_WATCHDOG,
2124 + }
2125 +};
2126 +
2127 +static struct platform_device ar2315_wdt = {
2128 + .id = 0,
2129 + .name = "ar2315-wdt",
2130 + .resource = ar2315_wdt_res,
2131 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2132 +};
2133 +
2134 +/*
2135 + * NB: We use mapping size that is larger than the actual flash size,
2136 + * but this shouldn't be a problem here, because the flash will simply
2137 + * be mapped multiple times.
2138 + */
2139 +static u8 __init *ar2315_flash_limit(void)
2140 +{
2141 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2142 +}
2143 +
2144 +#ifdef CONFIG_LEDS_GPIO
2145 +static struct gpio_led ar2315_leds[6];
2146 +static struct gpio_led_platform_data ar2315_led_data = {
2147 + .leds = (void *)ar2315_leds,
2148 +};
2149 +
2150 +static struct platform_device ar2315_gpio_leds = {
2151 + .name = "leds-gpio",
2152 + .id = -1,
2153 + .dev = {
2154 + .platform_data = (void *)&ar2315_led_data,
2155 + }
2156 +};
2157 +
2158 +static void __init ar2315_init_gpio_leds(void)
2159 +{
2160 + static char led_names[6][6];
2161 + int i, led = 0;
2162 +
2163 + ar2315_led_data.num_leds = 0;
2164 + for (i = 1; i < 8; i++) {
2165 + if ((i == AR2315_RESET_GPIO) ||
2166 + (i == ath25_board.config->reset_config_gpio))
2167 + continue;
2168 +
2169 + if (i == ath25_board.config->sys_led_gpio)
2170 + strcpy(led_names[led], "wlan");
2171 + else
2172 + sprintf(led_names[led], "gpio%d", i);
2173 +
2174 + ar2315_leds[led].name = led_names[led];
2175 + ar2315_leds[led].gpio = i;
2176 + ar2315_leds[led].active_low = 0;
2177 + led++;
2178 + }
2179 + ar2315_led_data.num_leds = led;
2180 + platform_device_register(&ar2315_gpio_leds);
2181 +}
2182 +#else
2183 +static inline void ar2315_init_gpio_leds(void)
2184 +{
2185 +}
2186 +#endif
2187 +
2188 +void __init ar2315_init_devices(void)
2189 +{
2190 + /* Find board configuration */
2191 + ath25_find_config(ar2315_flash_limit());
2192 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
2193 +
2194 + ar2315_init_gpio_leds();
2195 + platform_device_register(&ar2315_wdt);
2196 + platform_device_register(&ar2315_spiflash);
2197 + ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2198 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2199 + ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2200 +}
2201 +
2202 +static void ar2315_restart(char *command)
2203 +{
2204 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2205 +
2206 + local_irq_disable();
2207 +
2208 + /* try reset the system via reset control */
2209 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2210 +
2211 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2212 + * a workaround. Give it some time to attempt a gpio based hardware
2213 + * reset (atheros reference design workaround) */
2214 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2215 + mdelay(100);
2216 +
2217 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2218 + * workaround. Attempt to jump to the mips reset location -
2219 + * the boot loader itself might be able to recover the system */
2220 + mips_reset_vec();
2221 +}
2222 +
2223 +/*
2224 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2225 + * to determine the predevisor value.
2226 + */
2227 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2228 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2229 +
2230 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
2231 +{
2232 + unsigned int pllc_ctrl, cpu_div;
2233 + unsigned int pllc_out, refdiv, fdiv, divby2;
2234 + unsigned int clk_div;
2235 +
2236 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2237 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2238 + refdiv = clockctl1_predivide_table[refdiv];
2239 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2240 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2241 + divby2 += 1;
2242 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2243 +
2244 + /* clkm input selected */
2245 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2246 + case 0:
2247 + case 1:
2248 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2249 + PLLC_CLKM_DIV_S];
2250 + break;
2251 + case 2:
2252 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2253 + PLLC_CLKC_DIV_S];
2254 + break;
2255 + default:
2256 + pllc_out = 40000000;
2257 + clk_div = 1;
2258 + break;
2259 + }
2260 +
2261 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2262 + cpu_div = cpu_div * 2 ?: 1;
2263 +
2264 + return pllc_out / (clk_div * cpu_div);
2265 +}
2266 +
2267 +static inline unsigned ar2315_cpu_frequency(void)
2268 +{
2269 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2270 +}
2271 +
2272 +static inline unsigned ar2315_apb_frequency(void)
2273 +{
2274 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2275 +}
2276 +
2277 +void __init ar2315_plat_time_init(void)
2278 +{
2279 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2280 +}
2281 +
2282 +void __init ar2315_plat_mem_setup(void)
2283 +{
2284 + u32 memsize, memcfg;
2285 + u32 devid;
2286 + u32 config;
2287 +
2288 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2289 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2290 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2291 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2292 + memsize <<= 3;
2293 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2294 +
2295 + /* Detect the hardware based on the device ID */
2296 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2297 + switch (devid) {
2298 + case 0x91: /* Need to check */
2299 + ath25_soc = ATH25_SOC_AR2318;
2300 + break;
2301 + case 0x90:
2302 + ath25_soc = ATH25_SOC_AR2317;
2303 + break;
2304 + case 0x87:
2305 + ath25_soc = ATH25_SOC_AR2316;
2306 + break;
2307 + case 0x86:
2308 + default:
2309 + ath25_soc = ATH25_SOC_AR2315;
2310 + break;
2311 + }
2312 + ath25_board.devid = devid;
2313 +
2314 + /* Clear any lingering AHB errors */
2315 + config = read_c0_config();
2316 + write_c0_config(config & ~0x3);
2317 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2318 + ar231x_read_reg(AR2315_AHB_ERR1);
2319 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2320 +
2321 + _machine_restart = ar2315_restart;
2322 +}
2323 +
2324 +void __init ar2315_arch_init(void)
2325 +{
2326 + ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2327 + ar2315_apb_frequency());
2328 +}
2329 --- /dev/null
2330 +++ b/arch/mips/ath25/ar2315.h
2331 @@ -0,0 +1,36 @@
2332 +#ifndef __AR2315_H
2333 +#define __AR2315_H
2334 +
2335 +#ifdef CONFIG_SOC_AR2315
2336 +
2337 +void ar2315_arch_init_irq(void);
2338 +void ar2315_init_devices(void);
2339 +void ar2315_plat_time_init(void);
2340 +void ar2315_plat_mem_setup(void);
2341 +void ar2315_arch_init(void);
2342 +
2343 +#else
2344 +
2345 +static inline void ar2315_arch_init_irq(void)
2346 +{
2347 +}
2348 +
2349 +static inline void ar2315_init_devices(void)
2350 +{
2351 +}
2352 +
2353 +static inline void ar2315_plat_time_init(void)
2354 +{
2355 +}
2356 +
2357 +static inline void ar2315_plat_mem_setup(void)
2358 +{
2359 +}
2360 +
2361 +static inline void ar2315_arch_init(void)
2362 +{
2363 +}
2364 +
2365 +#endif
2366 +
2367 +#endif
2368 --- /dev/null
2369 +++ b/arch/mips/ath25/ar5312.h
2370 @@ -0,0 +1,36 @@
2371 +#ifndef __AR5312_H
2372 +#define __AR5312_H
2373 +
2374 +#ifdef CONFIG_SOC_AR5312
2375 +
2376 +void ar5312_arch_init_irq(void);
2377 +void ar5312_init_devices(void);
2378 +void ar5312_plat_time_init(void);
2379 +void ar5312_plat_mem_setup(void);
2380 +void ar5312_arch_init(void);
2381 +
2382 +#else
2383 +
2384 +static inline void ar5312_arch_init_irq(void)
2385 +{
2386 +}
2387 +
2388 +static inline void ar5312_init_devices(void)
2389 +{
2390 +}
2391 +
2392 +static inline void ar5312_plat_time_init(void)
2393 +{
2394 +}
2395 +
2396 +static inline void ar5312_plat_mem_setup(void)
2397 +{
2398 +}
2399 +
2400 +static inline void ar5312_arch_init(void)
2401 +{
2402 +}
2403 +
2404 +#endif
2405 +
2406 +#endif
2407 --- /dev/null
2408 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2409 @@ -0,0 +1,38 @@
2410 +#ifndef __ASM_MACH_ATH25_AR231X_H
2411 +#define __ASM_MACH_ATH25_AR231X_H
2412 +
2413 +#include <linux/types.h>
2414 +#include <linux/io.h>
2415 +
2416 +#define AR231X_MISC_IRQ_BASE 0x20
2417 +#define AR231X_GPIO_IRQ_BASE 0x30
2418 +
2419 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2420 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2421 +
2422 +static inline u32
2423 +ar231x_read_reg(u32 reg)
2424 +{
2425 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2426 +}
2427 +
2428 +static inline void
2429 +ar231x_write_reg(u32 reg, u32 val)
2430 +{
2431 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2432 +}
2433 +
2434 +static inline u32
2435 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2436 +{
2437 + u32 ret;
2438 +
2439 + ret = ar231x_read_reg(reg);
2440 + ret &= ~mask;
2441 + ret |= val;
2442 + ar231x_write_reg(reg, ret);
2443 +
2444 + return ret;
2445 +}
2446 +
2447 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2448 --- /dev/null
2449 +++ b/arch/mips/ath25/devices.h
2450 @@ -0,0 +1,39 @@
2451 +#ifndef __ATH25_DEVICES_H
2452 +#define __ATH25_DEVICES_H
2453 +
2454 +enum ath25_soc_type {
2455 + /* handled by ar5312.c */
2456 + ATH25_SOC_AR2312,
2457 + ATH25_SOC_AR2313,
2458 + ATH25_SOC_AR5312,
2459 +
2460 + /* handled by ar2315.c */
2461 + ATH25_SOC_AR2315,
2462 + ATH25_SOC_AR2316,
2463 + ATH25_SOC_AR2317,
2464 + ATH25_SOC_AR2318,
2465 +
2466 + ATH25_SOC_UNKNOWN
2467 +};
2468 +
2469 +extern enum ath25_soc_type ath25_soc;
2470 +extern struct ar231x_board_config ath25_board;
2471 +extern void (*ath25_irq_dispatch)(void);
2472 +
2473 +int ath25_find_config(u8 *flash_limit);
2474 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2475 + int irq, void *pdata);
2476 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2477 +int ath25_add_wmac(int nr, u32 base, int irq);
2478 +
2479 +static inline bool is_ar2315(void)
2480 +{
2481 + return (current_cpu_data.cputype == CPU_4KEC);
2482 +}
2483 +
2484 +static inline bool is_ar5312(void)
2485 +{
2486 + return !is_ar2315();
2487 +}
2488 +
2489 +#endif
2490 --- /dev/null
2491 +++ b/arch/mips/ath25/devices.c
2492 @@ -0,0 +1,192 @@
2493 +#include <linux/kernel.h>
2494 +#include <linux/init.h>
2495 +#include <linux/serial.h>
2496 +#include <linux/serial_core.h>
2497 +#include <linux/serial_8250.h>
2498 +#include <linux/platform_device.h>
2499 +#include <asm/bootinfo.h>
2500 +
2501 +#include <ath25_platform.h>
2502 +#include <ar231x.h>
2503 +#include "devices.h"
2504 +#include "ar5312.h"
2505 +#include "ar2315.h"
2506 +
2507 +struct ar231x_board_config ath25_board;
2508 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2509 +
2510 +static struct resource ath25_eth0_res[] = {
2511 + {
2512 + .name = "eth0_membase",
2513 + .flags = IORESOURCE_MEM,
2514 + },
2515 + {
2516 + .name = "eth0_mii",
2517 + .flags = IORESOURCE_MEM,
2518 + },
2519 + {
2520 + .name = "eth0_irq",
2521 + .flags = IORESOURCE_IRQ,
2522 + }
2523 +};
2524 +
2525 +static struct resource ath25_eth1_res[] = {
2526 + {
2527 + .name = "eth1_membase",
2528 + .flags = IORESOURCE_MEM,
2529 + },
2530 + {
2531 + .name = "eth1_mii",
2532 + .flags = IORESOURCE_MEM,
2533 + },
2534 + {
2535 + .name = "eth1_irq",
2536 + .flags = IORESOURCE_IRQ,
2537 + }
2538 +};
2539 +
2540 +static struct platform_device ath25_eth[] = {
2541 + {
2542 + .id = 0,
2543 + .name = "ar231x-eth",
2544 + .resource = ath25_eth0_res,
2545 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
2546 + },
2547 + {
2548 + .id = 1,
2549 + .name = "ar231x-eth",
2550 + .resource = ath25_eth1_res,
2551 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
2552 + }
2553 +};
2554 +
2555 +static struct resource ath25_wmac0_res[] = {
2556 + {
2557 + .name = "wmac0_membase",
2558 + .flags = IORESOURCE_MEM,
2559 + },
2560 + {
2561 + .name = "wmac0_irq",
2562 + .flags = IORESOURCE_IRQ,
2563 + }
2564 +};
2565 +
2566 +static struct resource ath25_wmac1_res[] = {
2567 + {
2568 + .name = "wmac1_membase",
2569 + .flags = IORESOURCE_MEM,
2570 + },
2571 + {
2572 + .name = "wmac1_irq",
2573 + .flags = IORESOURCE_IRQ,
2574 + }
2575 +};
2576 +
2577 +static struct platform_device ath25_wmac[] = {
2578 + {
2579 + .id = 0,
2580 + .name = "ar231x-wmac",
2581 + .resource = ath25_wmac0_res,
2582 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2583 + .dev.platform_data = &ath25_board,
2584 + },
2585 + {
2586 + .id = 1,
2587 + .name = "ar231x-wmac",
2588 + .resource = ath25_wmac1_res,
2589 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2590 + .dev.platform_data = &ath25_board,
2591 + },
2592 +};
2593 +
2594 +static const char * const soc_type_strings[] = {
2595 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2596 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2597 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2598 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2599 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2600 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2601 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2602 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2603 +};
2604 +
2605 +const char *get_system_type(void)
2606 +{
2607 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2608 + !soc_type_strings[ath25_soc])
2609 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2610 + return soc_type_strings[ath25_soc];
2611 +}
2612 +
2613 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
2614 + u32 mii_base, int irq, void *pdata)
2615 +{
2616 + struct resource *res;
2617 +
2618 + ath25_eth[nr].dev.platform_data = pdata;
2619 + res = &ath25_eth[nr].resource[0];
2620 + res->start = base;
2621 + res->end = base + 0x2000 - 1;
2622 + res++;
2623 + res->name = mii_name;
2624 + res->start = mii_base;
2625 + res->end = mii_base + 8 - 1;
2626 + res++;
2627 + res->start = irq;
2628 + res->end = irq;
2629 + return platform_device_register(&ath25_eth[nr]);
2630 +}
2631 +
2632 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2633 +{
2634 + struct uart_port s;
2635 +
2636 + memset(&s, 0, sizeof(s));
2637 +
2638 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2639 + s.iotype = UPIO_MEM32;
2640 + s.irq = irq;
2641 + s.regshift = 2;
2642 + s.mapbase = mapbase;
2643 + s.uartclk = uartclk;
2644 +
2645 + early_serial_setup(&s);
2646 +}
2647 +
2648 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2649 +{
2650 + struct resource *res;
2651 +
2652 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2653 + res = &ath25_wmac[nr].resource[0];
2654 + res->start = base;
2655 + res->end = base + 0x10000 - 1;
2656 + res++;
2657 + res->start = irq;
2658 + res->end = irq;
2659 + return platform_device_register(&ath25_wmac[nr]);
2660 +}
2661 +
2662 +static int __init ath25_register_devices(void)
2663 +{
2664 + if (is_ar5312())
2665 + ar5312_init_devices();
2666 + else
2667 + ar2315_init_devices();
2668 +
2669 + return 0;
2670 +}
2671 +
2672 +device_initcall(ath25_register_devices);
2673 +
2674 +static int __init ath25_arch_init(void)
2675 +{
2676 + if (is_ar5312())
2677 + ar5312_arch_init();
2678 + else
2679 + ar2315_arch_init();
2680 +
2681 + return 0;
2682 +}
2683 +
2684 +arch_initcall(ath25_arch_init);
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