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atheros: v3.18: rearrange PCI regs definitions
[openwrt/staging/dedeckeh.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,234 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ath25_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == ATH25_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ath25_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ath25_board.radio = addr + 0x10000;
140 +
141 + if (ath25_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ath25_find_config(u8 *flash_limit)
191 +{
192 + struct ath25_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ath25_board.config = NULL;
202 + ath25_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ath25_board.config = (struct ath25_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ath25_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ath25_board.radio)
241 + rcfg = (u8 *)ath25_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ath25_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ath25_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ath25_halt;
275 + pm_power_off = ath25_halt;
276 +
277 + if (is_ar5312())
278 + ar5312_plat_mem_setup();
279 + else
280 + ar2315_plat_mem_setup();
281 +
282 + /* Disable data watchpoints */
283 + write_c0_watchlo0(0);
284 +}
285 +
286 +asmlinkage void plat_irq_dispatch(void)
287 +{
288 + ath25_irq_dispatch();
289 +}
290 +
291 +void __init plat_time_init(void)
292 +{
293 + if (is_ar5312())
294 + ar5312_plat_time_init();
295 + else
296 + ar2315_plat_time_init();
297 +}
298 +
299 +unsigned int __cpuinit get_c0_compare_int(void)
300 +{
301 + return CP0_LEGACY_COMPARE_IRQ;
302 +}
303 +
304 +void __init arch_init_irq(void)
305 +{
306 + clear_c0_status(ST0_IM);
307 + mips_cpu_irq_init();
308 +
309 + /* Initialize interrupt controllers */
310 + if (is_ar5312())
311 + ar5312_arch_init_irq();
312 + else
313 + ar2315_arch_init_irq();
314 +}
315 --- /dev/null
316 +++ b/arch/mips/ath25/prom.c
317 @@ -0,0 +1,26 @@
318 +/*
319 + * This file is subject to the terms and conditions of the GNU General Public
320 + * License. See the file "COPYING" in the main directory of this archive
321 + * for more details.
322 + *
323 + * Copyright MontaVista Software Inc
324 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
325 + * Copyright (C) 2006 FON Technology, SL.
326 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
327 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
328 + */
329 +
330 +/*
331 + * Prom setup file for ar231x
332 + */
333 +
334 +#include <linux/init.h>
335 +#include <asm/bootinfo.h>
336 +
337 +void __init prom_init(void)
338 +{
339 +}
340 +
341 +void __init prom_free_prom_memory(void)
342 +{
343 +}
344 --- /dev/null
345 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
346 @@ -0,0 +1,84 @@
347 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
348 +#define __ASM_MACH_ATH25_PLATFORM_H
349 +
350 +#include <linux/etherdevice.h>
351 +
352 +/*
353 + * This is board-specific data that is stored in a "fixed" location in flash.
354 + * It is shared across operating systems, so it should not be changed lightly.
355 + * The main reason we need it is in order to extract the ethernet MAC
356 + * address(es).
357 + */
358 +struct ath25_boarddata {
359 + u32 magic; /* board data is valid */
360 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
361 + u16 cksum; /* checksum (starting with BD_REV 2) */
362 + u16 rev; /* revision of this struct */
363 +#define BD_REV 4
364 + char board_name[64]; /* Name of board */
365 + u16 major; /* Board major number */
366 + u16 minor; /* Board minor number */
367 + u32 flags; /* Board configuration */
368 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
369 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
370 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
371 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
372 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
373 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
374 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
375 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
376 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
377 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
378 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
379 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
380 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
381 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
382 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
383 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
384 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
385 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
386 + u16 reset_config_gpio; /* Reset factory GPIO pin */
387 + u16 sys_led_gpio; /* System LED GPIO pin */
388 +
389 + u32 cpu_freq; /* CPU core frequency in Hz */
390 + u32 sys_freq; /* System frequency in Hz */
391 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
392 +
393 + u8 wlan0_mac[ETH_ALEN];
394 + u8 enet0_mac[ETH_ALEN];
395 + u8 enet1_mac[ETH_ALEN];
396 +
397 + u16 pci_id; /* Pseudo PCIID for common code */
398 + u16 mem_cap; /* cap bank1 in MB */
399 +
400 + /* version 3 */
401 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
402 +};
403 +
404 +#define BOARD_CONFIG_BUFSZ 0x1000
405 +
406 +/*
407 + * Platform device information for the Wireless MAC
408 + */
409 +struct ar231x_board_config {
410 + u16 devid;
411 +
412 + /* board config data */
413 + struct ath25_boarddata *config;
414 +
415 + /* radio calibration data */
416 + const char *radio;
417 +};
418 +
419 +/*
420 + * Platform device information for the Ethernet MAC
421 + */
422 +struct ar231x_eth {
423 + void (*reset_set)(u32);
424 + void (*reset_clear)(u32);
425 + u32 reset_mac;
426 + u32 reset_phy;
427 + char *macaddr;
428 +};
429 +
430 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
431 --- /dev/null
432 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
433 @@ -0,0 +1,64 @@
434 +/*
435 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
436 + *
437 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
438 + *
439 + * This file was derived from: include/asm-mips/cpu-features.h
440 + * Copyright (C) 2003, 2004 Ralf Baechle
441 + * Copyright (C) 2004 Maciej W. Rozycki
442 + *
443 + * This program is free software; you can redistribute it and/or modify it
444 + * under the terms of the GNU General Public License version 2 as published
445 + * by the Free Software Foundation.
446 + *
447 + */
448 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
449 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
450 +
451 +/*
452 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
453 + */
454 +#define cpu_has_tlb 1
455 +#define cpu_has_4kex 1
456 +#define cpu_has_3k_cache 0
457 +#define cpu_has_4k_cache 1
458 +#define cpu_has_tx39_cache 0
459 +#define cpu_has_sb1_cache 0
460 +#define cpu_has_fpu 0
461 +#define cpu_has_32fpr 0
462 +#define cpu_has_counter 1
463 +#define cpu_has_ejtag 1
464 +
465 +#if !defined(CONFIG_SOC_AR5312)
466 +# define cpu_has_llsc 1
467 +#else
468 +/*
469 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
470 + * ll/sc instructions.
471 + */
472 +# define cpu_has_llsc 0
473 +#endif
474 +
475 +#define cpu_has_mips16 0
476 +#define cpu_has_mdmx 0
477 +#define cpu_has_mips3d 0
478 +#define cpu_has_smartmips 0
479 +
480 +#define cpu_has_mips32r1 1
481 +
482 +#if !defined(CONFIG_SOC_AR5312)
483 +# define cpu_has_mips32r2 1
484 +#endif
485 +
486 +#define cpu_has_mips64r1 0
487 +#define cpu_has_mips64r2 0
488 +
489 +#define cpu_has_dsp 0
490 +#define cpu_has_mipsmt 0
491 +
492 +#define cpu_has_64bits 0
493 +#define cpu_has_64bit_zero_reg 0
494 +#define cpu_has_64bit_gp_regs 0
495 +#define cpu_has_64bit_addresses 0
496 +
497 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
498 --- /dev/null
499 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
500 @@ -0,0 +1,82 @@
501 +/*
502 + * This file is subject to the terms and conditions of the GNU General Public
503 + * License. See the file "COPYING" in the main directory of this archive
504 + * for more details.
505 + *
506 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
507 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
508 + *
509 + */
510 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
511 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
512 +
513 +#include <linux/device.h>
514 +
515 +/*
516 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
517 + * of PCI host controller to enable DMA. The same value should be used as the
518 + * offset to calculate the physical address of DMA buffer for PCI devices.
519 + */
520 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
521 +
522 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
523 +{
524 +#ifdef CONFIG_PCI
525 + extern struct bus_type pci_bus_type;
526 +
527 + if (dev && dev->bus == &pci_bus_type)
528 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
529 +#endif
530 + return 0;
531 +}
532 +
533 +static inline dma_addr_t
534 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
535 +{
536 + return virt_to_phys(addr) + ath25_dev_offset(dev);
537 +}
538 +
539 +static inline dma_addr_t
540 +plat_map_dma_mem_page(struct device *dev, struct page *page)
541 +{
542 + return page_to_phys(page) + ath25_dev_offset(dev);
543 +}
544 +
545 +static inline unsigned long
546 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
547 +{
548 + return dma_addr - ath25_dev_offset(dev);
549 +}
550 +
551 +static inline void
552 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
553 + enum dma_data_direction direction)
554 +{
555 +}
556 +
557 +static inline int plat_dma_supported(struct device *dev, u64 mask)
558 +{
559 + return 1;
560 +}
561 +
562 +static inline void plat_extra_sync_for_device(struct device *dev)
563 +{
564 +}
565 +
566 +static inline int plat_dma_mapping_error(struct device *dev,
567 + dma_addr_t dma_addr)
568 +{
569 + return 0;
570 +}
571 +
572 +static inline int plat_device_is_coherent(struct device *dev)
573 +{
574 +#ifdef CONFIG_DMA_COHERENT
575 + return 1;
576 +#endif
577 +#ifdef CONFIG_DMA_NONCOHERENT
578 + return 0;
579 +#endif
580 +}
581 +
582 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
583 --- /dev/null
584 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
585 @@ -0,0 +1,16 @@
586 +#ifndef __ASM_MACH_ATH25_GPIO_H
587 +#define __ASM_MACH_ATH25_GPIO_H
588 +
589 +#include <asm-generic/gpio.h>
590 +
591 +#define gpio_get_value __gpio_get_value
592 +#define gpio_set_value __gpio_set_value
593 +#define gpio_cansleep __gpio_cansleep
594 +#define gpio_to_irq __gpio_to_irq
595 +
596 +static inline int irq_to_gpio(unsigned irq)
597 +{
598 + return -EINVAL;
599 +}
600 +
601 +#endif /* __ASM_MACH_ATH25_GPIO_H */
602 --- /dev/null
603 +++ b/arch/mips/include/asm/mach-ath25/war.h
604 @@ -0,0 +1,25 @@
605 +/*
606 + * This file is subject to the terms and conditions of the GNU General Public
607 + * License. See the file "COPYING" in the main directory of this archive
608 + * for more details.
609 + *
610 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
611 + */
612 +#ifndef __ASM_MACH_ATH25_WAR_H
613 +#define __ASM_MACH_ATH25_WAR_H
614 +
615 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
616 +#define R4600_V1_HIT_CACHEOP_WAR 0
617 +#define R4600_V2_HIT_CACHEOP_WAR 0
618 +#define R5432_CP0_INTERRUPT_WAR 0
619 +#define BCM1250_M3_WAR 0
620 +#define SIBYTE_1956_WAR 0
621 +#define MIPS4K_ICACHE_REFILL_WAR 0
622 +#define MIPS_CACHE_SYNC_WAR 0
623 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
624 +#define RM9000_CDEX_SMP_WAR 0
625 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
626 +#define R10000_LLSC_WAR 0
627 +#define MIPS34K_MISSED_ITLB_WAR 0
628 +
629 +#endif /* __ASM_MACH_ATH25_WAR_H */
630 --- /dev/null
631 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
632 @@ -0,0 +1,510 @@
633 +/*
634 + * Register definitions for AR2315+
635 + *
636 + * This file is subject to the terms and conditions of the GNU General Public
637 + * License. See the file "COPYING" in the main directory of this archive
638 + * for more details.
639 + *
640 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
641 + * Copyright (C) 2006 FON Technology, SL.
642 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
643 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
644 + */
645 +
646 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
647 +#define __ASM_MACH_ATH25_AR2315_REGS_H
648 +
649 +/*
650 + * IRQs
651 + */
652 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
653 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
654 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
655 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
656 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
657 +
658 +/*
659 + * Miscellaneous interrupts, which share IP2.
660 + */
661 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
662 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
663 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
664 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
665 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
666 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
667 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
668 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
669 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
670 +#define AR2315_MISC_IRQ_COUNT 9
671 +
672 +/*
673 + * Address map
674 + */
675 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
676 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
677 +#define AR2315_PCI 0x10100000 /* PCI MMR */
678 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
679 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
680 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
681 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
682 +#define AR2315_UART0 0x11100000 /* UART MMR */
683 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
684 +#define AR2315_PCIEXT 0x80000000 /* pci external */
685 +#define AR2315_PCIEXT_SZ 0x40000000
686 +
687 +/* MII registers offset inside Ethernet MMR region */
688 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
689 +
690 +/*
691 + * Cold reset register
692 + */
693 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
694 +
695 +#define AR2315_RESET_COLD_AHB 0x00000001
696 +#define AR2315_RESET_COLD_APB 0x00000002
697 +#define AR2315_RESET_COLD_CPU 0x00000004
698 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
699 +#define AR2315_RESET_SYSTEM \
700 + (RESET_COLD_CPU |\
701 + RESET_COLD_APB |\
702 + RESET_COLD_AHB) /* full system */
703 +#define AR2317_RESET_SYSTEM 0x00000010
704 +
705 +/*
706 + * Reset register
707 + */
708 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
709 +
710 +/* warm reset WLAN0 MAC */
711 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
712 +/* warm reset WLAN0 BaseBand */
713 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
714 +/* warm reset MPEG-TS */
715 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
716 +/* warm reset PCI ahb/dma */
717 +#define AR2315_RESET_PCIDMA 0x00000008
718 +/* warm reset memory controller */
719 +#define AR2315_RESET_MEMCTL 0x00000010
720 +/* warm reset local bus */
721 +#define AR2315_RESET_LOCAL 0x00000020
722 +/* warm reset I2C bus */
723 +#define AR2315_RESET_I2C_RSVD 0x00000040
724 +/* warm reset SPI interface */
725 +#define AR2315_RESET_SPI 0x00000080
726 +/* warm reset UART0 */
727 +#define AR2315_RESET_UART0 0x00000100
728 +/* warm reset IR interface */
729 +#define AR2315_RESET_IR_RSVD 0x00000200
730 +/* cold reset ENET0 phy */
731 +#define AR2315_RESET_EPHY0 0x00000400
732 +/* cold reset ENET0 mac */
733 +#define AR2315_RESET_ENET0 0x00000800
734 +
735 +/*
736 + * AHB master arbitration control
737 + */
738 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
739 +
740 +/* CPU, default */
741 +#define AR2315_ARB_CPU 0x00000001
742 +/* WLAN */
743 +#define AR2315_ARB_WLAN 0x00000002
744 +/* MPEG-TS */
745 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
746 +/* LOCAL */
747 +#define AR2315_ARB_LOCAL 0x00000008
748 +/* PCI */
749 +#define AR2315_ARB_PCI 0x00000010
750 +/* Ethernet */
751 +#define AR2315_ARB_ETHERNET 0x00000020
752 +/* retry policy, debug only */
753 +#define AR2315_ARB_RETRY 0x00000100
754 +
755 +/*
756 + * Config Register
757 + */
758 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
759 +
760 +/* EC - AHB bridge endianess */
761 +#define AR2315_CONFIG_AHB 0x00000001
762 +/* WLAN byteswap */
763 +#define AR2315_CONFIG_WLAN 0x00000002
764 +/* MPEG-TS byteswap */
765 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
766 +/* PCI byteswap */
767 +#define AR2315_CONFIG_PCI 0x00000008
768 +/* Memory controller endianess */
769 +#define AR2315_CONFIG_MEMCTL 0x00000010
770 +/* Local bus byteswap */
771 +#define AR2315_CONFIG_LOCAL 0x00000020
772 +/* Ethernet byteswap */
773 +#define AR2315_CONFIG_ETHERNET 0x00000040
774 +
775 +/* CPU write buffer merge */
776 +#define AR2315_CONFIG_MERGE 0x00000200
777 +/* CPU big endian */
778 +#define AR2315_CONFIG_CPU 0x00000400
779 +#define AR2315_CONFIG_PCIAHB 0x00000800
780 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
781 +/* SPI byteswap */
782 +#define AR2315_CONFIG_SPI 0x00008000
783 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
784 +#define AR2315_CONFIG_CPU_PCI 0x00020000
785 +#define AR2315_CONFIG_CPU_MMR 0x00040000
786 +#define AR2315_CONFIG_BIG 0x00000400
787 +
788 +/*
789 + * NMI control
790 + */
791 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
792 +
793 +#define AR2315_NMI_EN 1
794 +
795 +/*
796 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
797 + */
798 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
799 +
800 +#define AR2315_REV_MAJ 0x00f0
801 +#define AR2315_REV_MAJ_S 4
802 +#define AR2315_REV_MIN 0x000f
803 +#define AR2315_REV_MIN_S 0
804 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
805 +
806 +/*
807 + * Interface Enable
808 + */
809 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
810 +
811 +#define AR2315_IF_MASK 0x00000007
812 +#define AR2315_IF_DISABLED 0
813 +#define AR2315_IF_PCI 1
814 +#define AR2315_IF_TS_LOCAL 2
815 +/* only for emulation with separate pins */
816 +#define AR2315_IF_ALL 3
817 +#define AR2315_IF_LOCAL_HOST 0x00000008
818 +#define AR2315_IF_PCI_HOST 0x00000010
819 +#define AR2315_IF_PCI_INTR 0x00000020
820 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
821 +#define AR2315_IF_PCI_CLK_INPUT 0
822 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
823 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
824 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
825 +#define AR2315_IF_PCI_CLK_SHIFT 16
826 +
827 +/*
828 + * APB Interrupt control
829 + */
830 +
831 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
832 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
833 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
834 +
835 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
836 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
837 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
838 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
839 +#define AR2315_ISR_APB 0x0010 /* APB error */
840 +#define AR2315_ISR_TIMER 0x0020 /* timer */
841 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
842 +#define AR2315_ISR_WD 0x0080 /* watchdog */
843 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
844 +
845 +#define AR2315_GISR_MISC 0x0001
846 +#define AR2315_GISR_WLAN0 0x0002
847 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
848 +#define AR2315_GISR_LOCALPCI 0x0008
849 +#define AR2315_GISR_WMACPOLL 0x0010
850 +#define AR2315_GISR_TIMER 0x0020
851 +#define AR2315_GISR_ETHERNET 0x0040
852 +
853 +/*
854 + * Interrupt routing from IO to the processor IP bits
855 + * Define our inter mask and level
856 + */
857 +#define AR2315_INTR_MISCIO SR_IBIT3
858 +#define AR2315_INTR_WLAN0 SR_IBIT4
859 +#define AR2315_INTR_ENET0 SR_IBIT5
860 +#define AR2315_INTR_LOCALPCI SR_IBIT6
861 +#define AR2315_INTR_WMACPOLL SR_IBIT7
862 +#define AR2315_INTR_COMPARE SR_IBIT8
863 +
864 +/*
865 + * Timers
866 + */
867 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
868 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
869 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
870 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
871 +
872 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
873 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
874 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
875 +
876 +/*
877 + * CPU Performance Counters
878 + */
879 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
880 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
881 +
882 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
883 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
884 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
885 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
886 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
887 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
888 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
889 +
890 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
891 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
892 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
893 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
894 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
895 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
896 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
897 +
898 +/*
899 + * AHB Error Reporting.
900 + */
901 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
902 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
903 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
904 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
905 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
906 +
907 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
908 + /* write 1 to clear all bits in ERR0 */
909 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
910 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
911 +
912 +#define AR2315_PROCERR_HMAST 0x0000000f
913 +#define AR2315_PROCERR_HMAST_DFLT 0
914 +#define AR2315_PROCERR_HMAST_WMAC 1
915 +#define AR2315_PROCERR_HMAST_ENET 2
916 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
917 +#define AR2315_PROCERR_HMAST_LOCAL 4
918 +#define AR2315_PROCERR_HMAST_CPU 5
919 +#define AR2315_PROCERR_HMAST_PCITGT 6
920 +
921 +#define AR2315_PROCERR_HMAST_S 0
922 +#define AR2315_PROCERR_HWRITE 0x00000010
923 +#define AR2315_PROCERR_HSIZE 0x00000060
924 +#define AR2315_PROCERR_HSIZE_S 5
925 +#define AR2315_PROCERR_HTRANS 0x00000180
926 +#define AR2315_PROCERR_HTRANS_S 7
927 +#define AR2315_PROCERR_HBURST 0x00000e00
928 +#define AR2315_PROCERR_HBURST_S 9
929 +
930 +/*
931 + * Clock Control
932 + */
933 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
934 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
935 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
936 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
937 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
938 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
939 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
940 +
941 +/* PLLc Control fields */
942 +#define PLLC_REF_DIV_M 0x00000003
943 +#define PLLC_REF_DIV_S 0
944 +#define PLLC_FDBACK_DIV_M 0x0000007C
945 +#define PLLC_FDBACK_DIV_S 2
946 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
947 +#define PLLC_ADD_FDBACK_DIV_S 7
948 +#define PLLC_CLKC_DIV_M 0x0001c000
949 +#define PLLC_CLKC_DIV_S 14
950 +#define PLLC_CLKM_DIV_M 0x00700000
951 +#define PLLC_CLKM_DIV_S 20
952 +
953 +/* CPU CLK Control fields */
954 +#define CPUCLK_CLK_SEL_M 0x00000003
955 +#define CPUCLK_CLK_SEL_S 0
956 +#define CPUCLK_CLK_DIV_M 0x0000000c
957 +#define CPUCLK_CLK_DIV_S 2
958 +
959 +/* AMBA CLK Control fields */
960 +#define AMBACLK_CLK_SEL_M 0x00000003
961 +#define AMBACLK_CLK_SEL_S 0
962 +#define AMBACLK_CLK_DIV_M 0x0000000c
963 +#define AMBACLK_CLK_DIV_S 2
964 +
965 +/* GPIO MMR base address */
966 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
967 +
968 +#define AR2315_RESET_GPIO 5
969 +
970 +/*
971 + * PCI Clock Control
972 + */
973 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
974 +
975 +#define AR2315_PCICLK_INPUT_M 0x3
976 +#define AR2315_PCICLK_INPUT_S 0
977 +
978 +#define AR2315_PCICLK_PLLC_CLKM 0
979 +#define AR2315_PCICLK_PLLC_CLKM1 1
980 +#define AR2315_PCICLK_PLLC_CLKC 2
981 +#define AR2315_PCICLK_REF_CLK 3
982 +
983 +#define AR2315_PCICLK_DIV_M 0xc
984 +#define AR2315_PCICLK_DIV_S 2
985 +
986 +#define AR2315_PCICLK_IN_FREQ 0
987 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
988 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
989 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
990 +
991 +/*
992 + * Observation Control Register
993 + */
994 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
995 +#define OCR_GPIO0_IRIN 0x0040
996 +#define OCR_GPIO1_IROUT 0x0080
997 +#define OCR_GPIO3_RXCLR 0x0200
998 +
999 +/*
1000 + * General Clock Control
1001 + */
1002 +
1003 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1004 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1005 +#define MISCCLK_PROCREFCLK 0x00000002
1006 +
1007 +/*
1008 + * SDRAM Controller
1009 + * - No read or write buffers are included.
1010 + */
1011 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1012 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1013 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1014 +
1015 +#define SDRAM_DATA_WIDTH_M 0x00006000
1016 +#define SDRAM_DATA_WIDTH_S 13
1017 +
1018 +#define SDRAM_COL_WIDTH_M 0x00001E00
1019 +#define SDRAM_COL_WIDTH_S 9
1020 +
1021 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1022 +#define SDRAM_ROW_WIDTH_S 5
1023 +
1024 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1025 +#define SDRAM_BANKADDR_BITS_S 3
1026 +
1027 +/*
1028 + * Local Bus Interface Registers
1029 + */
1030 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1031 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1032 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1033 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1034 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1035 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1036 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1037 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1038 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1039 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1040 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1041 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1042 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1043 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1044 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1045 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1046 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1047 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1048 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1049 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1050 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1051 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1052 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1053 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1054 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1055 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1056 +
1057 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1058 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1059 +
1060 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1061 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1062 +
1063 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1064 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1065 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1066 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1067 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1068 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1069 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1070 +#define AR2315_LBM_TIMEOUT_SHFT 7
1071 +#define AR2315_LBM_PORTMUX 0x07000000
1072 +
1073 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1074 +
1075 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1076 +#define AR2315_LB_TXEN_0 0x01
1077 +#define AR2315_LB_TXEN_1 0x02
1078 +#define AR2315_LB_TXEN_2 0x04
1079 +#define AR2315_LB_TXEN_3 0x08
1080 +
1081 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1082 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1083 +
1084 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1085 +#define AR2315_LB_RXEN 0x01
1086 +
1087 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1088 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1089 +
1090 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1091 +#define AR2315_INT_TX_DESC 0x0001
1092 +#define AR2315_INT_TX_OK 0x0002
1093 +#define AR2315_INT_TX_ERR 0x0004
1094 +#define AR2315_INT_TX_EOF 0x0008
1095 +#define AR2315_INT_RX_DESC 0x0010
1096 +#define AR2315_INT_RX_OK 0x0020
1097 +#define AR2315_INT_RX_ERR 0x0040
1098 +#define AR2315_INT_RX_EOF 0x0080
1099 +#define AR2315_INT_TX_TRUNC 0x0100
1100 +#define AR2315_INT_TX_STARVE 0x0200
1101 +#define AR2315_INT_LB_TIMEOUT 0x0400
1102 +#define AR2315_INT_LB_ERR 0x0800
1103 +#define AR2315_INT_MBOX_WR 0x1000
1104 +#define AR2315_INT_MBOX_RD 0x2000
1105 +
1106 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1107 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1108 +
1109 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1110 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1111 +
1112 +/*
1113 + * IR Interface Registers
1114 + */
1115 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1116 +
1117 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1118 +
1119 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1120 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1121 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1122 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1123 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1124 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1125 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1126 +
1127 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1128 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1129 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1130 +
1131 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1132 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1133 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1134 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1135 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1136 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1137 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1138 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1139 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1140 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1141 +
1142 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1143 --- /dev/null
1144 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1145 @@ -0,0 +1,235 @@
1146 +/*
1147 + * This file is subject to the terms and conditions of the GNU General Public
1148 + * License. See the file "COPYING" in the main directory of this archive
1149 + * for more details.
1150 + *
1151 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1152 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1153 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1154 + */
1155 +
1156 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1157 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1158 +
1159 +#include <asm/addrspace.h>
1160 +
1161 +/*
1162 + * IRQs
1163 + */
1164 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1165 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1166 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1167 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1168 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1169 +
1170 +/*
1171 + * Miscellaneous interrupts, which share IP6.
1172 + */
1173 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1174 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1175 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1176 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1177 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1178 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1179 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1180 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1181 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1182 +#define AR5312_MISC_IRQ_COUNT 9
1183 +
1184 +/*
1185 + * Address Map
1186 + */
1187 +#define AR5312_WLAN0 0x18000000
1188 +#define AR5312_WLAN1 0x18500000
1189 +#define AR5312_ENET0 0x18100000
1190 +#define AR5312_ENET1 0x18200000
1191 +#define AR5312_SDRAMCTL 0x18300000
1192 +#define AR5312_FLASHCTL 0x18400000
1193 +#define AR5312_APBBASE 0x1c000000
1194 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1195 +#define AR5312_FLASH 0x1e000000
1196 +
1197 +/*
1198 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1199 + * should be considered available. The AR5312 supports 2 enet MACS,
1200 + * even though many reference boards only actually use 1 of them
1201 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1202 + * The AR2312 supports 1 enet MAC.
1203 + */
1204 +#define AR5312_NUM_ENET_MAC 2
1205 +
1206 +/*
1207 + * Need these defines to determine true number of ethernet MACs
1208 + */
1209 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1210 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1211 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1212 +
1213 +/* MII registers offset inside Ethernet MMR region */
1214 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1215 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1216 +
1217 +/*
1218 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1219 + * should be considered available.
1220 + */
1221 +#define AR5312_NUM_WMAC 2
1222 +
1223 +/* Reset/Timer Block Address Map */
1224 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1225 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1226 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1227 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1228 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1229 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1230 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1231 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1232 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1233 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1234 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1235 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1236 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1237 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1238 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1239 +
1240 +/* AR5312_WD_CTRL register bit field definitions */
1241 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1242 +#define AR5312_WD_CTRL_NMI 0x0001
1243 +#define AR5312_WD_CTRL_RESET 0x0002
1244 +
1245 +/* AR5312_ISR register bit field definitions */
1246 +#define AR5312_ISR_TIMER 0x0001
1247 +#define AR5312_ISR_AHBPROC 0x0002
1248 +#define AR5312_ISR_AHBDMA 0x0004
1249 +#define AR5312_ISR_GPIO 0x0008
1250 +#define AR5312_ISR_UART0 0x0010
1251 +#define AR5312_ISR_UART0DMA 0x0020
1252 +#define AR5312_ISR_WD 0x0040
1253 +#define AR5312_ISR_LOCAL 0x0080
1254 +
1255 +/* AR5312_RESET register bit field definitions */
1256 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1257 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1258 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1259 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1260 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1261 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1262 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1263 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1264 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1265 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1266 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1267 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1268 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1269 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1270 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1271 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1272 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1273 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1274 +
1275 +#define AR5312_RESET_WMAC0_BITS \
1276 + (AR5312_RESET_WLAN0 |\
1277 + AR5312_RESET_WARM_WLAN0_MAC |\
1278 + AR5312_RESET_WARM_WLAN0_BB)
1279 +
1280 +#define AR5312_RESET_WMAC1_BITS \
1281 + (AR5312_RESET_WLAN1 |\
1282 + AR5312_RESET_WARM_WLAN1_MAC |\
1283 + AR5312_RESET_WARM_WLAN1_BB)
1284 +
1285 +/* AR5312_CLOCKCTL1 register bit field definitions */
1286 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1287 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1288 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1289 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1290 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1291 +
1292 +/* Valid for AR5312 and AR2312 */
1293 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1294 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1295 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1296 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1297 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1298 +
1299 +/* Valid for AR2313 */
1300 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1301 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1302 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1303 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1304 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1305 +
1306 +/* AR5312_ENABLE register bit field definitions */
1307 +#define AR5312_ENABLE_WLAN0 0x0001
1308 +#define AR5312_ENABLE_ENET0 0x0002
1309 +#define AR5312_ENABLE_ENET1 0x0004
1310 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1311 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1312 +#define AR5312_ENABLE_WLAN1 \
1313 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1314 + AR5312_ENABLE_WLAN1_DMA)
1315 +
1316 +/* AR5312_REV register bit field definitions */
1317 +#define AR5312_REV_WMAC_MAJ 0xf000
1318 +#define AR5312_REV_WMAC_MAJ_S 12
1319 +#define AR5312_REV_WMAC_MIN 0x0f00
1320 +#define AR5312_REV_WMAC_MIN_S 8
1321 +#define AR5312_REV_MAJ 0x00f0
1322 +#define AR5312_REV_MAJ_S 4
1323 +#define AR5312_REV_MIN 0x000f
1324 +#define AR5312_REV_MIN_S 0
1325 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1326 +
1327 +/* Major revision numbers, bits 7..4 of Revision ID register */
1328 +#define AR5312_REV_MAJ_AR5312 0x4
1329 +#define AR5312_REV_MAJ_AR2313 0x5
1330 +
1331 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1332 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1333 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1334 +
1335 +/* AR5312_FLASHCTL register bit field definitions */
1336 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1337 +#define FLASHCTL_IDCY_S 0
1338 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1339 +#define FLASHCTL_WST1_S 5
1340 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1341 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1342 +#define FLASHCTL_WST2_S 11
1343 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1344 +#define FLASHCTL_AC_S 16
1345 +#define FLASHCTL_AC_128K 0x00000000
1346 +#define FLASHCTL_AC_256K 0x00010000
1347 +#define FLASHCTL_AC_512K 0x00020000
1348 +#define FLASHCTL_AC_1M 0x00030000
1349 +#define FLASHCTL_AC_2M 0x00040000
1350 +#define FLASHCTL_AC_4M 0x00050000
1351 +#define FLASHCTL_AC_8M 0x00060000
1352 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1353 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1354 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1355 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1356 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1357 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1358 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1359 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1360 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1361 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1362 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1363 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1364 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1365 +
1366 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1367 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1368 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1369 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1370 +
1371 +/* ARM SDRAM Controller -- just enough to determine memory size */
1372 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1373 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1374 +#define MEM_CFG1_AC0_S 8
1375 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1376 +#define MEM_CFG1_AC1_S 12
1377 +
1378 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1379 +
1380 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1381 --- /dev/null
1382 +++ b/arch/mips/ath25/ar5312.c
1383 @@ -0,0 +1,449 @@
1384 +/*
1385 + * This file is subject to the terms and conditions of the GNU General Public
1386 + * License. See the file "COPYING" in the main directory of this archive
1387 + * for more details.
1388 + *
1389 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1390 + * Copyright (C) 2006 FON Technology, SL.
1391 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1392 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1393 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1394 + */
1395 +
1396 +/*
1397 + * Platform devices for Atheros SoCs
1398 + */
1399 +
1400 +#include <generated/autoconf.h>
1401 +#include <linux/init.h>
1402 +#include <linux/module.h>
1403 +#include <linux/types.h>
1404 +#include <linux/string.h>
1405 +#include <linux/mtd/physmap.h>
1406 +#include <linux/platform_device.h>
1407 +#include <linux/kernel.h>
1408 +#include <linux/reboot.h>
1409 +#include <linux/leds.h>
1410 +#include <linux/gpio.h>
1411 +#include <asm/bootinfo.h>
1412 +#include <asm/reboot.h>
1413 +#include <asm/time.h>
1414 +#include <linux/irq.h>
1415 +#include <linux/io.h>
1416 +
1417 +#include <ath25_platform.h>
1418 +#include <ar5312_regs.h>
1419 +#include <ar231x.h>
1420 +#include "devices.h"
1421 +#include "ar5312.h"
1422 +
1423 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1424 +{
1425 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1426 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1427 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1428 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1429 +
1430 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1431 + proc_addr, proc1, dma_addr, dma1);
1432 +
1433 + machine_restart("AHB error"); /* Catastrophic failure */
1434 + return IRQ_HANDLED;
1435 +}
1436 +
1437 +static struct irqaction ar5312_ahb_err_interrupt = {
1438 + .handler = ar5312_ahb_err_handler,
1439 + .name = "ar5312-ahb-error",
1440 +};
1441 +
1442 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1443 +{
1444 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1445 + ar231x_read_reg(AR5312_IMR);
1446 +
1447 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1448 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1449 + (void)ar231x_read_reg(AR5312_TIMER);
1450 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1451 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1452 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1453 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1454 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1455 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1456 + else
1457 + spurious_interrupt();
1458 +}
1459 +
1460 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1461 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1462 +{
1463 + unsigned int imr;
1464 +
1465 + imr = ar231x_read_reg(AR5312_IMR);
1466 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1467 + ar231x_write_reg(AR5312_IMR, imr);
1468 +}
1469 +
1470 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1471 +static void ar5312_misc_irq_mask(struct irq_data *d)
1472 +{
1473 + unsigned int imr;
1474 +
1475 + imr = ar231x_read_reg(AR5312_IMR);
1476 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1477 + ar231x_write_reg(AR5312_IMR, imr);
1478 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1479 +}
1480 +
1481 +static struct irq_chip ar5312_misc_irq_chip = {
1482 + .name = "ar5312-misc",
1483 + .irq_unmask = ar5312_misc_irq_unmask,
1484 + .irq_mask = ar5312_misc_irq_mask,
1485 +};
1486 +
1487 +static void ar5312_irq_dispatch(void)
1488 +{
1489 + int pending = read_c0_status() & read_c0_cause();
1490 +
1491 + if (pending & CAUSEF_IP2)
1492 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1493 + else if (pending & CAUSEF_IP3)
1494 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1495 + else if (pending & CAUSEF_IP4)
1496 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1497 + else if (pending & CAUSEF_IP5)
1498 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1499 + else if (pending & CAUSEF_IP6)
1500 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1501 + else if (pending & CAUSEF_IP7)
1502 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1503 + else
1504 + spurious_interrupt();
1505 +}
1506 +
1507 +void __init ar5312_arch_init_irq(void)
1508 +{
1509 + int i;
1510 +
1511 + ath25_irq_dispatch = ar5312_irq_dispatch;
1512 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1513 + int irq = AR231X_MISC_IRQ_BASE + i;
1514 +
1515 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1516 + handle_level_irq);
1517 + }
1518 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
1519 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1520 +}
1521 +
1522 +static void ar5312_device_reset_set(u32 mask)
1523 +{
1524 + u32 val;
1525 +
1526 + val = ar231x_read_reg(AR5312_RESET);
1527 + ar231x_write_reg(AR5312_RESET, val | mask);
1528 +}
1529 +
1530 +static void ar5312_device_reset_clear(u32 mask)
1531 +{
1532 + u32 val;
1533 +
1534 + val = ar231x_read_reg(AR5312_RESET);
1535 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1536 +}
1537 +
1538 +static struct physmap_flash_data ar5312_flash_data = {
1539 + .width = 2,
1540 +};
1541 +
1542 +static struct resource ar5312_flash_resource = {
1543 + .start = AR5312_FLASH,
1544 + .end = AR5312_FLASH + 0x800000 - 1,
1545 + .flags = IORESOURCE_MEM,
1546 +};
1547 +
1548 +static struct ar231x_eth ar5312_eth0_data = {
1549 + .reset_set = ar5312_device_reset_set,
1550 + .reset_clear = ar5312_device_reset_clear,
1551 + .reset_mac = AR5312_RESET_ENET0,
1552 + .reset_phy = AR5312_RESET_EPHY0,
1553 +};
1554 +
1555 +static struct ar231x_eth ar5312_eth1_data = {
1556 + .reset_set = ar5312_device_reset_set,
1557 + .reset_clear = ar5312_device_reset_clear,
1558 + .reset_mac = AR5312_RESET_ENET1,
1559 + .reset_phy = AR5312_RESET_EPHY1,
1560 +};
1561 +
1562 +static struct platform_device ar5312_physmap_flash = {
1563 + .name = "physmap-flash",
1564 + .id = 0,
1565 + .dev.platform_data = &ar5312_flash_data,
1566 + .resource = &ar5312_flash_resource,
1567 + .num_resources = 1,
1568 +};
1569 +
1570 +#ifdef CONFIG_LEDS_GPIO
1571 +static struct gpio_led ar5312_leds[] = {
1572 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1573 +};
1574 +
1575 +static const struct gpio_led_platform_data ar5312_led_data = {
1576 + .num_leds = ARRAY_SIZE(ar5312_leds),
1577 + .leds = (void *)ar5312_leds,
1578 +};
1579 +
1580 +static struct platform_device ar5312_gpio_leds = {
1581 + .name = "leds-gpio",
1582 + .id = -1,
1583 + .dev.platform_data = (void *)&ar5312_led_data,
1584 +};
1585 +#endif
1586 +
1587 +/*
1588 + * NB: This mapping size is larger than the actual flash size,
1589 + * but this shouldn't be a problem here, because the flash
1590 + * will simply be mapped multiple times.
1591 + */
1592 +static char __init *ar5312_flash_limit(void)
1593 +{
1594 + u32 ctl;
1595 + /*
1596 + * Configure flash bank 0.
1597 + * Assume 8M window size. Flash will be aliased if it's smaller
1598 + */
1599 + ctl = FLASHCTL_E |
1600 + FLASHCTL_AC_8M |
1601 + FLASHCTL_RBLE |
1602 + (0x01 << FLASHCTL_IDCY_S) |
1603 + (0x07 << FLASHCTL_WST1_S) |
1604 + (0x07 << FLASHCTL_WST2_S) |
1605 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1606 +
1607 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1608 +
1609 + /* Disable other flash banks */
1610 + ar231x_write_reg(AR5312_FLASHCTL1,
1611 + ar231x_read_reg(AR5312_FLASHCTL1) &
1612 + ~(FLASHCTL_E | FLASHCTL_AC));
1613 +
1614 + ar231x_write_reg(AR5312_FLASHCTL2,
1615 + ar231x_read_reg(AR5312_FLASHCTL2) &
1616 + ~(FLASHCTL_E | FLASHCTL_AC));
1617 +
1618 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1619 +}
1620 +
1621 +void __init ar5312_init_devices(void)
1622 +{
1623 + struct ath25_boarddata *config;
1624 + u32 fctl = 0;
1625 + u8 *c;
1626 +
1627 + /* Locate board/radio config data */
1628 + ath25_find_config(ar5312_flash_limit());
1629 + config = ath25_board.config;
1630 +
1631 + /* AR2313 has CPU minor rev. 10 */
1632 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1633 + ath25_soc = ATH25_SOC_AR2313;
1634 +
1635 + /* AR2312 shares the same Silicon ID as AR5312 */
1636 + else if (config->flags & BD_ISCASPER)
1637 + ath25_soc = ATH25_SOC_AR2312;
1638 +
1639 + /* Everything else is probably AR5312 or compatible */
1640 + else
1641 + ath25_soc = ATH25_SOC_AR5312;
1642 +
1643 + /* fixup flash width */
1644 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1645 + switch (fctl) {
1646 + case FLASHCTL_MW16:
1647 + ar5312_flash_data.width = 2;
1648 + break;
1649 + case FLASHCTL_MW8:
1650 + default:
1651 + ar5312_flash_data.width = 1;
1652 + break;
1653 + }
1654 +
1655 + platform_device_register(&ar5312_physmap_flash);
1656 +
1657 +#ifdef CONFIG_LEDS_GPIO
1658 + ar5312_leds[0].gpio = config->sys_led_gpio;
1659 + platform_device_register(&ar5312_gpio_leds);
1660 +#endif
1661 +
1662 + /* Fix up MAC addresses if necessary */
1663 + if (is_broadcast_ether_addr(config->enet0_mac))
1664 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1665 +
1666 + /* If ENET0 and ENET1 have the same mac address,
1667 + * increment the one from ENET1 */
1668 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1669 + c = config->enet1_mac + 5;
1670 + while ((c >= config->enet1_mac) && !(++(*c)))
1671 + c--;
1672 + }
1673 +
1674 + switch (ath25_soc) {
1675 + case ATH25_SOC_AR5312:
1676 + ar5312_eth0_data.macaddr = config->enet0_mac;
1677 + ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1678 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1679 + &ar5312_eth0_data);
1680 +
1681 + ar5312_eth1_data.macaddr = config->enet1_mac;
1682 + ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1683 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1684 + &ar5312_eth1_data);
1685 +
1686 + if (!ath25_board.radio)
1687 + return;
1688 +
1689 + if (!(config->flags & BD_WLAN0))
1690 + break;
1691 +
1692 + ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1693 + break;
1694 + /*
1695 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1696 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1697 + */
1698 + case ATH25_SOC_AR2312:
1699 + case ATH25_SOC_AR2313:
1700 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1701 + ar5312_eth1_data.macaddr = config->enet0_mac;
1702 + ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1703 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1704 + &ar5312_eth1_data);
1705 +
1706 + if (!ath25_board.radio)
1707 + return;
1708 + break;
1709 + default:
1710 + break;
1711 + }
1712 +
1713 + if (config->flags & BD_WLAN1)
1714 + ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1715 +}
1716 +
1717 +static void ar5312_restart(char *command)
1718 +{
1719 + /* reset the system */
1720 + local_irq_disable();
1721 + while (1)
1722 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1723 +}
1724 +
1725 +/*
1726 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1727 + * to determine the predevisor value.
1728 + */
1729 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1730 +
1731 +static unsigned __init ar5312_cpu_frequency(void)
1732 +{
1733 + unsigned int scratch;
1734 + unsigned int predivide_mask, predivide_shift;
1735 + unsigned int multiplier_mask, multiplier_shift;
1736 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1737 + unsigned int doubler_mask;
1738 + u16 devid;
1739 +
1740 + /* Trust the bootrom's idea of cpu frequency. */
1741 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1742 + if (scratch)
1743 + return scratch;
1744 +
1745 + devid = ar231x_read_reg(AR5312_REV);
1746 + devid &= AR5312_REV_MAJ;
1747 + devid >>= AR5312_REV_MAJ_S;
1748 + if (devid == AR5312_REV_MAJ_AR2313) {
1749 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1750 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1751 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1752 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1753 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1754 + } else { /* AR5312 and AR2312 */
1755 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1756 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1757 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1758 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1759 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1760 + }
1761 +
1762 + /*
1763 + * Clocking is derived from a fixed 40MHz input clock.
1764 + *
1765 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1766 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1767 + * flash, Timer, Watchdog Timer)
1768 + *
1769 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1770 + *
1771 + * So, for example, with a PLL multiplier of 5, we have
1772 + *
1773 + * cpu_freq = 200MHz
1774 + * sys_freq = 50MHz
1775 + * cnt_freq = 100MHz
1776 + *
1777 + * We compute the CPU frequency, based on PLL settings.
1778 + */
1779 +
1780 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1781 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1782 + predivisor = clockctl1_predivide_table[predivide_select];
1783 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1784 +
1785 + if (clock_ctl1 & doubler_mask)
1786 + multiplier = multiplier << 1;
1787 +
1788 + return (40000000 / predivisor) * multiplier;
1789 +}
1790 +
1791 +static inline unsigned ar5312_sys_frequency(void)
1792 +{
1793 + return ar5312_cpu_frequency() / 4;
1794 +}
1795 +
1796 +void __init ar5312_plat_time_init(void)
1797 +{
1798 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1799 +}
1800 +
1801 +void __init ar5312_plat_mem_setup(void)
1802 +{
1803 + u32 memsize, memcfg, bank0AC, bank1AC;
1804 + u32 devid;
1805 +
1806 + /* Detect memory size */
1807 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1808 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1809 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1810 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1811 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1812 + memsize <<= 20;
1813 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1814 +
1815 + devid = ar231x_read_reg(AR5312_REV);
1816 + devid >>= AR5312_REV_WMAC_MIN_S;
1817 + devid &= AR5312_REV_CHIP;
1818 + ath25_board.devid = (u16)devid;
1819 +
1820 + /* Clear any lingering AHB errors */
1821 + ar231x_read_reg(AR5312_PROCADDR);
1822 + ar231x_read_reg(AR5312_DMAADDR);
1823 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1824 +
1825 + _machine_restart = ar5312_restart;
1826 +}
1827 +
1828 +void __init ar5312_arch_init(void)
1829 +{
1830 + ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1831 + ar5312_sys_frequency());
1832 +}
1833 --- /dev/null
1834 +++ b/arch/mips/ath25/ar2315.c
1835 @@ -0,0 +1,401 @@
1836 +/*
1837 + * This file is subject to the terms and conditions of the GNU General Public
1838 + * License. See the file "COPYING" in the main directory of this archive
1839 + * for more details.
1840 + *
1841 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1842 + * Copyright (C) 2006 FON Technology, SL.
1843 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1844 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1845 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1846 + */
1847 +
1848 +/*
1849 + * Platform devices for Atheros SoCs
1850 + */
1851 +
1852 +#include <generated/autoconf.h>
1853 +#include <linux/init.h>
1854 +#include <linux/module.h>
1855 +#include <linux/types.h>
1856 +#include <linux/string.h>
1857 +#include <linux/platform_device.h>
1858 +#include <linux/kernel.h>
1859 +#include <linux/reboot.h>
1860 +#include <linux/delay.h>
1861 +#include <linux/leds.h>
1862 +#include <linux/gpio.h>
1863 +#include <asm/bootinfo.h>
1864 +#include <asm/reboot.h>
1865 +#include <asm/time.h>
1866 +#include <linux/irq.h>
1867 +#include <linux/io.h>
1868 +
1869 +#include <ath25_platform.h>
1870 +#include <ar2315_regs.h>
1871 +#include <ar231x.h>
1872 +#include "devices.h"
1873 +#include "ar2315.h"
1874 +
1875 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1876 +{
1877 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
1878 + ar231x_read_reg(AR2315_AHB_ERR1);
1879 +
1880 + pr_emerg("AHB fatal error\n");
1881 + machine_restart("AHB error"); /* Catastrophic failure */
1882 +
1883 + return IRQ_HANDLED;
1884 +}
1885 +
1886 +static struct irqaction ar2315_ahb_err_interrupt = {
1887 + .handler = ar2315_ahb_err_handler,
1888 + .name = "ar2315-ahb-error",
1889 +};
1890 +
1891 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1892 +{
1893 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
1894 + ar231x_read_reg(AR2315_IMR);
1895 +
1896 + if (misc_intr & AR2315_ISR_SPI)
1897 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
1898 + else if (misc_intr & AR2315_ISR_TIMER)
1899 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
1900 + else if (misc_intr & AR2315_ISR_AHB)
1901 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
1902 + else if (misc_intr & AR2315_ISR_GPIO) {
1903 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
1904 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
1905 + } else if (misc_intr & AR2315_ISR_UART0)
1906 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
1907 + else if (misc_intr & AR2315_ISR_WD) {
1908 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
1909 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
1910 + } else
1911 + spurious_interrupt();
1912 +}
1913 +
1914 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1915 +{
1916 + unsigned int imr;
1917 +
1918 + imr = ar231x_read_reg(AR2315_IMR);
1919 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1920 + ar231x_write_reg(AR2315_IMR, imr);
1921 +}
1922 +
1923 +static void ar2315_misc_irq_mask(struct irq_data *d)
1924 +{
1925 + unsigned int imr;
1926 +
1927 + imr = ar231x_read_reg(AR2315_IMR);
1928 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1929 + ar231x_write_reg(AR2315_IMR, imr);
1930 +}
1931 +
1932 +static struct irq_chip ar2315_misc_irq_chip = {
1933 + .name = "ar2315-misc",
1934 + .irq_unmask = ar2315_misc_irq_unmask,
1935 + .irq_mask = ar2315_misc_irq_mask,
1936 +};
1937 +
1938 +/*
1939 + * Called when an interrupt is received, this function
1940 + * determines exactly which interrupt it was, and it
1941 + * invokes the appropriate handler.
1942 + *
1943 + * Implicitly, we also define interrupt priority by
1944 + * choosing which to dispatch first.
1945 + */
1946 +static void ar2315_irq_dispatch(void)
1947 +{
1948 + int pending = read_c0_status() & read_c0_cause();
1949 +
1950 + if (pending & CAUSEF_IP3)
1951 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
1952 + else if (pending & CAUSEF_IP4)
1953 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
1954 + else if (pending & CAUSEF_IP2)
1955 + do_IRQ(AR2315_IRQ_MISC_INTRS);
1956 + else if (pending & CAUSEF_IP7)
1957 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1958 + else
1959 + spurious_interrupt();
1960 +}
1961 +
1962 +void __init ar2315_arch_init_irq(void)
1963 +{
1964 + int i;
1965 +
1966 + ath25_irq_dispatch = ar2315_irq_dispatch;
1967 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
1968 + int irq = AR231X_MISC_IRQ_BASE + i;
1969 +
1970 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
1971 + handle_level_irq);
1972 + }
1973 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
1974 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
1975 +}
1976 +
1977 +static void ar2315_device_reset_set(u32 mask)
1978 +{
1979 + u32 val;
1980 +
1981 + val = ar231x_read_reg(AR2315_RESET);
1982 + ar231x_write_reg(AR2315_RESET, val | mask);
1983 +}
1984 +
1985 +static void ar2315_device_reset_clear(u32 mask)
1986 +{
1987 + u32 val;
1988 +
1989 + val = ar231x_read_reg(AR2315_RESET);
1990 + ar231x_write_reg(AR2315_RESET, val & ~mask);
1991 +}
1992 +
1993 +static struct ar231x_eth ar2315_eth_data = {
1994 + .reset_set = ar2315_device_reset_set,
1995 + .reset_clear = ar2315_device_reset_clear,
1996 + .reset_mac = AR2315_RESET_ENET0,
1997 + .reset_phy = AR2315_RESET_EPHY0,
1998 +};
1999 +
2000 +static struct resource ar2315_spiflash_res[] = {
2001 + {
2002 + .name = "spiflash_read",
2003 + .flags = IORESOURCE_MEM,
2004 + .start = AR2315_SPI_READ,
2005 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2006 + },
2007 + {
2008 + .name = "spiflash_mmr",
2009 + .flags = IORESOURCE_MEM,
2010 + .start = AR2315_SPI_MMR,
2011 + .end = AR2315_SPI_MMR + 12 - 1,
2012 + },
2013 +};
2014 +
2015 +static struct platform_device ar2315_spiflash = {
2016 + .id = 0,
2017 + .name = "ar2315-spiflash",
2018 + .resource = ar2315_spiflash_res,
2019 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2020 +};
2021 +
2022 +static struct resource ar2315_wdt_res[] = {
2023 + {
2024 + .flags = IORESOURCE_MEM,
2025 + .start = AR2315_WD,
2026 + .end = AR2315_WD + 8 - 1,
2027 + },
2028 + {
2029 + .flags = IORESOURCE_IRQ,
2030 + .start = AR2315_MISC_IRQ_WATCHDOG,
2031 + .end = AR2315_MISC_IRQ_WATCHDOG,
2032 + }
2033 +};
2034 +
2035 +static struct platform_device ar2315_wdt = {
2036 + .id = 0,
2037 + .name = "ar2315-wdt",
2038 + .resource = ar2315_wdt_res,
2039 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2040 +};
2041 +
2042 +/*
2043 + * NB: We use mapping size that is larger than the actual flash size,
2044 + * but this shouldn't be a problem here, because the flash will simply
2045 + * be mapped multiple times.
2046 + */
2047 +static u8 __init *ar2315_flash_limit(void)
2048 +{
2049 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2050 +}
2051 +
2052 +#ifdef CONFIG_LEDS_GPIO
2053 +static struct gpio_led ar2315_leds[6];
2054 +static struct gpio_led_platform_data ar2315_led_data = {
2055 + .leds = (void *)ar2315_leds,
2056 +};
2057 +
2058 +static struct platform_device ar2315_gpio_leds = {
2059 + .name = "leds-gpio",
2060 + .id = -1,
2061 + .dev = {
2062 + .platform_data = (void *)&ar2315_led_data,
2063 + }
2064 +};
2065 +
2066 +static void __init ar2315_init_gpio_leds(void)
2067 +{
2068 + static char led_names[6][6];
2069 + int i, led = 0;
2070 +
2071 + ar2315_led_data.num_leds = 0;
2072 + for (i = 1; i < 8; i++) {
2073 + if ((i == AR2315_RESET_GPIO) ||
2074 + (i == ath25_board.config->reset_config_gpio))
2075 + continue;
2076 +
2077 + if (i == ath25_board.config->sys_led_gpio)
2078 + strcpy(led_names[led], "wlan");
2079 + else
2080 + sprintf(led_names[led], "gpio%d", i);
2081 +
2082 + ar2315_leds[led].name = led_names[led];
2083 + ar2315_leds[led].gpio = i;
2084 + ar2315_leds[led].active_low = 0;
2085 + led++;
2086 + }
2087 + ar2315_led_data.num_leds = led;
2088 + platform_device_register(&ar2315_gpio_leds);
2089 +}
2090 +#else
2091 +static inline void ar2315_init_gpio_leds(void)
2092 +{
2093 +}
2094 +#endif
2095 +
2096 +void __init ar2315_init_devices(void)
2097 +{
2098 + /* Find board configuration */
2099 + ath25_find_config(ar2315_flash_limit());
2100 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
2101 +
2102 + ar2315_init_gpio_leds();
2103 + platform_device_register(&ar2315_wdt);
2104 + platform_device_register(&ar2315_spiflash);
2105 + ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2106 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2107 + ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2108 +}
2109 +
2110 +static void ar2315_restart(char *command)
2111 +{
2112 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2113 +
2114 + local_irq_disable();
2115 +
2116 + /* try reset the system via reset control */
2117 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2118 +
2119 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2120 + * a workaround. Give it some time to attempt a gpio based hardware
2121 + * reset (atheros reference design workaround) */
2122 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2123 + mdelay(100);
2124 +
2125 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2126 + * workaround. Attempt to jump to the mips reset location -
2127 + * the boot loader itself might be able to recover the system */
2128 + mips_reset_vec();
2129 +}
2130 +
2131 +/*
2132 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2133 + * to determine the predevisor value.
2134 + */
2135 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2136 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2137 +
2138 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
2139 +{
2140 + unsigned int pllc_ctrl, cpu_div;
2141 + unsigned int pllc_out, refdiv, fdiv, divby2;
2142 + unsigned int clk_div;
2143 +
2144 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2145 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2146 + refdiv = clockctl1_predivide_table[refdiv];
2147 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2148 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2149 + divby2 += 1;
2150 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2151 +
2152 + /* clkm input selected */
2153 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2154 + case 0:
2155 + case 1:
2156 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2157 + PLLC_CLKM_DIV_S];
2158 + break;
2159 + case 2:
2160 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2161 + PLLC_CLKC_DIV_S];
2162 + break;
2163 + default:
2164 + pllc_out = 40000000;
2165 + clk_div = 1;
2166 + break;
2167 + }
2168 +
2169 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2170 + cpu_div = cpu_div * 2 ?: 1;
2171 +
2172 + return pllc_out / (clk_div * cpu_div);
2173 +}
2174 +
2175 +static inline unsigned ar2315_cpu_frequency(void)
2176 +{
2177 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2178 +}
2179 +
2180 +static inline unsigned ar2315_apb_frequency(void)
2181 +{
2182 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2183 +}
2184 +
2185 +void __init ar2315_plat_time_init(void)
2186 +{
2187 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2188 +}
2189 +
2190 +void __init ar2315_plat_mem_setup(void)
2191 +{
2192 + u32 memsize, memcfg;
2193 + u32 devid;
2194 + u32 config;
2195 +
2196 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2197 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2198 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2199 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2200 + memsize <<= 3;
2201 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2202 +
2203 + /* Detect the hardware based on the device ID */
2204 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2205 + switch (devid) {
2206 + case 0x91: /* Need to check */
2207 + ath25_soc = ATH25_SOC_AR2318;
2208 + break;
2209 + case 0x90:
2210 + ath25_soc = ATH25_SOC_AR2317;
2211 + break;
2212 + case 0x87:
2213 + ath25_soc = ATH25_SOC_AR2316;
2214 + break;
2215 + case 0x86:
2216 + default:
2217 + ath25_soc = ATH25_SOC_AR2315;
2218 + break;
2219 + }
2220 + ath25_board.devid = devid;
2221 +
2222 + /* Clear any lingering AHB errors */
2223 + config = read_c0_config();
2224 + write_c0_config(config & ~0x3);
2225 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2226 + ar231x_read_reg(AR2315_AHB_ERR1);
2227 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2228 +
2229 + _machine_restart = ar2315_restart;
2230 +}
2231 +
2232 +void __init ar2315_arch_init(void)
2233 +{
2234 + ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2235 + ar2315_apb_frequency());
2236 +}
2237 --- /dev/null
2238 +++ b/arch/mips/ath25/ar2315.h
2239 @@ -0,0 +1,36 @@
2240 +#ifndef __AR2315_H
2241 +#define __AR2315_H
2242 +
2243 +#ifdef CONFIG_SOC_AR2315
2244 +
2245 +void ar2315_arch_init_irq(void);
2246 +void ar2315_init_devices(void);
2247 +void ar2315_plat_time_init(void);
2248 +void ar2315_plat_mem_setup(void);
2249 +void ar2315_arch_init(void);
2250 +
2251 +#else
2252 +
2253 +static inline void ar2315_arch_init_irq(void)
2254 +{
2255 +}
2256 +
2257 +static inline void ar2315_init_devices(void)
2258 +{
2259 +}
2260 +
2261 +static inline void ar2315_plat_time_init(void)
2262 +{
2263 +}
2264 +
2265 +static inline void ar2315_plat_mem_setup(void)
2266 +{
2267 +}
2268 +
2269 +static inline void ar2315_arch_init(void)
2270 +{
2271 +}
2272 +
2273 +#endif
2274 +
2275 +#endif
2276 --- /dev/null
2277 +++ b/arch/mips/ath25/ar5312.h
2278 @@ -0,0 +1,36 @@
2279 +#ifndef __AR5312_H
2280 +#define __AR5312_H
2281 +
2282 +#ifdef CONFIG_SOC_AR5312
2283 +
2284 +void ar5312_arch_init_irq(void);
2285 +void ar5312_init_devices(void);
2286 +void ar5312_plat_time_init(void);
2287 +void ar5312_plat_mem_setup(void);
2288 +void ar5312_arch_init(void);
2289 +
2290 +#else
2291 +
2292 +static inline void ar5312_arch_init_irq(void)
2293 +{
2294 +}
2295 +
2296 +static inline void ar5312_init_devices(void)
2297 +{
2298 +}
2299 +
2300 +static inline void ar5312_plat_time_init(void)
2301 +{
2302 +}
2303 +
2304 +static inline void ar5312_plat_mem_setup(void)
2305 +{
2306 +}
2307 +
2308 +static inline void ar5312_arch_init(void)
2309 +{
2310 +}
2311 +
2312 +#endif
2313 +
2314 +#endif
2315 --- /dev/null
2316 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2317 @@ -0,0 +1,38 @@
2318 +#ifndef __ASM_MACH_ATH25_AR231X_H
2319 +#define __ASM_MACH_ATH25_AR231X_H
2320 +
2321 +#include <linux/types.h>
2322 +#include <linux/io.h>
2323 +
2324 +#define AR231X_MISC_IRQ_BASE 0x20
2325 +#define AR231X_GPIO_IRQ_BASE 0x30
2326 +
2327 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2328 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2329 +
2330 +static inline u32
2331 +ar231x_read_reg(u32 reg)
2332 +{
2333 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2334 +}
2335 +
2336 +static inline void
2337 +ar231x_write_reg(u32 reg, u32 val)
2338 +{
2339 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2340 +}
2341 +
2342 +static inline u32
2343 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2344 +{
2345 + u32 ret;
2346 +
2347 + ret = ar231x_read_reg(reg);
2348 + ret &= ~mask;
2349 + ret |= val;
2350 + ar231x_write_reg(reg, ret);
2351 +
2352 + return ret;
2353 +}
2354 +
2355 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2356 --- /dev/null
2357 +++ b/arch/mips/ath25/devices.h
2358 @@ -0,0 +1,39 @@
2359 +#ifndef __ATH25_DEVICES_H
2360 +#define __ATH25_DEVICES_H
2361 +
2362 +enum ath25_soc_type {
2363 + /* handled by ar5312.c */
2364 + ATH25_SOC_AR2312,
2365 + ATH25_SOC_AR2313,
2366 + ATH25_SOC_AR5312,
2367 +
2368 + /* handled by ar2315.c */
2369 + ATH25_SOC_AR2315,
2370 + ATH25_SOC_AR2316,
2371 + ATH25_SOC_AR2317,
2372 + ATH25_SOC_AR2318,
2373 +
2374 + ATH25_SOC_UNKNOWN
2375 +};
2376 +
2377 +extern enum ath25_soc_type ath25_soc;
2378 +extern struct ar231x_board_config ath25_board;
2379 +extern void (*ath25_irq_dispatch)(void);
2380 +
2381 +int ath25_find_config(u8 *flash_limit);
2382 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2383 + int irq, void *pdata);
2384 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2385 +int ath25_add_wmac(int nr, u32 base, int irq);
2386 +
2387 +static inline bool is_ar2315(void)
2388 +{
2389 + return (current_cpu_data.cputype == CPU_4KEC);
2390 +}
2391 +
2392 +static inline bool is_ar5312(void)
2393 +{
2394 + return !is_ar2315();
2395 +}
2396 +
2397 +#endif
2398 --- /dev/null
2399 +++ b/arch/mips/ath25/devices.c
2400 @@ -0,0 +1,192 @@
2401 +#include <linux/kernel.h>
2402 +#include <linux/init.h>
2403 +#include <linux/serial.h>
2404 +#include <linux/serial_core.h>
2405 +#include <linux/serial_8250.h>
2406 +#include <linux/platform_device.h>
2407 +#include <asm/bootinfo.h>
2408 +
2409 +#include <ath25_platform.h>
2410 +#include <ar231x.h>
2411 +#include "devices.h"
2412 +#include "ar5312.h"
2413 +#include "ar2315.h"
2414 +
2415 +struct ar231x_board_config ath25_board;
2416 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2417 +
2418 +static struct resource ath25_eth0_res[] = {
2419 + {
2420 + .name = "eth0_membase",
2421 + .flags = IORESOURCE_MEM,
2422 + },
2423 + {
2424 + .name = "eth0_mii",
2425 + .flags = IORESOURCE_MEM,
2426 + },
2427 + {
2428 + .name = "eth0_irq",
2429 + .flags = IORESOURCE_IRQ,
2430 + }
2431 +};
2432 +
2433 +static struct resource ath25_eth1_res[] = {
2434 + {
2435 + .name = "eth1_membase",
2436 + .flags = IORESOURCE_MEM,
2437 + },
2438 + {
2439 + .name = "eth1_mii",
2440 + .flags = IORESOURCE_MEM,
2441 + },
2442 + {
2443 + .name = "eth1_irq",
2444 + .flags = IORESOURCE_IRQ,
2445 + }
2446 +};
2447 +
2448 +static struct platform_device ath25_eth[] = {
2449 + {
2450 + .id = 0,
2451 + .name = "ar231x-eth",
2452 + .resource = ath25_eth0_res,
2453 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
2454 + },
2455 + {
2456 + .id = 1,
2457 + .name = "ar231x-eth",
2458 + .resource = ath25_eth1_res,
2459 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
2460 + }
2461 +};
2462 +
2463 +static struct resource ath25_wmac0_res[] = {
2464 + {
2465 + .name = "wmac0_membase",
2466 + .flags = IORESOURCE_MEM,
2467 + },
2468 + {
2469 + .name = "wmac0_irq",
2470 + .flags = IORESOURCE_IRQ,
2471 + }
2472 +};
2473 +
2474 +static struct resource ath25_wmac1_res[] = {
2475 + {
2476 + .name = "wmac1_membase",
2477 + .flags = IORESOURCE_MEM,
2478 + },
2479 + {
2480 + .name = "wmac1_irq",
2481 + .flags = IORESOURCE_IRQ,
2482 + }
2483 +};
2484 +
2485 +static struct platform_device ath25_wmac[] = {
2486 + {
2487 + .id = 0,
2488 + .name = "ar231x-wmac",
2489 + .resource = ath25_wmac0_res,
2490 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2491 + .dev.platform_data = &ath25_board,
2492 + },
2493 + {
2494 + .id = 1,
2495 + .name = "ar231x-wmac",
2496 + .resource = ath25_wmac1_res,
2497 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2498 + .dev.platform_data = &ath25_board,
2499 + },
2500 +};
2501 +
2502 +static const char * const soc_type_strings[] = {
2503 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2504 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2505 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2506 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2507 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2508 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2509 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2510 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2511 +};
2512 +
2513 +const char *get_system_type(void)
2514 +{
2515 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2516 + !soc_type_strings[ath25_soc])
2517 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2518 + return soc_type_strings[ath25_soc];
2519 +}
2520 +
2521 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
2522 + u32 mii_base, int irq, void *pdata)
2523 +{
2524 + struct resource *res;
2525 +
2526 + ath25_eth[nr].dev.platform_data = pdata;
2527 + res = &ath25_eth[nr].resource[0];
2528 + res->start = base;
2529 + res->end = base + 0x2000 - 1;
2530 + res++;
2531 + res->name = mii_name;
2532 + res->start = mii_base;
2533 + res->end = mii_base + 8 - 1;
2534 + res++;
2535 + res->start = irq;
2536 + res->end = irq;
2537 + return platform_device_register(&ath25_eth[nr]);
2538 +}
2539 +
2540 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2541 +{
2542 + struct uart_port s;
2543 +
2544 + memset(&s, 0, sizeof(s));
2545 +
2546 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2547 + s.iotype = UPIO_MEM32;
2548 + s.irq = irq;
2549 + s.regshift = 2;
2550 + s.mapbase = mapbase;
2551 + s.uartclk = uartclk;
2552 +
2553 + early_serial_setup(&s);
2554 +}
2555 +
2556 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2557 +{
2558 + struct resource *res;
2559 +
2560 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2561 + res = &ath25_wmac[nr].resource[0];
2562 + res->start = base;
2563 + res->end = base + 0x10000 - 1;
2564 + res++;
2565 + res->start = irq;
2566 + res->end = irq;
2567 + return platform_device_register(&ath25_wmac[nr]);
2568 +}
2569 +
2570 +static int __init ath25_register_devices(void)
2571 +{
2572 + if (is_ar5312())
2573 + ar5312_init_devices();
2574 + else
2575 + ar2315_init_devices();
2576 +
2577 + return 0;
2578 +}
2579 +
2580 +device_initcall(ath25_register_devices);
2581 +
2582 +static int __init ath25_arch_init(void)
2583 +{
2584 + if (is_ar5312())
2585 + ar5312_arch_init();
2586 + else
2587 + ar2315_arch_init();
2588 +
2589 + return 0;
2590 +}
2591 +
2592 +arch_initcall(ath25_arch_init);
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