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atheros: v3.18: remove eth platform device unused field
[openwrt/staging/wigyori.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ath25/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
352 @@ -0,0 +1,84 @@
353 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
354 +#define __ASM_MACH_ATH25_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + char *macaddr;
434 +};
435 +
436 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
437 --- /dev/null
438 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
439 @@ -0,0 +1,84 @@
440 +/*
441 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
442 + *
443 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
444 + *
445 + * This file was derived from: include/asm-mips/cpu-features.h
446 + * Copyright (C) 2003, 2004 Ralf Baechle
447 + * Copyright (C) 2004 Maciej W. Rozycki
448 + *
449 + * This program is free software; you can redistribute it and/or modify it
450 + * under the terms of the GNU General Public License version 2 as published
451 + * by the Free Software Foundation.
452 + *
453 + */
454 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
455 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
456 +
457 +/*
458 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
459 + */
460 +#define cpu_has_tlb 1
461 +#define cpu_has_4kex 1
462 +#define cpu_has_3k_cache 0
463 +#define cpu_has_4k_cache 1
464 +#define cpu_has_tx39_cache 0
465 +#define cpu_has_sb1_cache 0
466 +#define cpu_has_fpu 0
467 +#define cpu_has_32fpr 0
468 +#define cpu_has_counter 1
469 +/* #define cpu_has_watch ? */
470 +/* #define cpu_has_divec ? */
471 +/* #define cpu_has_vce ? */
472 +/* #define cpu_has_cache_cdex_p ? */
473 +/* #define cpu_has_cache_cdex_s ? */
474 +/* #define cpu_has_prefetch ? */
475 +/* #define cpu_has_mcheck ? */
476 +#define cpu_has_ejtag 1
477 +
478 +#if !defined(CONFIG_SOC_AR5312)
479 +# define cpu_has_llsc 1
480 +#else
481 +/*
482 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
483 + * ll/sc instructions.
484 + */
485 +# define cpu_has_llsc 0
486 +#endif
487 +
488 +#define cpu_has_mips16 0
489 +#define cpu_has_mdmx 0
490 +#define cpu_has_mips3d 0
491 +#define cpu_has_smartmips 0
492 +
493 +/* #define cpu_has_vtag_icache ? */
494 +/* #define cpu_has_dc_aliases ? */
495 +/* #define cpu_has_ic_fills_f_dc ? */
496 +/* #define cpu_has_pindexed_dcache ? */
497 +
498 +/* #define cpu_icache_snoops_remote_store ? */
499 +
500 +#define cpu_has_mips32r1 1
501 +
502 +#if !defined(CONFIG_SOC_AR5312)
503 +# define cpu_has_mips32r2 1
504 +#endif
505 +
506 +#define cpu_has_mips64r1 0
507 +#define cpu_has_mips64r2 0
508 +
509 +#define cpu_has_dsp 0
510 +#define cpu_has_mipsmt 0
511 +
512 +/* #define cpu_has_nofpuex ? */
513 +#define cpu_has_64bits 0
514 +#define cpu_has_64bit_zero_reg 0
515 +#define cpu_has_64bit_gp_regs 0
516 +#define cpu_has_64bit_addresses 0
517 +
518 +/* #define cpu_has_inclusive_pcaches ? */
519 +
520 +/* #define cpu_dcache_line_size() ? */
521 +/* #define cpu_icache_line_size() ? */
522 +
523 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
524 --- /dev/null
525 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
526 @@ -0,0 +1,76 @@
527 +/*
528 + * This file is subject to the terms and conditions of the GNU General Public
529 + * License. See the file "COPYING" in the main directory of this archive
530 + * for more details.
531 + *
532 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
533 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
534 + *
535 + */
536 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
537 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
538 +
539 +#include <linux/device.h>
540 +#include <ar2315_regs.h>
541 +
542 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
543 +{
544 +#ifdef CONFIG_PCI
545 + extern struct bus_type pci_bus_type;
546 +
547 + if (dev && dev->bus == &pci_bus_type)
548 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
549 +#endif
550 + return 0;
551 +}
552 +
553 +static inline dma_addr_t
554 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
555 +{
556 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
557 +}
558 +
559 +static inline dma_addr_t
560 +plat_map_dma_mem_page(struct device *dev, struct page *page)
561 +{
562 + return page_to_phys(page) + ar231x_dev_offset(dev);
563 +}
564 +
565 +static inline unsigned long
566 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
567 +{
568 + return dma_addr - ar231x_dev_offset(dev);
569 +}
570 +
571 +static inline void
572 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
573 + enum dma_data_direction direction)
574 +{
575 +}
576 +
577 +static inline int plat_dma_supported(struct device *dev, u64 mask)
578 +{
579 + return 1;
580 +}
581 +
582 +static inline void plat_extra_sync_for_device(struct device *dev)
583 +{
584 +}
585 +
586 +static inline int plat_dma_mapping_error(struct device *dev,
587 + dma_addr_t dma_addr)
588 +{
589 + return 0;
590 +}
591 +
592 +static inline int plat_device_is_coherent(struct device *dev)
593 +{
594 +#ifdef CONFIG_DMA_COHERENT
595 + return 1;
596 +#endif
597 +#ifdef CONFIG_DMA_NONCOHERENT
598 + return 0;
599 +#endif
600 +}
601 +
602 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
603 --- /dev/null
604 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
605 @@ -0,0 +1,16 @@
606 +#ifndef __ASM_MACH_ATH25_GPIO_H
607 +#define __ASM_MACH_ATH25_GPIO_H
608 +
609 +#include <asm-generic/gpio.h>
610 +
611 +#define gpio_get_value __gpio_get_value
612 +#define gpio_set_value __gpio_set_value
613 +#define gpio_cansleep __gpio_cansleep
614 +#define gpio_to_irq __gpio_to_irq
615 +
616 +static inline int irq_to_gpio(unsigned irq)
617 +{
618 + return -EINVAL;
619 +}
620 +
621 +#endif /* __ASM_MACH_ATH25_GPIO_H */
622 --- /dev/null
623 +++ b/arch/mips/include/asm/mach-ath25/war.h
624 @@ -0,0 +1,25 @@
625 +/*
626 + * This file is subject to the terms and conditions of the GNU General Public
627 + * License. See the file "COPYING" in the main directory of this archive
628 + * for more details.
629 + *
630 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
631 + */
632 +#ifndef __ASM_MACH_ATH25_WAR_H
633 +#define __ASM_MACH_ATH25_WAR_H
634 +
635 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
636 +#define R4600_V1_HIT_CACHEOP_WAR 0
637 +#define R4600_V2_HIT_CACHEOP_WAR 0
638 +#define R5432_CP0_INTERRUPT_WAR 0
639 +#define BCM1250_M3_WAR 0
640 +#define SIBYTE_1956_WAR 0
641 +#define MIPS4K_ICACHE_REFILL_WAR 0
642 +#define MIPS_CACHE_SYNC_WAR 0
643 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
644 +#define RM9000_CDEX_SMP_WAR 0
645 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
646 +#define R10000_LLSC_WAR 0
647 +#define MIPS34K_MISSED_ITLB_WAR 0
648 +
649 +#endif /* __ASM_MACH_ATH25_WAR_H */
650 --- /dev/null
651 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
652 @@ -0,0 +1,608 @@
653 +/*
654 + * Register definitions for AR2315+
655 + *
656 + * This file is subject to the terms and conditions of the GNU General Public
657 + * License. See the file "COPYING" in the main directory of this archive
658 + * for more details.
659 + *
660 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
661 + * Copyright (C) 2006 FON Technology, SL.
662 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
663 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
664 + */
665 +
666 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
667 +#define __ASM_MACH_ATH25_AR2315_REGS_H
668 +
669 +/*
670 + * IRQs
671 + */
672 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
673 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
674 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
675 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
676 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
677 +
678 +/*
679 + * Miscellaneous interrupts, which share IP2.
680 + */
681 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
682 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
683 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
684 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
685 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
686 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
687 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
688 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
689 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
690 +#define AR2315_MISC_IRQ_COUNT 9
691 +
692 +/*
693 + * PCI interrupts, which share IP5
694 + * Keep ordered according to AR2315_PCI_INT_XXX bits
695 + */
696 +#define AR2315_PCI_IRQ_BASE 0x50
697 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
698 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
699 +#define AR2315_PCI_IRQ_COUNT 2
700 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
701 +
702 +/*
703 + * Address map
704 + */
705 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
706 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
707 +#define AR2315_PCI 0x10100000 /* PCI MMR */
708 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
709 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
710 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
711 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
712 +#define AR2315_UART0 0x11100000 /* UART MMR */
713 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
714 +#define AR2315_PCIEXT 0x80000000 /* pci external */
715 +#define AR2315_PCIEXT_SZ 0x40000000
716 +
717 +/* MII registers offset inside Ethernet MMR region */
718 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
719 +
720 +/*
721 + * Cold reset register
722 + */
723 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
724 +
725 +#define AR2315_RESET_COLD_AHB 0x00000001
726 +#define AR2315_RESET_COLD_APB 0x00000002
727 +#define AR2315_RESET_COLD_CPU 0x00000004
728 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
729 +#define AR2315_RESET_SYSTEM \
730 + (RESET_COLD_CPU |\
731 + RESET_COLD_APB |\
732 + RESET_COLD_AHB) /* full system */
733 +#define AR2317_RESET_SYSTEM 0x00000010
734 +
735 +/*
736 + * Reset register
737 + */
738 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
739 +
740 +/* warm reset WLAN0 MAC */
741 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
742 +/* warm reset WLAN0 BaseBand */
743 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
744 +/* warm reset MPEG-TS */
745 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
746 +/* warm reset PCI ahb/dma */
747 +#define AR2315_RESET_PCIDMA 0x00000008
748 +/* warm reset memory controller */
749 +#define AR2315_RESET_MEMCTL 0x00000010
750 +/* warm reset local bus */
751 +#define AR2315_RESET_LOCAL 0x00000020
752 +/* warm reset I2C bus */
753 +#define AR2315_RESET_I2C_RSVD 0x00000040
754 +/* warm reset SPI interface */
755 +#define AR2315_RESET_SPI 0x00000080
756 +/* warm reset UART0 */
757 +#define AR2315_RESET_UART0 0x00000100
758 +/* warm reset IR interface */
759 +#define AR2315_RESET_IR_RSVD 0x00000200
760 +/* cold reset ENET0 phy */
761 +#define AR2315_RESET_EPHY0 0x00000400
762 +/* cold reset ENET0 mac */
763 +#define AR2315_RESET_ENET0 0x00000800
764 +
765 +/*
766 + * AHB master arbitration control
767 + */
768 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
769 +
770 +/* CPU, default */
771 +#define AR2315_ARB_CPU 0x00000001
772 +/* WLAN */
773 +#define AR2315_ARB_WLAN 0x00000002
774 +/* MPEG-TS */
775 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
776 +/* LOCAL */
777 +#define AR2315_ARB_LOCAL 0x00000008
778 +/* PCI */
779 +#define AR2315_ARB_PCI 0x00000010
780 +/* Ethernet */
781 +#define AR2315_ARB_ETHERNET 0x00000020
782 +/* retry policy, debug only */
783 +#define AR2315_ARB_RETRY 0x00000100
784 +
785 +/*
786 + * Config Register
787 + */
788 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
789 +
790 +/* EC - AHB bridge endianess */
791 +#define AR2315_CONFIG_AHB 0x00000001
792 +/* WLAN byteswap */
793 +#define AR2315_CONFIG_WLAN 0x00000002
794 +/* MPEG-TS byteswap */
795 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
796 +/* PCI byteswap */
797 +#define AR2315_CONFIG_PCI 0x00000008
798 +/* Memory controller endianess */
799 +#define AR2315_CONFIG_MEMCTL 0x00000010
800 +/* Local bus byteswap */
801 +#define AR2315_CONFIG_LOCAL 0x00000020
802 +/* Ethernet byteswap */
803 +#define AR2315_CONFIG_ETHERNET 0x00000040
804 +
805 +/* CPU write buffer merge */
806 +#define AR2315_CONFIG_MERGE 0x00000200
807 +/* CPU big endian */
808 +#define AR2315_CONFIG_CPU 0x00000400
809 +#define AR2315_CONFIG_PCIAHB 0x00000800
810 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
811 +/* SPI byteswap */
812 +#define AR2315_CONFIG_SPI 0x00008000
813 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
814 +#define AR2315_CONFIG_CPU_PCI 0x00020000
815 +#define AR2315_CONFIG_CPU_MMR 0x00040000
816 +#define AR2315_CONFIG_BIG 0x00000400
817 +
818 +/*
819 + * NMI control
820 + */
821 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
822 +
823 +#define AR2315_NMI_EN 1
824 +
825 +/*
826 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
827 + */
828 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
829 +
830 +#define AR2315_REV_MAJ 0x00f0
831 +#define AR2315_REV_MAJ_S 4
832 +#define AR2315_REV_MIN 0x000f
833 +#define AR2315_REV_MIN_S 0
834 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
835 +
836 +/*
837 + * Interface Enable
838 + */
839 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
840 +
841 +#define AR2315_IF_MASK 0x00000007
842 +#define AR2315_IF_DISABLED 0
843 +#define AR2315_IF_PCI 1
844 +#define AR2315_IF_TS_LOCAL 2
845 +/* only for emulation with separate pins */
846 +#define AR2315_IF_ALL 3
847 +#define AR2315_IF_LOCAL_HOST 0x00000008
848 +#define AR2315_IF_PCI_HOST 0x00000010
849 +#define AR2315_IF_PCI_INTR 0x00000020
850 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
851 +#define AR2315_IF_PCI_CLK_INPUT 0
852 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
853 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
854 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
855 +#define AR2315_IF_PCI_CLK_SHIFT 16
856 +
857 +/*
858 + * APB Interrupt control
859 + */
860 +
861 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
862 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
863 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
864 +
865 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
866 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
867 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
868 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
869 +#define AR2315_ISR_APB 0x0010 /* APB error */
870 +#define AR2315_ISR_TIMER 0x0020 /* timer */
871 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
872 +#define AR2315_ISR_WD 0x0080 /* watchdog */
873 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
874 +
875 +#define AR2315_GISR_MISC 0x0001
876 +#define AR2315_GISR_WLAN0 0x0002
877 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
878 +#define AR2315_GISR_LOCALPCI 0x0008
879 +#define AR2315_GISR_WMACPOLL 0x0010
880 +#define AR2315_GISR_TIMER 0x0020
881 +#define AR2315_GISR_ETHERNET 0x0040
882 +
883 +/*
884 + * Interrupt routing from IO to the processor IP bits
885 + * Define our inter mask and level
886 + */
887 +#define AR2315_INTR_MISCIO SR_IBIT3
888 +#define AR2315_INTR_WLAN0 SR_IBIT4
889 +#define AR2315_INTR_ENET0 SR_IBIT5
890 +#define AR2315_INTR_LOCALPCI SR_IBIT6
891 +#define AR2315_INTR_WMACPOLL SR_IBIT7
892 +#define AR2315_INTR_COMPARE SR_IBIT8
893 +
894 +/*
895 + * Timers
896 + */
897 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
898 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
899 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
900 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
901 +
902 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
903 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
904 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
905 +
906 +/*
907 + * CPU Performance Counters
908 + */
909 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
910 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
911 +
912 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
913 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
914 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
915 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
916 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
917 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
918 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
919 +
920 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
921 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
922 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
923 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
924 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
925 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
926 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
927 +
928 +/*
929 + * AHB Error Reporting.
930 + */
931 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
932 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
933 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
934 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
935 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
936 +
937 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
938 + /* write 1 to clear all bits in ERR0 */
939 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
940 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
941 +
942 +#define AR2315_PROCERR_HMAST 0x0000000f
943 +#define AR2315_PROCERR_HMAST_DFLT 0
944 +#define AR2315_PROCERR_HMAST_WMAC 1
945 +#define AR2315_PROCERR_HMAST_ENET 2
946 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
947 +#define AR2315_PROCERR_HMAST_LOCAL 4
948 +#define AR2315_PROCERR_HMAST_CPU 5
949 +#define AR2315_PROCERR_HMAST_PCITGT 6
950 +
951 +#define AR2315_PROCERR_HMAST_S 0
952 +#define AR2315_PROCERR_HWRITE 0x00000010
953 +#define AR2315_PROCERR_HSIZE 0x00000060
954 +#define AR2315_PROCERR_HSIZE_S 5
955 +#define AR2315_PROCERR_HTRANS 0x00000180
956 +#define AR2315_PROCERR_HTRANS_S 7
957 +#define AR2315_PROCERR_HBURST 0x00000e00
958 +#define AR2315_PROCERR_HBURST_S 9
959 +
960 +/*
961 + * Clock Control
962 + */
963 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
964 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
965 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
966 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
967 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
968 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
969 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
970 +
971 +/* PLLc Control fields */
972 +#define PLLC_REF_DIV_M 0x00000003
973 +#define PLLC_REF_DIV_S 0
974 +#define PLLC_FDBACK_DIV_M 0x0000007C
975 +#define PLLC_FDBACK_DIV_S 2
976 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
977 +#define PLLC_ADD_FDBACK_DIV_S 7
978 +#define PLLC_CLKC_DIV_M 0x0001c000
979 +#define PLLC_CLKC_DIV_S 14
980 +#define PLLC_CLKM_DIV_M 0x00700000
981 +#define PLLC_CLKM_DIV_S 20
982 +
983 +/* CPU CLK Control fields */
984 +#define CPUCLK_CLK_SEL_M 0x00000003
985 +#define CPUCLK_CLK_SEL_S 0
986 +#define CPUCLK_CLK_DIV_M 0x0000000c
987 +#define CPUCLK_CLK_DIV_S 2
988 +
989 +/* AMBA CLK Control fields */
990 +#define AMBACLK_CLK_SEL_M 0x00000003
991 +#define AMBACLK_CLK_SEL_S 0
992 +#define AMBACLK_CLK_DIV_M 0x0000000c
993 +#define AMBACLK_CLK_DIV_S 2
994 +
995 +/* GPIO MMR base address */
996 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
997 +
998 +#define AR2315_RESET_GPIO 5
999 +
1000 +/*
1001 + * PCI Clock Control
1002 + */
1003 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1004 +
1005 +#define AR2315_PCICLK_INPUT_M 0x3
1006 +#define AR2315_PCICLK_INPUT_S 0
1007 +
1008 +#define AR2315_PCICLK_PLLC_CLKM 0
1009 +#define AR2315_PCICLK_PLLC_CLKM1 1
1010 +#define AR2315_PCICLK_PLLC_CLKC 2
1011 +#define AR2315_PCICLK_REF_CLK 3
1012 +
1013 +#define AR2315_PCICLK_DIV_M 0xc
1014 +#define AR2315_PCICLK_DIV_S 2
1015 +
1016 +#define AR2315_PCICLK_IN_FREQ 0
1017 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1018 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1019 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1020 +
1021 +/*
1022 + * Observation Control Register
1023 + */
1024 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1025 +#define OCR_GPIO0_IRIN 0x0040
1026 +#define OCR_GPIO1_IROUT 0x0080
1027 +#define OCR_GPIO3_RXCLR 0x0200
1028 +
1029 +/*
1030 + * General Clock Control
1031 + */
1032 +
1033 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1034 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1035 +#define MISCCLK_PROCREFCLK 0x00000002
1036 +
1037 +/*
1038 + * SDRAM Controller
1039 + * - No read or write buffers are included.
1040 + */
1041 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1042 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1043 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1044 +
1045 +#define SDRAM_DATA_WIDTH_M 0x00006000
1046 +#define SDRAM_DATA_WIDTH_S 13
1047 +
1048 +#define SDRAM_COL_WIDTH_M 0x00001E00
1049 +#define SDRAM_COL_WIDTH_S 9
1050 +
1051 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1052 +#define SDRAM_ROW_WIDTH_S 5
1053 +
1054 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1055 +#define SDRAM_BANKADDR_BITS_S 3
1056 +
1057 +/*
1058 + * PCI Bus Interface Registers
1059 + */
1060 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1061 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1062 +
1063 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1064 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1065 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1066 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1067 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1068 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1069 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1070 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1071 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1072 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1073 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1074 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1075 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1076 + * disable */
1077 +
1078 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1079 +
1080 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1081 +
1082 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1083 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1084 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1085 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1086 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1087 +
1088 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1089 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1090 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1091 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1092 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1093 +
1094 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1095 +
1096 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1097 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1098 +
1099 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1100 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1101 +
1102 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1103 +
1104 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1105 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1106 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1107 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1108 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1109 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1110 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1111 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1112 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1113 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1114 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1115 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1116 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1117 +
1118 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1119 +
1120 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1121 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1122 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1123 +
1124 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1125 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1126 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1127 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1128 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1129 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1130 +
1131 +/*
1132 + * Local Bus Interface Registers
1133 + */
1134 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1135 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1136 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1137 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1138 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1139 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1140 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1141 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1142 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1143 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1144 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1145 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1146 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1147 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1148 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1149 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1150 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1151 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1152 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1153 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1154 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1155 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1156 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1157 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1158 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1159 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1160 +
1161 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1162 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1163 +
1164 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1165 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1166 +
1167 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1168 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1169 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1170 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1171 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1172 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1173 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1174 +#define AR2315_LBM_TIMEOUT_SHFT 7
1175 +#define AR2315_LBM_PORTMUX 0x07000000
1176 +
1177 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1178 +
1179 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1180 +#define AR2315_LB_TXEN_0 0x01
1181 +#define AR2315_LB_TXEN_1 0x02
1182 +#define AR2315_LB_TXEN_2 0x04
1183 +#define AR2315_LB_TXEN_3 0x08
1184 +
1185 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1186 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1187 +
1188 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1189 +#define AR2315_LB_RXEN 0x01
1190 +
1191 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1192 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1193 +
1194 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1195 +#define AR2315_INT_TX_DESC 0x0001
1196 +#define AR2315_INT_TX_OK 0x0002
1197 +#define AR2315_INT_TX_ERR 0x0004
1198 +#define AR2315_INT_TX_EOF 0x0008
1199 +#define AR2315_INT_RX_DESC 0x0010
1200 +#define AR2315_INT_RX_OK 0x0020
1201 +#define AR2315_INT_RX_ERR 0x0040
1202 +#define AR2315_INT_RX_EOF 0x0080
1203 +#define AR2315_INT_TX_TRUNC 0x0100
1204 +#define AR2315_INT_TX_STARVE 0x0200
1205 +#define AR2315_INT_LB_TIMEOUT 0x0400
1206 +#define AR2315_INT_LB_ERR 0x0800
1207 +#define AR2315_INT_MBOX_WR 0x1000
1208 +#define AR2315_INT_MBOX_RD 0x2000
1209 +
1210 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1211 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1212 +
1213 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1214 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1215 +
1216 +/*
1217 + * IR Interface Registers
1218 + */
1219 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1220 +
1221 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1222 +
1223 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1224 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1225 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1226 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1227 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1228 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1229 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1230 +
1231 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1232 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1233 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1234 +
1235 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1236 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1237 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1238 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1239 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1240 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1241 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1242 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1243 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1244 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1245 +
1246 +/*
1247 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1248 + * of PCI host controller to enable DMA. The same value should be used as the
1249 + * offset to calculate the physical address of DMA buffer for PCI devices.
1250 + */
1251 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1252 +
1253 +/* ??? access BAR */
1254 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1255 +/* RAM access BAR */
1256 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1257 +/* ??? access BAR */
1258 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1259 +
1260 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1261 --- /dev/null
1262 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1263 @@ -0,0 +1,235 @@
1264 +/*
1265 + * This file is subject to the terms and conditions of the GNU General Public
1266 + * License. See the file "COPYING" in the main directory of this archive
1267 + * for more details.
1268 + *
1269 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1270 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1271 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1272 + */
1273 +
1274 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1275 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1276 +
1277 +#include <asm/addrspace.h>
1278 +
1279 +/*
1280 + * IRQs
1281 + */
1282 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1283 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1284 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1285 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1286 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1287 +
1288 +/*
1289 + * Miscellaneous interrupts, which share IP6.
1290 + */
1291 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1292 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1293 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1294 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1295 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1296 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1297 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1298 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1299 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1300 +#define AR5312_MISC_IRQ_COUNT 9
1301 +
1302 +/*
1303 + * Address Map
1304 + */
1305 +#define AR5312_WLAN0 0x18000000
1306 +#define AR5312_WLAN1 0x18500000
1307 +#define AR5312_ENET0 0x18100000
1308 +#define AR5312_ENET1 0x18200000
1309 +#define AR5312_SDRAMCTL 0x18300000
1310 +#define AR5312_FLASHCTL 0x18400000
1311 +#define AR5312_APBBASE 0x1c000000
1312 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1313 +#define AR5312_FLASH 0x1e000000
1314 +
1315 +/*
1316 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1317 + * should be considered available. The AR5312 supports 2 enet MACS,
1318 + * even though many reference boards only actually use 1 of them
1319 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1320 + * The AR2312 supports 1 enet MAC.
1321 + */
1322 +#define AR5312_NUM_ENET_MAC 2
1323 +
1324 +/*
1325 + * Need these defines to determine true number of ethernet MACs
1326 + */
1327 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1328 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1329 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1330 +
1331 +/* MII registers offset inside Ethernet MMR region */
1332 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1333 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1334 +
1335 +/*
1336 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1337 + * should be considered available.
1338 + */
1339 +#define AR5312_NUM_WMAC 2
1340 +
1341 +/* Reset/Timer Block Address Map */
1342 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1343 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1344 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1345 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1346 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1347 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1348 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1349 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1350 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1351 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1352 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1353 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1354 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1355 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1356 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1357 +
1358 +/* AR5312_WD_CTRL register bit field definitions */
1359 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1360 +#define AR5312_WD_CTRL_NMI 0x0001
1361 +#define AR5312_WD_CTRL_RESET 0x0002
1362 +
1363 +/* AR5312_ISR register bit field definitions */
1364 +#define AR5312_ISR_TIMER 0x0001
1365 +#define AR5312_ISR_AHBPROC 0x0002
1366 +#define AR5312_ISR_AHBDMA 0x0004
1367 +#define AR5312_ISR_GPIO 0x0008
1368 +#define AR5312_ISR_UART0 0x0010
1369 +#define AR5312_ISR_UART0DMA 0x0020
1370 +#define AR5312_ISR_WD 0x0040
1371 +#define AR5312_ISR_LOCAL 0x0080
1372 +
1373 +/* AR5312_RESET register bit field definitions */
1374 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1375 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1376 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1377 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1378 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1379 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1380 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1381 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1382 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1383 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1384 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1385 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1386 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1387 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1388 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1389 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1390 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1391 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1392 +
1393 +#define AR5312_RESET_WMAC0_BITS \
1394 + (AR5312_RESET_WLAN0 |\
1395 + AR5312_RESET_WARM_WLAN0_MAC |\
1396 + AR5312_RESET_WARM_WLAN0_BB)
1397 +
1398 +#define AR5312_RESET_WMAC1_BITS \
1399 + (AR5312_RESET_WLAN1 |\
1400 + AR5312_RESET_WARM_WLAN1_MAC |\
1401 + AR5312_RESET_WARM_WLAN1_BB)
1402 +
1403 +/* AR5312_CLOCKCTL1 register bit field definitions */
1404 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1405 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1406 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1407 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1408 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1409 +
1410 +/* Valid for AR5312 and AR2312 */
1411 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1412 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1413 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1414 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1415 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1416 +
1417 +/* Valid for AR2313 */
1418 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1419 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1420 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1421 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1422 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1423 +
1424 +/* AR5312_ENABLE register bit field definitions */
1425 +#define AR5312_ENABLE_WLAN0 0x0001
1426 +#define AR5312_ENABLE_ENET0 0x0002
1427 +#define AR5312_ENABLE_ENET1 0x0004
1428 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1429 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1430 +#define AR5312_ENABLE_WLAN1 \
1431 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1432 + AR5312_ENABLE_WLAN1_DMA)
1433 +
1434 +/* AR5312_REV register bit field definitions */
1435 +#define AR5312_REV_WMAC_MAJ 0xf000
1436 +#define AR5312_REV_WMAC_MAJ_S 12
1437 +#define AR5312_REV_WMAC_MIN 0x0f00
1438 +#define AR5312_REV_WMAC_MIN_S 8
1439 +#define AR5312_REV_MAJ 0x00f0
1440 +#define AR5312_REV_MAJ_S 4
1441 +#define AR5312_REV_MIN 0x000f
1442 +#define AR5312_REV_MIN_S 0
1443 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1444 +
1445 +/* Major revision numbers, bits 7..4 of Revision ID register */
1446 +#define AR5312_REV_MAJ_AR5312 0x4
1447 +#define AR5312_REV_MAJ_AR2313 0x5
1448 +
1449 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1450 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1451 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1452 +
1453 +/* AR5312_FLASHCTL register bit field definitions */
1454 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1455 +#define FLASHCTL_IDCY_S 0
1456 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1457 +#define FLASHCTL_WST1_S 5
1458 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1459 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1460 +#define FLASHCTL_WST2_S 11
1461 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1462 +#define FLASHCTL_AC_S 16
1463 +#define FLASHCTL_AC_128K 0x00000000
1464 +#define FLASHCTL_AC_256K 0x00010000
1465 +#define FLASHCTL_AC_512K 0x00020000
1466 +#define FLASHCTL_AC_1M 0x00030000
1467 +#define FLASHCTL_AC_2M 0x00040000
1468 +#define FLASHCTL_AC_4M 0x00050000
1469 +#define FLASHCTL_AC_8M 0x00060000
1470 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1471 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1472 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1473 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1474 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1475 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1476 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1477 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1478 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1479 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1480 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1481 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1482 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1483 +
1484 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1485 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1486 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1487 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1488 +
1489 +/* ARM SDRAM Controller -- just enough to determine memory size */
1490 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1491 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1492 +#define MEM_CFG1_AC0_S 8
1493 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1494 +#define MEM_CFG1_AC1_S 12
1495 +
1496 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1497 +
1498 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1499 --- /dev/null
1500 +++ b/arch/mips/ath25/ar5312.c
1501 @@ -0,0 +1,474 @@
1502 +/*
1503 + * This file is subject to the terms and conditions of the GNU General Public
1504 + * License. See the file "COPYING" in the main directory of this archive
1505 + * for more details.
1506 + *
1507 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1508 + * Copyright (C) 2006 FON Technology, SL.
1509 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1510 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1511 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1512 + */
1513 +
1514 +/*
1515 + * Platform devices for Atheros SoCs
1516 + */
1517 +
1518 +#include <generated/autoconf.h>
1519 +#include <linux/init.h>
1520 +#include <linux/module.h>
1521 +#include <linux/types.h>
1522 +#include <linux/string.h>
1523 +#include <linux/mtd/physmap.h>
1524 +#include <linux/platform_device.h>
1525 +#include <linux/kernel.h>
1526 +#include <linux/reboot.h>
1527 +#include <linux/leds.h>
1528 +#include <linux/gpio.h>
1529 +#include <asm/bootinfo.h>
1530 +#include <asm/reboot.h>
1531 +#include <asm/time.h>
1532 +#include <linux/irq.h>
1533 +#include <linux/io.h>
1534 +
1535 +#include <ath25_platform.h>
1536 +#include <ar5312_regs.h>
1537 +#include <ar231x.h>
1538 +#include "devices.h"
1539 +#include "ar5312.h"
1540 +
1541 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1542 +{
1543 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1544 + ar231x_read_reg(AR5312_IMR);
1545 +
1546 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1547 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1548 + (void)ar231x_read_reg(AR5312_TIMER);
1549 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1550 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1551 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1552 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1553 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1554 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1555 + else
1556 + spurious_interrupt();
1557 +}
1558 +
1559 +static asmlinkage void
1560 +ar5312_irq_dispatch(void)
1561 +{
1562 + int pending = read_c0_status() & read_c0_cause();
1563 +
1564 + if (pending & CAUSEF_IP2)
1565 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1566 + else if (pending & CAUSEF_IP3)
1567 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1568 + else if (pending & CAUSEF_IP4)
1569 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1570 + else if (pending & CAUSEF_IP5)
1571 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1572 + else if (pending & CAUSEF_IP6)
1573 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1574 + else if (pending & CAUSEF_IP7)
1575 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1576 + else
1577 + spurious_interrupt();
1578 +}
1579 +
1580 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1581 +static void
1582 +ar5312_misc_irq_unmask(struct irq_data *d)
1583 +{
1584 + unsigned int imr;
1585 +
1586 + imr = ar231x_read_reg(AR5312_IMR);
1587 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1588 + ar231x_write_reg(AR5312_IMR, imr);
1589 +}
1590 +
1591 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1592 +static void
1593 +ar5312_misc_irq_mask(struct irq_data *d)
1594 +{
1595 + unsigned int imr;
1596 +
1597 + imr = ar231x_read_reg(AR5312_IMR);
1598 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1599 + ar231x_write_reg(AR5312_IMR, imr);
1600 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1601 +}
1602 +
1603 +static struct irq_chip ar5312_misc_irq_chip = {
1604 + .name = "AR5312-MISC",
1605 + .irq_unmask = ar5312_misc_irq_unmask,
1606 + .irq_mask = ar5312_misc_irq_mask,
1607 +};
1608 +
1609 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1610 +{
1611 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1612 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1613 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1614 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1615 +
1616 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1617 + proc_addr, proc1, dma_addr, dma1);
1618 +
1619 + machine_restart("AHB error"); /* Catastrophic failure */
1620 + return IRQ_HANDLED;
1621 +}
1622 +
1623 +static struct irqaction ar5312_ahb_proc_interrupt = {
1624 + .handler = ar5312_ahb_proc_handler,
1625 + .name = "ar5312_ahb_proc_interrupt",
1626 +};
1627 +
1628 +void __init ar5312_irq_init(void)
1629 +{
1630 + int i;
1631 +
1632 + if (!is_5312())
1633 + return;
1634 +
1635 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1636 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1637 + int irq = AR231X_MISC_IRQ_BASE + i;
1638 +
1639 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1640 + handle_level_irq);
1641 + }
1642 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1643 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1644 +}
1645 +
1646 +static void ar5312_device_reset_set(u32 mask)
1647 +{
1648 + u32 val;
1649 +
1650 + val = ar231x_read_reg(AR5312_RESET);
1651 + ar231x_write_reg(AR5312_RESET, val | mask);
1652 +}
1653 +
1654 +static void ar5312_device_reset_clear(u32 mask)
1655 +{
1656 + u32 val;
1657 +
1658 + val = ar231x_read_reg(AR5312_RESET);
1659 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1660 +}
1661 +
1662 +static struct physmap_flash_data ar5312_flash_data = {
1663 + .width = 2,
1664 +};
1665 +
1666 +static struct resource ar5312_flash_resource = {
1667 + .start = AR5312_FLASH,
1668 + .end = AR5312_FLASH + 0x800000 - 1,
1669 + .flags = IORESOURCE_MEM,
1670 +};
1671 +
1672 +static struct ar231x_eth ar5312_eth0_data = {
1673 + .reset_set = ar5312_device_reset_set,
1674 + .reset_clear = ar5312_device_reset_clear,
1675 + .reset_mac = AR5312_RESET_ENET0,
1676 + .reset_phy = AR5312_RESET_EPHY0,
1677 +};
1678 +
1679 +static struct ar231x_eth ar5312_eth1_data = {
1680 + .reset_set = ar5312_device_reset_set,
1681 + .reset_clear = ar5312_device_reset_clear,
1682 + .reset_mac = AR5312_RESET_ENET1,
1683 + .reset_phy = AR5312_RESET_EPHY1,
1684 +};
1685 +
1686 +static struct platform_device ar5312_physmap_flash = {
1687 + .name = "physmap-flash",
1688 + .id = 0,
1689 + .dev.platform_data = &ar5312_flash_data,
1690 + .resource = &ar5312_flash_resource,
1691 + .num_resources = 1,
1692 +};
1693 +
1694 +#ifdef CONFIG_LEDS_GPIO
1695 +static struct gpio_led ar5312_leds[] = {
1696 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1697 +};
1698 +
1699 +static const struct gpio_led_platform_data ar5312_led_data = {
1700 + .num_leds = ARRAY_SIZE(ar5312_leds),
1701 + .leds = (void *)ar5312_leds,
1702 +};
1703 +
1704 +static struct platform_device ar5312_gpio_leds = {
1705 + .name = "leds-gpio",
1706 + .id = -1,
1707 + .dev.platform_data = (void *)&ar5312_led_data,
1708 +};
1709 +#endif
1710 +
1711 +/*
1712 + * NB: This mapping size is larger than the actual flash size,
1713 + * but this shouldn't be a problem here, because the flash
1714 + * will simply be mapped multiple times.
1715 + */
1716 +static char __init *ar5312_flash_limit(void)
1717 +{
1718 + u32 ctl;
1719 + /*
1720 + * Configure flash bank 0.
1721 + * Assume 8M window size. Flash will be aliased if it's smaller
1722 + */
1723 + ctl = FLASHCTL_E |
1724 + FLASHCTL_AC_8M |
1725 + FLASHCTL_RBLE |
1726 + (0x01 << FLASHCTL_IDCY_S) |
1727 + (0x07 << FLASHCTL_WST1_S) |
1728 + (0x07 << FLASHCTL_WST2_S) |
1729 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1730 +
1731 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1732 +
1733 + /* Disable other flash banks */
1734 + ar231x_write_reg(AR5312_FLASHCTL1,
1735 + ar231x_read_reg(AR5312_FLASHCTL1) &
1736 + ~(FLASHCTL_E | FLASHCTL_AC));
1737 +
1738 + ar231x_write_reg(AR5312_FLASHCTL2,
1739 + ar231x_read_reg(AR5312_FLASHCTL2) &
1740 + ~(FLASHCTL_E | FLASHCTL_AC));
1741 +
1742 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1743 +}
1744 +
1745 +int __init ar5312_init_devices(void)
1746 +{
1747 + struct ar231x_boarddata *config;
1748 + u32 fctl = 0;
1749 + u8 *c;
1750 +
1751 + if (!is_5312())
1752 + return 0;
1753 +
1754 + /* Locate board/radio config data */
1755 + ar231x_find_config(ar5312_flash_limit());
1756 + config = ar231x_board.config;
1757 +
1758 + /* AR2313 has CPU minor rev. 10 */
1759 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1760 + ar231x_devtype = DEV_TYPE_AR2313;
1761 +
1762 + /* AR2312 shares the same Silicon ID as AR5312 */
1763 + else if (config->flags & BD_ISCASPER)
1764 + ar231x_devtype = DEV_TYPE_AR2312;
1765 +
1766 + /* Everything else is probably AR5312 or compatible */
1767 + else
1768 + ar231x_devtype = DEV_TYPE_AR5312;
1769 +
1770 + /* fixup flash width */
1771 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1772 + switch (fctl) {
1773 + case FLASHCTL_MW16:
1774 + ar5312_flash_data.width = 2;
1775 + break;
1776 + case FLASHCTL_MW8:
1777 + default:
1778 + ar5312_flash_data.width = 1;
1779 + break;
1780 + }
1781 +
1782 + platform_device_register(&ar5312_physmap_flash);
1783 +
1784 +#ifdef CONFIG_LEDS_GPIO
1785 + ar5312_leds[0].gpio = config->sys_led_gpio;
1786 + platform_device_register(&ar5312_gpio_leds);
1787 +#endif
1788 +
1789 + /* Fix up MAC addresses if necessary */
1790 + if (is_broadcast_ether_addr(config->enet0_mac))
1791 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1792 +
1793 + /* If ENET0 and ENET1 have the same mac address,
1794 + * increment the one from ENET1 */
1795 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1796 + c = config->enet1_mac + 5;
1797 + while ((c >= config->enet1_mac) && !(++(*c)))
1798 + c--;
1799 + }
1800 +
1801 + switch (ar231x_devtype) {
1802 + case DEV_TYPE_AR5312:
1803 + ar5312_eth0_data.macaddr = config->enet0_mac;
1804 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1805 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1806 + &ar5312_eth0_data);
1807 +
1808 + ar5312_eth1_data.macaddr = config->enet1_mac;
1809 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1810 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1811 + &ar5312_eth1_data);
1812 +
1813 + if (!ar231x_board.radio)
1814 + return 0;
1815 +
1816 + if (!(config->flags & BD_WLAN0))
1817 + break;
1818 +
1819 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1820 + break;
1821 + /*
1822 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1823 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1824 + */
1825 + case DEV_TYPE_AR2312:
1826 + case DEV_TYPE_AR2313:
1827 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1828 + ar5312_eth1_data.macaddr = config->enet0_mac;
1829 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1830 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1831 + &ar5312_eth1_data);
1832 +
1833 + if (!ar231x_board.radio)
1834 + return 0;
1835 + break;
1836 + default:
1837 + break;
1838 + }
1839 +
1840 + if (config->flags & BD_WLAN1)
1841 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1842 +
1843 + return 0;
1844 +}
1845 +
1846 +static void ar5312_restart(char *command)
1847 +{
1848 + /* reset the system */
1849 + local_irq_disable();
1850 + while (1)
1851 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1852 +}
1853 +
1854 +/*
1855 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1856 + * to determine the predevisor value.
1857 + */
1858 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1859 +
1860 +static int __init
1861 +ar5312_cpu_frequency(void)
1862 +{
1863 + unsigned int scratch;
1864 + unsigned int predivide_mask, predivide_shift;
1865 + unsigned int multiplier_mask, multiplier_shift;
1866 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1867 + unsigned int doubler_mask;
1868 + u16 devid;
1869 +
1870 + /* Trust the bootrom's idea of cpu frequency. */
1871 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1872 + if (scratch)
1873 + return scratch;
1874 +
1875 + devid = ar231x_read_reg(AR5312_REV);
1876 + devid &= AR5312_REV_MAJ;
1877 + devid >>= AR5312_REV_MAJ_S;
1878 + if (devid == AR5312_REV_MAJ_AR2313) {
1879 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1880 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1881 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1882 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1883 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1884 + } else { /* AR5312 and AR2312 */
1885 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1886 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1887 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1888 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1889 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1890 + }
1891 +
1892 + /*
1893 + * Clocking is derived from a fixed 40MHz input clock.
1894 + *
1895 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1896 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1897 + * flash, Timer, Watchdog Timer)
1898 + *
1899 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1900 + *
1901 + * So, for example, with a PLL multiplier of 5, we have
1902 + *
1903 + * cpu_freq = 200MHz
1904 + * sys_freq = 50MHz
1905 + * cnt_freq = 100MHz
1906 + *
1907 + * We compute the CPU frequency, based on PLL settings.
1908 + */
1909 +
1910 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1911 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1912 + predivisor = clockctl1_predivide_table[predivide_select];
1913 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1914 +
1915 + if (clock_ctl1 & doubler_mask)
1916 + multiplier = multiplier << 1;
1917 +
1918 + return (40000000 / predivisor) * multiplier;
1919 +}
1920 +
1921 +static inline int
1922 +ar5312_sys_frequency(void)
1923 +{
1924 + return ar5312_cpu_frequency() / 4;
1925 +}
1926 +
1927 +void __init
1928 +ar5312_time_init(void)
1929 +{
1930 + if (!is_5312())
1931 + return;
1932 +
1933 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1934 +}
1935 +
1936 +void __init
1937 +ar5312_prom_init(void)
1938 +{
1939 + u32 memsize, memcfg, bank0AC, bank1AC;
1940 + u32 devid;
1941 +
1942 + if (!is_5312())
1943 + return;
1944 +
1945 + /* Detect memory size */
1946 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1947 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1948 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1949 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1950 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1951 + memsize <<= 20;
1952 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1953 +
1954 + devid = ar231x_read_reg(AR5312_REV);
1955 + devid >>= AR5312_REV_WMAC_MIN_S;
1956 + devid &= AR5312_REV_CHIP;
1957 + ar231x_board.devid = (u16)devid;
1958 +}
1959 +
1960 +void __init
1961 +ar5312_plat_setup(void)
1962 +{
1963 + if (!is_5312())
1964 + return;
1965 +
1966 + /* Clear any lingering AHB errors */
1967 + ar231x_read_reg(AR5312_PROCADDR);
1968 + ar231x_read_reg(AR5312_DMAADDR);
1969 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1970 +
1971 + _machine_restart = ar5312_restart;
1972 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1973 + ar5312_sys_frequency());
1974 +}
1975 +
1976 --- /dev/null
1977 +++ b/arch/mips/ath25/ar2315.c
1978 @@ -0,0 +1,430 @@
1979 +/*
1980 + * This file is subject to the terms and conditions of the GNU General Public
1981 + * License. See the file "COPYING" in the main directory of this archive
1982 + * for more details.
1983 + *
1984 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1985 + * Copyright (C) 2006 FON Technology, SL.
1986 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1987 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1988 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1989 + */
1990 +
1991 +/*
1992 + * Platform devices for Atheros SoCs
1993 + */
1994 +
1995 +#include <generated/autoconf.h>
1996 +#include <linux/init.h>
1997 +#include <linux/module.h>
1998 +#include <linux/types.h>
1999 +#include <linux/string.h>
2000 +#include <linux/platform_device.h>
2001 +#include <linux/kernel.h>
2002 +#include <linux/reboot.h>
2003 +#include <linux/delay.h>
2004 +#include <linux/leds.h>
2005 +#include <linux/gpio.h>
2006 +#include <asm/bootinfo.h>
2007 +#include <asm/reboot.h>
2008 +#include <asm/time.h>
2009 +#include <linux/irq.h>
2010 +#include <linux/io.h>
2011 +
2012 +#include <ath25_platform.h>
2013 +#include <ar2315_regs.h>
2014 +#include <ar231x.h>
2015 +#include "devices.h"
2016 +#include "ar2315.h"
2017 +
2018 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2019 +{
2020 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2021 + ar231x_read_reg(AR2315_IMR);
2022 +
2023 + if (misc_intr & AR2315_ISR_SPI)
2024 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
2025 + else if (misc_intr & AR2315_ISR_TIMER)
2026 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
2027 + else if (misc_intr & AR2315_ISR_AHB)
2028 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
2029 + else if (misc_intr & AR2315_ISR_GPIO) {
2030 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2031 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
2032 + } else if (misc_intr & AR2315_ISR_UART0)
2033 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
2034 + else if (misc_intr & AR2315_ISR_WD) {
2035 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2036 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
2037 + } else
2038 + spurious_interrupt();
2039 +}
2040 +
2041 +/*
2042 + * Called when an interrupt is received, this function
2043 + * determines exactly which interrupt it was, and it
2044 + * invokes the appropriate handler.
2045 + *
2046 + * Implicitly, we also define interrupt priority by
2047 + * choosing which to dispatch first.
2048 + */
2049 +static asmlinkage void
2050 +ar2315_irq_dispatch(void)
2051 +{
2052 + int pending = read_c0_status() & read_c0_cause();
2053 +
2054 + if (pending & CAUSEF_IP3)
2055 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2056 + else if (pending & CAUSEF_IP4)
2057 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2058 + else if (pending & CAUSEF_IP2)
2059 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2060 + else if (pending & CAUSEF_IP7)
2061 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2062 + else
2063 + spurious_interrupt();
2064 +}
2065 +
2066 +static void
2067 +ar2315_misc_irq_unmask(struct irq_data *d)
2068 +{
2069 + unsigned int imr;
2070 +
2071 + imr = ar231x_read_reg(AR2315_IMR);
2072 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
2073 + ar231x_write_reg(AR2315_IMR, imr);
2074 +}
2075 +
2076 +static void
2077 +ar2315_misc_irq_mask(struct irq_data *d)
2078 +{
2079 + unsigned int imr;
2080 +
2081 + imr = ar231x_read_reg(AR2315_IMR);
2082 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
2083 + ar231x_write_reg(AR2315_IMR, imr);
2084 +}
2085 +
2086 +static struct irq_chip ar2315_misc_irq_chip = {
2087 + .name = "AR2315-MISC",
2088 + .irq_unmask = ar2315_misc_irq_unmask,
2089 + .irq_mask = ar2315_misc_irq_mask,
2090 +};
2091 +
2092 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2093 +{
2094 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2095 + ar231x_read_reg(AR2315_AHB_ERR1);
2096 +
2097 + pr_emerg("AHB fatal error\n");
2098 + machine_restart("AHB error"); /* Catastrophic failure */
2099 +
2100 + return IRQ_HANDLED;
2101 +}
2102 +
2103 +static struct irqaction ar2315_ahb_proc_interrupt = {
2104 + .handler = ar2315_ahb_proc_handler,
2105 + .name = "ar2315_ahb_proc_interrupt",
2106 +};
2107 +
2108 +void
2109 +ar2315_irq_init(void)
2110 +{
2111 + int i;
2112 +
2113 + if (!is_2315())
2114 + return;
2115 +
2116 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2117 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2118 + int irq = AR231X_MISC_IRQ_BASE + i;
2119 +
2120 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2121 + handle_level_irq);
2122 + }
2123 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2124 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2125 +}
2126 +
2127 +static void ar2315_device_reset_set(u32 mask)
2128 +{
2129 + u32 val;
2130 +
2131 + val = ar231x_read_reg(AR2315_RESET);
2132 + ar231x_write_reg(AR2315_RESET, val | mask);
2133 +}
2134 +
2135 +static void ar2315_device_reset_clear(u32 mask)
2136 +{
2137 + u32 val;
2138 +
2139 + val = ar231x_read_reg(AR2315_RESET);
2140 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2141 +}
2142 +
2143 +static struct ar231x_eth ar2315_eth_data = {
2144 + .reset_set = ar2315_device_reset_set,
2145 + .reset_clear = ar2315_device_reset_clear,
2146 + .reset_mac = AR2315_RESET_ENET0,
2147 + .reset_phy = AR2315_RESET_EPHY0,
2148 +};
2149 +
2150 +static struct resource ar2315_spiflash_res[] = {
2151 + {
2152 + .name = "spiflash_read",
2153 + .flags = IORESOURCE_MEM,
2154 + .start = AR2315_SPI_READ,
2155 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2156 + },
2157 + {
2158 + .name = "spiflash_mmr",
2159 + .flags = IORESOURCE_MEM,
2160 + .start = AR2315_SPI_MMR,
2161 + .end = AR2315_SPI_MMR + 12 - 1,
2162 + },
2163 +};
2164 +
2165 +static struct platform_device ar2315_spiflash = {
2166 + .id = 0,
2167 + .name = "ar2315-spiflash",
2168 + .resource = ar2315_spiflash_res,
2169 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2170 +};
2171 +
2172 +static struct resource ar2315_wdt_res[] = {
2173 + {
2174 + .flags = IORESOURCE_MEM,
2175 + .start = AR2315_WD,
2176 + .end = AR2315_WD + 8 - 1,
2177 + },
2178 + {
2179 + .flags = IORESOURCE_IRQ,
2180 + .start = AR2315_MISC_IRQ_WATCHDOG,
2181 + .end = AR2315_MISC_IRQ_WATCHDOG,
2182 + }
2183 +};
2184 +
2185 +static struct platform_device ar2315_wdt = {
2186 + .id = 0,
2187 + .name = "ar2315-wdt",
2188 + .resource = ar2315_wdt_res,
2189 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2190 +};
2191 +
2192 +/*
2193 + * NB: We use mapping size that is larger than the actual flash size,
2194 + * but this shouldn't be a problem here, because the flash will simply
2195 + * be mapped multiple times.
2196 + */
2197 +static u8 __init *ar2315_flash_limit(void)
2198 +{
2199 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2200 +}
2201 +
2202 +#ifdef CONFIG_LEDS_GPIO
2203 +static struct gpio_led ar2315_leds[6];
2204 +static struct gpio_led_platform_data ar2315_led_data = {
2205 + .leds = (void *)ar2315_leds,
2206 +};
2207 +
2208 +static struct platform_device ar2315_gpio_leds = {
2209 + .name = "leds-gpio",
2210 + .id = -1,
2211 + .dev = {
2212 + .platform_data = (void *)&ar2315_led_data,
2213 + }
2214 +};
2215 +
2216 +static void __init
2217 +ar2315_init_gpio_leds(void)
2218 +{
2219 + static char led_names[6][6];
2220 + int i, led = 0;
2221 +
2222 + ar2315_led_data.num_leds = 0;
2223 + for (i = 1; i < 8; i++) {
2224 + if ((i == AR2315_RESET_GPIO) ||
2225 + (i == ar231x_board.config->reset_config_gpio))
2226 + continue;
2227 +
2228 + if (i == ar231x_board.config->sys_led_gpio)
2229 + strcpy(led_names[led], "wlan");
2230 + else
2231 + sprintf(led_names[led], "gpio%d", i);
2232 +
2233 + ar2315_leds[led].name = led_names[led];
2234 + ar2315_leds[led].gpio = i;
2235 + ar2315_leds[led].active_low = 0;
2236 + led++;
2237 + }
2238 + ar2315_led_data.num_leds = led;
2239 + platform_device_register(&ar2315_gpio_leds);
2240 +}
2241 +#else
2242 +static inline void ar2315_init_gpio_leds(void)
2243 +{
2244 +}
2245 +#endif
2246 +
2247 +int __init
2248 +ar2315_init_devices(void)
2249 +{
2250 + if (!is_2315())
2251 + return 0;
2252 +
2253 + /* Find board configuration */
2254 + ar231x_find_config(ar2315_flash_limit());
2255 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2256 +
2257 + ar2315_init_gpio_leds();
2258 + platform_device_register(&ar2315_wdt);
2259 + platform_device_register(&ar2315_spiflash);
2260 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2261 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2262 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2263 +
2264 + return 0;
2265 +}
2266 +
2267 +static void
2268 +ar2315_restart(char *command)
2269 +{
2270 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2271 +
2272 + local_irq_disable();
2273 +
2274 + /* try reset the system via reset control */
2275 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2276 +
2277 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2278 + * a workaround. Give it some time to attempt a gpio based hardware
2279 + * reset (atheros reference design workaround) */
2280 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2281 + mdelay(100);
2282 +
2283 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2284 + * workaround. Attempt to jump to the mips reset location -
2285 + * the boot loader itself might be able to recover the system */
2286 + mips_reset_vec();
2287 +}
2288 +
2289 +/*
2290 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2291 + * to determine the predevisor value.
2292 + */
2293 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2294 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2295 +
2296 +static unsigned int __init
2297 +ar2315_sys_clk(unsigned int clock_ctl)
2298 +{
2299 + unsigned int pllc_ctrl, cpu_div;
2300 + unsigned int pllc_out, refdiv, fdiv, divby2;
2301 + unsigned int clk_div;
2302 +
2303 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2304 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2305 + refdiv = clockctl1_predivide_table[refdiv];
2306 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2307 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2308 + divby2 += 1;
2309 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2310 +
2311 + /* clkm input selected */
2312 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2313 + case 0:
2314 + case 1:
2315 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2316 + PLLC_CLKM_DIV_S];
2317 + break;
2318 + case 2:
2319 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2320 + PLLC_CLKC_DIV_S];
2321 + break;
2322 + default:
2323 + pllc_out = 40000000;
2324 + clk_div = 1;
2325 + break;
2326 + }
2327 +
2328 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2329 + cpu_div = cpu_div * 2 ?: 1;
2330 +
2331 + return pllc_out / (clk_div * cpu_div);
2332 +}
2333 +
2334 +static inline unsigned int
2335 +ar2315_cpu_frequency(void)
2336 +{
2337 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2338 +}
2339 +
2340 +static inline unsigned int
2341 +ar2315_apb_frequency(void)
2342 +{
2343 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2344 +}
2345 +
2346 +void __init
2347 +ar2315_time_init(void)
2348 +{
2349 + if (!is_2315())
2350 + return;
2351 +
2352 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2353 +}
2354 +
2355 +void __init
2356 +ar2315_prom_init(void)
2357 +{
2358 + u32 memsize, memcfg, devid;
2359 +
2360 + if (!is_2315())
2361 + return;
2362 +
2363 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2364 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2365 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2366 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2367 + memsize <<= 3;
2368 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2369 +
2370 + /* Detect the hardware based on the device ID */
2371 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2372 + switch (devid) {
2373 + case 0x91: /* Need to check */
2374 + ar231x_devtype = DEV_TYPE_AR2318;
2375 + break;
2376 + case 0x90:
2377 + ar231x_devtype = DEV_TYPE_AR2317;
2378 + break;
2379 + case 0x87:
2380 + ar231x_devtype = DEV_TYPE_AR2316;
2381 + break;
2382 + case 0x86:
2383 + default:
2384 + ar231x_devtype = DEV_TYPE_AR2315;
2385 + break;
2386 + }
2387 + ar231x_board.devid = devid;
2388 +}
2389 +
2390 +void __init
2391 +ar2315_plat_setup(void)
2392 +{
2393 + u32 config;
2394 +
2395 + if (!is_2315())
2396 + return;
2397 +
2398 + /* Clear any lingering AHB errors */
2399 + config = read_c0_config();
2400 + write_c0_config(config & ~0x3);
2401 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2402 + ar231x_read_reg(AR2315_AHB_ERR1);
2403 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2404 +
2405 + _machine_restart = ar2315_restart;
2406 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2407 + ar2315_apb_frequency());
2408 +}
2409 --- /dev/null
2410 +++ b/arch/mips/ath25/ar2315.h
2411 @@ -0,0 +1,37 @@
2412 +#ifndef __AR2315_H
2413 +#define __AR2315_H
2414 +
2415 +#ifdef CONFIG_SOC_AR2315
2416 +
2417 +void ar2315_irq_init(void);
2418 +int ar2315_init_devices(void);
2419 +void ar2315_prom_init(void);
2420 +void ar2315_plat_setup(void);
2421 +void ar2315_time_init(void);
2422 +
2423 +#else
2424 +
2425 +static inline void ar2315_irq_init(void)
2426 +{
2427 +}
2428 +
2429 +static inline int ar2315_init_devices(void)
2430 +{
2431 + return 0;
2432 +}
2433 +
2434 +static inline void ar2315_prom_init(void)
2435 +{
2436 +}
2437 +
2438 +static inline void ar2315_plat_setup(void)
2439 +{
2440 +}
2441 +
2442 +static inline void ar2315_time_init(void)
2443 +{
2444 +}
2445 +
2446 +#endif
2447 +
2448 +#endif
2449 --- /dev/null
2450 +++ b/arch/mips/ath25/ar5312.h
2451 @@ -0,0 +1,37 @@
2452 +#ifndef __AR5312_H
2453 +#define __AR5312_H
2454 +
2455 +#ifdef CONFIG_SOC_AR5312
2456 +
2457 +void ar5312_irq_init(void);
2458 +int ar5312_init_devices(void);
2459 +void ar5312_prom_init(void);
2460 +void ar5312_plat_setup(void);
2461 +void ar5312_time_init(void);
2462 +
2463 +#else
2464 +
2465 +static inline void ar5312_irq_init(void)
2466 +{
2467 +}
2468 +
2469 +static inline int ar5312_init_devices(void)
2470 +{
2471 + return 0;
2472 +}
2473 +
2474 +static inline void ar5312_prom_init(void)
2475 +{
2476 +}
2477 +
2478 +static inline void ar5312_plat_setup(void)
2479 +{
2480 +}
2481 +
2482 +static inline void ar5312_time_init(void)
2483 +{
2484 +}
2485 +
2486 +#endif
2487 +
2488 +#endif
2489 --- /dev/null
2490 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2491 @@ -0,0 +1,38 @@
2492 +#ifndef __ASM_MACH_ATH25_AR231X_H
2493 +#define __ASM_MACH_ATH25_AR231X_H
2494 +
2495 +#include <linux/types.h>
2496 +#include <linux/io.h>
2497 +
2498 +#define AR231X_MISC_IRQ_BASE 0x20
2499 +#define AR231X_GPIO_IRQ_BASE 0x30
2500 +
2501 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2502 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2503 +
2504 +static inline u32
2505 +ar231x_read_reg(u32 reg)
2506 +{
2507 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2508 +}
2509 +
2510 +static inline void
2511 +ar231x_write_reg(u32 reg, u32 val)
2512 +{
2513 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2514 +}
2515 +
2516 +static inline u32
2517 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2518 +{
2519 + u32 ret;
2520 +
2521 + ret = ar231x_read_reg(reg);
2522 + ret &= ~mask;
2523 + ret |= val;
2524 + ar231x_write_reg(reg, ret);
2525 +
2526 + return ret;
2527 +}
2528 +
2529 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2530 --- /dev/null
2531 +++ b/arch/mips/ath25/devices.h
2532 @@ -0,0 +1,39 @@
2533 +#ifndef __ATH25_DEVICES_H
2534 +#define __ATH25_DEVICES_H
2535 +
2536 +enum {
2537 + /* handled by ar5312.c */
2538 + DEV_TYPE_AR2312,
2539 + DEV_TYPE_AR2313,
2540 + DEV_TYPE_AR5312,
2541 +
2542 + /* handled by ar2315.c */
2543 + DEV_TYPE_AR2315,
2544 + DEV_TYPE_AR2316,
2545 + DEV_TYPE_AR2317,
2546 + DEV_TYPE_AR2318,
2547 +
2548 + DEV_TYPE_UNKNOWN
2549 +};
2550 +
2551 +extern int ar231x_devtype;
2552 +extern struct ar231x_board_config ar231x_board;
2553 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2554 +
2555 +int ar231x_find_config(u8 *flash_limit);
2556 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2557 +int ar231x_add_wmac(int nr, u32 base, int irq);
2558 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2559 + int irq, void *pdata);
2560 +
2561 +static inline bool is_2315(void)
2562 +{
2563 + return (current_cpu_data.cputype == CPU_4KEC);
2564 +}
2565 +
2566 +static inline bool is_5312(void)
2567 +{
2568 + return !is_2315();
2569 +}
2570 +
2571 +#endif
2572 --- /dev/null
2573 +++ b/arch/mips/ath25/devices.c
2574 @@ -0,0 +1,181 @@
2575 +#include <linux/kernel.h>
2576 +#include <linux/init.h>
2577 +#include <linux/serial.h>
2578 +#include <linux/serial_core.h>
2579 +#include <linux/serial_8250.h>
2580 +#include <linux/platform_device.h>
2581 +#include <asm/bootinfo.h>
2582 +
2583 +#include <ath25_platform.h>
2584 +#include <ar231x.h>
2585 +#include "devices.h"
2586 +#include "ar5312.h"
2587 +#include "ar2315.h"
2588 +
2589 +struct ar231x_board_config ar231x_board;
2590 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2591 +
2592 +static struct resource ar231x_eth0_res[] = {
2593 + {
2594 + .name = "eth0_membase",
2595 + .flags = IORESOURCE_MEM,
2596 + },
2597 + {
2598 + .name = "eth0_mii",
2599 + .flags = IORESOURCE_MEM,
2600 + },
2601 + {
2602 + .name = "eth0_irq",
2603 + .flags = IORESOURCE_IRQ,
2604 + }
2605 +};
2606 +
2607 +static struct resource ar231x_eth1_res[] = {
2608 + {
2609 + .name = "eth1_membase",
2610 + .flags = IORESOURCE_MEM,
2611 + },
2612 + {
2613 + .name = "eth1_mii",
2614 + .flags = IORESOURCE_MEM,
2615 + },
2616 + {
2617 + .name = "eth1_irq",
2618 + .flags = IORESOURCE_IRQ,
2619 + }
2620 +};
2621 +
2622 +static struct platform_device ar231x_eth[] = {
2623 + {
2624 + .id = 0,
2625 + .name = "ar231x-eth",
2626 + .resource = ar231x_eth0_res,
2627 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2628 + },
2629 + {
2630 + .id = 1,
2631 + .name = "ar231x-eth",
2632 + .resource = ar231x_eth1_res,
2633 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2634 + }
2635 +};
2636 +
2637 +static struct resource ar231x_wmac0_res[] = {
2638 + {
2639 + .name = "wmac0_membase",
2640 + .flags = IORESOURCE_MEM,
2641 + },
2642 + {
2643 + .name = "wmac0_irq",
2644 + .flags = IORESOURCE_IRQ,
2645 + }
2646 +};
2647 +
2648 +static struct resource ar231x_wmac1_res[] = {
2649 + {
2650 + .name = "wmac1_membase",
2651 + .flags = IORESOURCE_MEM,
2652 + },
2653 + {
2654 + .name = "wmac1_irq",
2655 + .flags = IORESOURCE_IRQ,
2656 + }
2657 +};
2658 +
2659 +static struct platform_device ar231x_wmac[] = {
2660 + {
2661 + .id = 0,
2662 + .name = "ar231x-wmac",
2663 + .resource = ar231x_wmac0_res,
2664 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2665 + .dev.platform_data = &ar231x_board,
2666 + },
2667 + {
2668 + .id = 1,
2669 + .name = "ar231x-wmac",
2670 + .resource = ar231x_wmac1_res,
2671 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2672 + .dev.platform_data = &ar231x_board,
2673 + },
2674 +};
2675 +
2676 +static const char * const devtype_strings[] = {
2677 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2678 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2679 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2680 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2681 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2682 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2683 + [DEV_TYPE_AR2318] = "Atheros AR2318",
2684 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2685 +};
2686 +
2687 +const char *get_system_type(void)
2688 +{
2689 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2690 + !devtype_strings[ar231x_devtype])
2691 + return devtype_strings[DEV_TYPE_UNKNOWN];
2692 + return devtype_strings[ar231x_devtype];
2693 +}
2694 +
2695 +int __init
2696 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2697 + int irq, void *pdata)
2698 +{
2699 + struct resource *res;
2700 +
2701 + ar231x_eth[nr].dev.platform_data = pdata;
2702 + res = &ar231x_eth[nr].resource[0];
2703 + res->start = base;
2704 + res->end = base + 0x2000 - 1;
2705 + res++;
2706 + res->name = mii_name;
2707 + res->start = mii_base;
2708 + res->end = mii_base + 8 - 1;
2709 + res++;
2710 + res->start = irq;
2711 + res->end = irq;
2712 + return platform_device_register(&ar231x_eth[nr]);
2713 +}
2714 +
2715 +void __init
2716 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2717 +{
2718 + struct uart_port s;
2719 +
2720 + memset(&s, 0, sizeof(s));
2721 +
2722 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2723 + s.iotype = UPIO_MEM32;
2724 + s.irq = irq;
2725 + s.regshift = 2;
2726 + s.mapbase = mapbase;
2727 + s.uartclk = uartclk;
2728 +
2729 + early_serial_setup(&s);
2730 +}
2731 +
2732 +int __init
2733 +ar231x_add_wmac(int nr, u32 base, int irq)
2734 +{
2735 + struct resource *res;
2736 +
2737 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2738 + res = &ar231x_wmac[nr].resource[0];
2739 + res->start = base;
2740 + res->end = base + 0x10000 - 1;
2741 + res++;
2742 + res->start = irq;
2743 + res->end = irq;
2744 + return platform_device_register(&ar231x_wmac[nr]);
2745 +}
2746 +
2747 +static int __init ar231x_register_devices(void)
2748 +{
2749 + ar5312_init_devices();
2750 + ar2315_init_devices();
2751 +
2752 + return 0;
2753 +}
2754 +
2755 +device_initcall(ar231x_register_devices);
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