target/linux/bcm27xx/patches-5.10/950-0389-drm-vc4-Correct-DSI-register-definition.patch

   1 From 264515dcb2a318072530a2171c084dc207006399 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Mon, 30 Nov 2020 16:16:03 +0000
   4 Subject: [PATCH] drm/vc4: Correct DSI register definition
   5
   6 The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register
   7 definitions were swapped, so trying to use more than a single data
   8 lane failed as lane 1 would get powered down.
   9 (In theory a 4 lane device would work as all lanes would remain
  10 powered).
  11
  12 Correct the definitions.
  13
  14 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  15 ---
  16  drivers/gpu/drm/vc4/vc4_dsi.c | 4 ++--
  17  1 file changed, 2 insertions(+), 2 deletions(-)
  18
  19 --- a/drivers/gpu/drm/vc4/vc4_dsi.c
  20 +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
  21 @@ -306,11 +306,11 @@
  22  # define DSI0_PHY_AFEC0_RESET                  BIT(11)
  23  # define DSI1_PHY_AFEC0_PD_BG                  BIT(11)
  24  # define DSI0_PHY_AFEC0_PD                     BIT(10)
  25 -# define DSI1_PHY_AFEC0_PD_DLANE3              BIT(10)
  26 +# define DSI1_PHY_AFEC0_PD_DLANE1              BIT(10)
  27  # define DSI0_PHY_AFEC0_PD_BG                  BIT(9)
  28  # define DSI1_PHY_AFEC0_PD_DLANE2              BIT(9)
  29  # define DSI0_PHY_AFEC0_PD_DLANE1              BIT(8)
  30 -# define DSI1_PHY_AFEC0_PD_DLANE1              BIT(8)
  31 +# define DSI1_PHY_AFEC0_PD_DLANE3              BIT(8)
  32  # define DSI_PHY_AFEC0_PTATADJ_MASK            VC4_MASK(7, 4)
  33  # define DSI_PHY_AFEC0_PTATADJ_SHIFT           4
  34  # define DSI_PHY_AFEC0_CTATADJ_MASK            VC4_MASK(3, 0)