target/linux/bcm27xx/patches-5.10/950-0720-drm-vc4-Increase-the-core-clock-based-on-HVS-load.patch

   1 From cf8b55ab71c780cefff2c152949303e82559701c Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Mon, 26 Jul 2021 18:03:53 +0100
   4 Subject: [PATCH] drm/vc4: Increase the core clock based on HVS load
   5
   6 Depending on a given HVS output (HVS to PixelValves) and input (planes
   7 attached to a channel) load, the HVS needs for the core clock to be
   8 raised above its boot time default.
   9
  10 Failing to do so will result in a vblank timeout and a stalled display
  11 pipeline.
  12
  13 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  14 ---
  15  drivers/gpu/drm/vc4/vc4_crtc.c |  15 +++++
  16  drivers/gpu/drm/vc4/vc4_drv.h  |   3 +
  17  drivers/gpu/drm/vc4/vc4_kms.c  | 116 ++++++++++++++++++++++++++++++++-
  18  3 files changed, 131 insertions(+), 3 deletions(-)
  19
  20 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  21 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  22 @@ -660,12 +660,27 @@ static int vc4_crtc_atomic_check(struct
  23         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
  24         struct drm_connector *conn;
  25         struct drm_connector_state *conn_state;
  26 +       struct drm_encoder *encoder;
  27         int ret, i;
  28
  29         ret = vc4_hvs_atomic_check(crtc, state);
  30         if (ret)
  31                 return ret;
  32
  33 +       encoder = vc4_get_crtc_encoder(crtc, crtc_state);
  34 +       if (encoder) {
  35 +               const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
  36 +               struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
  37 +
  38 +               mode = &crtc_state->adjusted_mode;
  39 +               if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
  40 +                       vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,
  41 +                                                 mode->clock * 9 / 10) * 1000;
  42 +               } else {
  43 +                       vc4_state->hvs_load = mode->clock * 1000;
  44 +               }
  45 +       }
  46 +
  47         for_each_new_connector_in_state(state, conn, conn_state,
  48                                         i) {
  49                 if (conn_state->crtc != crtc)
  50 --- a/drivers/gpu/drm/vc4/vc4_drv.h
  51 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
  52 @@ -326,6 +326,7 @@ struct vc4_hvs {
  53         u32 __iomem *dlist;
  54
  55         struct clk *core_clk;
  56 +       struct clk_request *core_req;
  57
  58         /* Memory manager for CRTCs to allocate space in the display
  59          * list.  Units are dwords.
  60 @@ -537,6 +538,8 @@ struct vc4_crtc_state {
  61                 unsigned int bottom;
  62         } margins;
  63
  64 +       unsigned long hvs_load;
  65 +
  66         /* Transitional state below, only valid during atomic commits */
  67         bool update_muxing;
  68  };
  69 --- a/drivers/gpu/drm/vc4/vc4_kms.c
  70 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
  71 @@ -40,6 +40,9 @@ static struct vc4_ctm_state *to_vc4_ctm_
  72  struct vc4_hvs_state {
  73         struct drm_private_state base;
  74         unsigned int unassigned_channels;
  75 +       unsigned int num_outputs;
  76 +       unsigned long fifo_load;
  77 +       unsigned long core_clock_rate;
  78  };
  79
  80  static struct vc4_hvs_state *
  81 @@ -186,6 +189,19 @@ vc4_ctm_commit(struct vc4_dev *vc4, stru
  82  }
  83
  84  static struct vc4_hvs_state *
  85 +vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
  86 +{
  87 +       struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  88 +       struct drm_private_state *priv_state;
  89 +
  90 +       priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
  91 +       if (IS_ERR(priv_state))
  92 +               return ERR_CAST(priv_state);
  93 +
  94 +       return to_vc4_hvs_state(priv_state);
  95 +}
  96 +
  97 +static struct vc4_hvs_state *
  98  vc4_hvs_get_global_state(struct drm_atomic_state *state)
  99  {
 100         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 101 @@ -312,10 +328,15 @@ vc4_atomic_complete_commit(struct drm_at
 102         struct vc4_dev *vc4 = to_vc4_dev(dev);
 103         struct vc4_hvs *hvs = vc4->hvs;
 104         struct drm_crtc_state *new_crtc_state;
 105 +       struct vc4_hvs_state *hvs_state;
 106         struct drm_crtc *crtc;
 107         struct clk_request *core_req;
 108         int i;
 109
 110 +       hvs_state = vc4_hvs_get_new_global_state(state);
 111 +       if (WARN_ON(!hvs_state))
 112 +               return;
 113 +
 114         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 115                 struct vc4_crtc_state *vc4_crtc_state;
 116
 117 @@ -326,9 +347,20 @@ vc4_atomic_complete_commit(struct drm_at
 118                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 119         }
 120
 121 -       if (vc4->hvs && vc4->hvs->hvs5)
 122 +       if (vc4->hvs && vc4->hvs->hvs5) {
 123 +               /*
 124 +                * Do a temporary request on the core clock during the
 125 +                * modeset.
 126 +                */
 127                 core_req = clk_request_start(hvs->core_clk, 500000000);
 128
 129 +               /*
 130 +                * And remove the previous one based on the HVS
 131 +                * requirements if any.
 132 +                */
 133 +               clk_request_done(hvs->core_req);
 134 +       }
 135 +
 136         drm_atomic_helper_wait_for_fences(dev, state, false);
 137
 138         drm_atomic_helper_wait_for_dependencies(state);
 139 @@ -358,8 +390,20 @@ vc4_atomic_complete_commit(struct drm_at
 140
 141         drm_atomic_helper_commit_cleanup_done(state);
 142
 143 -       if (vc4->hvs && vc4->hvs->hvs5)
 144 +       if (vc4->hvs && vc4->hvs->hvs5) {
 145 +               drm_dbg(dev, "Running the core clock at %lu Hz\n",
 146 +                       hvs_state->core_clock_rate);
 147 +
 148 +               /*
 149 +                * Request a clock rate based on the current HVS
 150 +                * requirements.
 151 +                */
 152 +               hvs->core_req = clk_request_start(hvs->core_clk,
 153 +                                                 hvs_state->core_clock_rate);
 154 +
 155 +               /* And drop the temporary request */
 156                 clk_request_done(core_req);
 157 +       }
 158
 159         drm_atomic_state_put(state);
 160
 161 @@ -703,6 +747,9 @@ vc4_hvs_channels_duplicate_state(struct
 162         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 163
 164         state->unassigned_channels = old_state->unassigned_channels;
 165 +       state->fifo_load = old_state->fifo_load;
 166 +       state->num_outputs = old_state->num_outputs;
 167 +       state->core_clock_rate = old_state->core_clock_rate;
 168
 169         return &state->base;
 170  }
 171 @@ -849,6 +896,65 @@ static int vc4_pv_muxing_atomic_check(st
 172  }
 173
 174  static int
 175 +vc4_core_clock_atomic_check(struct drm_atomic_state *state)
 176 +{
 177 +       struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 178 +       struct drm_private_state *priv_state;
 179 +       struct vc4_hvs_state *hvs_new_state;
 180 +       struct vc4_load_tracker_state *load_state;
 181 +       struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 182 +       struct drm_crtc *crtc;
 183 +       unsigned long pixel_rate;
 184 +       unsigned long cob_rate;
 185 +       unsigned int i;
 186 +
 187 +       priv_state = drm_atomic_get_private_obj_state(state,
 188 +                                                     &vc4->load_tracker);
 189 +       if (IS_ERR(priv_state))
 190 +               return PTR_ERR(priv_state);
 191 +
 192 +       load_state = to_vc4_load_tracker_state(priv_state);
 193 +
 194 +       hvs_new_state = vc4_hvs_get_global_state(state);
 195 +       if (!hvs_new_state)
 196 +               return -EINVAL;
 197 +
 198 +       for_each_oldnew_crtc_in_state(state, crtc,
 199 +                                     old_crtc_state,
 200 +                                     new_crtc_state,
 201 +                                     i) {
 202 +               if (old_crtc_state->active) {
 203 +                       struct vc4_crtc_state *old_vc4_state =
 204 +                               to_vc4_crtc_state(old_crtc_state);
 205 +
 206 +                       hvs_new_state->num_outputs -= 1;
 207 +                       hvs_new_state->fifo_load -= old_vc4_state->hvs_load;
 208 +               }
 209 +
 210 +               if (new_crtc_state->active) {
 211 +                       struct vc4_crtc_state *new_vc4_state =
 212 +                               to_vc4_crtc_state(new_crtc_state);
 213 +
 214 +                       hvs_new_state->num_outputs += 1;
 215 +                       hvs_new_state->fifo_load += new_vc4_state->hvs_load;
 216 +               }
 217 +       }
 218 +
 219 +       cob_rate = hvs_new_state->fifo_load;
 220 +       pixel_rate = load_state->hvs_load;
 221 +       if (hvs_new_state->num_outputs > 1) {
 222 +               pixel_rate = (pixel_rate * 40) / 100;
 223 +       } else {
 224 +               pixel_rate = (pixel_rate * 60) / 100;
 225 +       }
 226 +
 227 +       hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate);
 228 +
 229 +       return 0;
 230 +}
 231 +
 232 +
 233 +static int
 234  vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 235  {
 236         int ret;
 237 @@ -865,7 +971,11 @@ vc4_atomic_check(struct drm_device *dev,
 238         if (ret)
 239                 return ret;
 240
 241 -       return vc4_load_tracker_atomic_check(state);
 242 +       ret = vc4_load_tracker_atomic_check(state);
 243 +       if (ret)
 244 +               return ret;
 245 +
 246 +       return vc4_core_clock_atomic_check(state);
 247  }
 248
 249  static const struct drm_mode_config_funcs vc4_mode_funcs = {