1 From d2a60430df21f213b9b9d2eb46d2f4afbbea3213 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Fri, 4 Mar 2022 16:24:00 +0100
4 Subject: [PATCH] drm/vc4: hvs: Reset muxes at probe time
6 By default, the HVS driver will force the HVS output 3 to be muxed to
7 the HVS channel 2. However, the Transposer can only be assigned to the
8 HVS channel 2, so whenever we try to use the writeback connector, we'll
9 mux its associated output (Output 2) to the channel 2.
11 This leads to both the output 2 and 3 feeding from the same channel,
12 which is explicitly discouraged in the documentation.
14 In order to avoid this, let's reset all the output muxes to their reset
17 Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically")
18 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
20 drivers/gpu/drm/vc4/vc4_hvs.c | 26 +++++++++++++++++++++-----
21 1 file changed, 21 insertions(+), 5 deletions(-)
23 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
24 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
25 @@ -1017,6 +1017,7 @@ static int vc4_hvs_bind(struct device *d
26 struct vc4_hvs *hvs = NULL;
31 hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
33 @@ -1090,6 +1091,26 @@ static int vc4_hvs_bind(struct device *d
37 + reg = HVS_READ(SCALER_DISPECTRL);
38 + reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK;
39 + HVS_WRITE(SCALER_DISPECTRL,
40 + reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));
42 + reg = HVS_READ(SCALER_DISPCTRL);
43 + reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
44 + HVS_WRITE(SCALER_DISPCTRL,
45 + reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX));
47 + reg = HVS_READ(SCALER_DISPEOLN);
48 + reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK;
49 + HVS_WRITE(SCALER_DISPEOLN,
50 + reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX));
52 + reg = HVS_READ(SCALER_DISPDITHER);
53 + reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK;
54 + HVS_WRITE(SCALER_DISPDITHER,
55 + reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX));
57 dispctrl = HVS_READ(SCALER_DISPCTRL);
59 dispctrl |= SCALER_DISPCTRL_ENABLE;
60 @@ -1097,10 +1118,6 @@ static int vc4_hvs_bind(struct device *d
61 SCALER_DISPCTRL_DISPEIRQ(1) |
62 SCALER_DISPCTRL_DISPEIRQ(2);
64 - /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
67 - dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
68 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
69 SCALER_DISPCTRL_SLVWREIRQ |
70 SCALER_DISPCTRL_SLVRDEIRQ |
71 @@ -1114,7 +1131,6 @@ static int vc4_hvs_bind(struct device *d
72 SCALER_DISPCTRL_DSPEISLUR(1) |
73 SCALER_DISPCTRL_DSPEISLUR(2) |
74 SCALER_DISPCTRL_SCLEIRQ);
75 - dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
77 HVS_WRITE(SCALER_DISPCTRL, dispctrl);